ICS8737-11 Integrated Circuit Systems, Inc. ÷2 LOW SKEW ÷1/÷ DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/ HiPerClockS™ Divider and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8737-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. • 2 divide by 1 differential 3.3V LVPECL outputs; 2 divide by 2 differential 3.3V LVPECL outputs ,&6 • Selectable CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency up to 650MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input Guaranteed output and part-to-part skew characteristics make the ICS8737-11 ideal for clock distribution applications demanding well defined performance and repeatability. • Output skew: 60ps (maximum) • Part-to-part skew: 200ps (maximum) • Bank skew: Bank A - 20ps (maximum), Bank B - 35ps (maximum) • Propagation delay: 1.7ns (maximum) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT QA0 nQA0 D CLK_EN QA1 nQA1 Q LE CLK nCLK PCLK nPCLK CLK_SEL MR 8737AG-11 VEE CLK_EN CLK_SEL CLK nCLK PCLK nPCLK nc MR VCC 0 ÷1 1 ÷2 QB0 nQB0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 QA0 nQA0 VCC QA1 nQA1 QB0 nQB0 VCC QB1 nQB1 ICS8737-11 QB1 nQB1 20-Lead TSSOP 6.50mm x 4.40mm x 0.92 package body G Package Top View www.icst.com/products/hiperclocks.html 1 REV. A JULY 13, 2001 ICS8737-11 Integrated Circuit Systems, Inc. ÷2 LOW SKEW ÷1/÷ DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name Type 1 VEE Power 2 CLK_EN Power 3 CLK_SEL Input 4 CLK Input Description Negative supply pin. Connect to ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. Clock Select input. When HIGH, selects PCLK, nPCLK inputs. Pulldown When LOW, selects CLK, nCLK inputs. LVTTL / LVCMOS interface levels. Pulldown Non-inver ting differential clock input. 5 nCLK Input Pullup Inver ting differential clock input. 6 PCLK Input Pulldown Non-inver ting differential LVPECL clock input. 7 nPCLK Input Pullup Inver ting differential LVPECL clock input. 8 nc Unused No connect. 9 MR Input Pulldown Master reset. Resets the output divider. Power Positive supply pins. Connect to 3.3V. 10, 13, 18 VCC 11, 12 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 14, 15 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 16, 17 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 19, 20 nQA0, QA0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical CLK, nCLK RPULLUP PCLK, nPCLK CLK_SEL, CLK_EN, MR Input Pullup Resistor 51 RPULLDOWN Input Pulldown Resistor 51 CIN 8737AG-11 Input Capacitance www.icst.com/products/hiperclocks.html 2 Maximum Units 4 pF 4 pF 4 pF KW KW REV. A JULY 13, 2001 ICS8737-11 Integrated Circuit Systems, Inc. ÷2 LOW SKEW ÷1/÷ DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Outputs MR CLK_EN CLK_SEL Selected Source QA0 thru QA1 nQA0 thru nQA1 QB0 thru QB1 nQB0 thru nQB1 1 X X X LOW HIGH LOW HIGH 0 0 0 CLK, nCLK Disabled; LOW Disabled; HIGH Disabled; LOW Disabled; HIGH 0 0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH Disabled; LOW Disabled; HIGH 0 1 0 CLK, nCLK Enabled Enabled Enabled Enabled 0 1 1 PCLK, nPCLK Enabled Enabled Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown if Figure 1. In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described in Table 3B. Enabled Disabled nCLK, nPCLK CLK, PCLK CLK_EN nQA0 - nQA1, nQB0 - nQB1 QA0 - QA1, QB0 - QB1 FIGURE 1: CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs CLK or PCLK nCLK or nPCLK QAx nQAx 0 1 0 LOW 1 HIGH 0 1 Biased; NOTE 1 LOW Biased; NOTE 1 HIGH Biased; NOTE 1 0 HIGH Input to Output Mode Polarity HIGH Differential to Differential Non Inver ting LOW Differential to Differential Non Inver ting LOW HIGH Single Ended to Differential Non Inver ting HIGH LOW Single Ended to Differential Non Inver ting LOW Single Ended to Differential Inver ting QBx nQBx HIGH LOW LOW HIGH HIGH LOW LOW HIGH Biased; NOTE 1 1 LOW HIGH LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section on page 8, Figure 9, which discusses wiring differential input to accept single ended levels. 8737AG-11 www.icst.com/products/hiperclocks.html 3 REV. A JULY 13, 2001 ICS8737-11 Integrated Circuit Systems, Inc. ÷2 LOW SKEW ÷1/÷ DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI Outputs, VO Package Thermal Impedance, θ JA Storage Temperature, TSTG -0.5V to VCC + 0.5V -0.5V to VCC + 0.5V 73.2°C/W (0lfpm) -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VCC Positive Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 50 mA Maximum Units TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH CLK_EN, CLK_SEL, MR 2 3.765 V VIL CLK_EN, CLK_SEL, MR -0.3 0.8 V IIH Input High Current 5 µA IIL Input Low Current Test Conditions Minimum Typical VIN = VCC = 3.465V CLK_EN CLK_SEL, MR VIN = VCC = 3.465V 150 µA CLK_EN VIN = 0V, VCC = 3.465V -150 µA CLK_SEL,MR VIN = 0V, VCC = 3.465V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Maximum Units nCLK VIN = VCC = 3.465V Test Conditions Minimum Typical 5 µA CLK VIN = VCC = 3.465V 150 µA nCLK VIN = 0V, VCC = 3.465V -150 µA CLK VIN = 0V, VCC = 3.465V -5 µA Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. VPP 8737AG-11 www.icst.com/products/hiperclocks.html 4 1.3 V VCC - 0.85 V REV. A JULY 13, 2001 ICS8737-11 Integrated Circuit Systems, Inc. ÷2 LOW SKEW ÷1/÷ DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Test Conditions Input Low Current Typical VIN = VCC = 3.465V Input High Current IIL Minimum VIN = VCC = 3.465V Maximum Units 150 µA 5 µA VIN = 0V, VCC = 3.465V -5 µA VIN = 0V, VCC = 3.465V -150 µA VPP Peak-to-Peak Input Voltage 0.3 1 V VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 1.5 VCC V VOH Output High Voltage; NOTE 3 VCC - 1.4 VCC - 1.0 V VOL Output Low Voltage; NOTE 3 VCC - 2.0 VCC - 1.7 V 0.9 V VSWING Peak-to-Peak Output Voltage Swing 0.65 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50W to VCC - 2V. TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions fMAX Maximum Output Frequency tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 t sk(b) Bank Skew; NOTE 4 t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 tR Output Rise Time 20% to 80% @ 50MHz tF Output Fall Time 20% to 80% @ 50MHz CLK, nCLK ƒ £ 650MHz PCLK, nPCLK Minimum Typical Maximum Units 650 MHz 1.3 1.7 ns 1.2 1.6 Bank A Bank B ps 20 ps 35 200 ps 300 700 ps 300 700 ps 52 % odc Output Duty Cycle 48 50 All parameters measured at 500MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8737AG-11 60 www.icst.com/products/hiperclocks.html 5 REV. A JULY 13, 2001 ICS8737-11 Integrated Circuit Systems, Inc. ÷2 LOW SKEW ÷1/÷ DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION V CC SCOPE Qx LVPECL VCC = 2.0V nQx VEE = -1.3V ± 0.135V FIGURE 2 - OUTPUT LOAD TEST CIRCUIT VCC CLK, PCLK V Cross Points PP V CMR nCLK, nPCLK VEE FIGURE 3 - DIFFERENTIAL INPUT LEVEL Qx nQx Qy nQy tsk(o) FIGURE 4 - OUTPUT SKEW 8737AG-11 www.icst.com/products/hiperclocks.html 6 REV. A JULY 13, 2001 ICS8737-11 Integrated Circuit Systems, Inc. ÷2 LOW SKEW ÷1/÷ DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR Qx PART 1 nQx Qy PART 2 nQy tsk(pp) FIGURE 5 - PART-TO-PART SKEW 80% 80% V 20% SWING 20% Clock Inputs and Outputs t t R FIGURE 6 - INPUT AND OUTPUT RISE AND F FALL TIME CLK, PCLK nCLK, nPCLK Q0A0, Q0A1 Q0B0, Q0B1 nQ0A0, nQ0A1 nQ0B0, nQ0B1 t PD FIGURE 7 - PROPAGATION DELAY CLK, PCLK nCLK, nPCLK Pulse Width t t odc = t PERIOD PW PERIOD FIGURE 8 - odc & tPERIOD 8737AG-11 www.icst.com/products/hiperclocks.html 7 REV. A JULY 13, 2001 ICS8737-11 Integrated Circuit Systems, Inc. ÷2 LOW SKEW ÷1/÷ DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 9 shows how the differential input can be wired to accept single end levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 12.5V and VCC = 3.3V, V_REF should be 1.25V and R2/ R1 = 0.609. VCC R1 1K CLK_IN + V_REF - C1 0.1uF R2 1K FIGURE 9 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8737AG-11 www.icst.com/products/hiperclocks.html 8 REV. A JULY 13, 2001 ICS8737-11 Integrated Circuit Systems, Inc. ÷2 LOW SKEW ÷1/÷ DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8737-11. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8737-11 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * ICC_MAX = 3.465V * 50mA = 173.25mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 120.8mW = 294.05mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.294W * 66.6°C/W = 89.58°C. This is well below the limit of 125°C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 20-pin TSSOP, Forced Convection θ by Velocity (Linear Feet per Minute) JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8737AG-11 www.icst.com/products/hiperclocks.html 9 REV. A JULY 13, 2001 ICS8737-11 Integrated Circuit Systems, Inc. ÷2 LOW SKEW ÷1/÷ DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR 3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 10. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 10 - LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. – (V Pd_H = [(V OH_MAX Pd_L = [(V - 2V))/R ] * (V CC_MAX – (V OL_MAX L -V CC_MAX - 2V))/R ] * (V CC_MAX • For logic high, V L =V OH_MAX – 1.0V CC_MAX CC_MAX = 2.465V OH_MAX • For logic low, V =V OUT CC_MAX ) OL_MAX = 3.465, this results in V Using V Using V -V CC_MAX =V OUT ) OH_MAX OL_MAX =V – 1.7V CC_MAX = 3.465, this results in V = 1.765V OL_MAX Pd_H = [(2.465V - (3.465V - 2V))/50 Ω] * (3.465V - 2.465V) = 20.0mW Pd_L = [(1.765V - (3.465V - 2V))/50 Ω] * (3.465V - 1.765V) = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 8737AG-11 www.icst.com/products/hiperclocks.html 10 REV. A JULY 13, 2001 ICS8737-11 Integrated Circuit Systems, Inc. ÷2 LOW SKEW ÷1/÷ DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE θ by Velocity (Linear Feet per Minute) JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8737-11 is: 510 8737AG-11 www.icst.com/products/hiperclocks.html 11 REV. A JULY 13, 2001 ICS8737-11 Integrated Circuit Systems, Inc. ÷2 LOW SKEW ÷1/÷ DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR PACKAGE OUTLINE - G SUFFIX TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 a 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 8737AG-11 www.icst.com/products/hiperclocks.html 12 REV. A JULY 13, 2001 ICS8737-11 Integrated Circuit Systems, Inc. ÷2 LOW SKEW ÷1/÷ DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR TABLE 9. ORDERING INFORMATION Part/Order Number ICS8737AG-11 ICS8737AG-11T Marking ICS8737AG-11 ICS8737AG-11 Package 20 lead TSSOP 20 lead TSSOP on Tape and Reel Count 72 2500 Temperature 0°C to 70°C 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8737AG-11 www.icst.com/products/hiperclocks.html 13 REV. A JULY 13, 2001