ICS8533-11 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8533-11 is a low skew, high performance ,&6 1-to-4 Crystal Oscillator/Differential-to-3.3V HiPerClockS™ LVPECL fanout buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8533-11 has selectable differential clock or crystal inputs. The CLK, nCLK pair can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. • 4 differential 3.3V LVPECL outputs Guaranteed output and part-to-part skew characteristics make the ICS8533-11 ideal for those applications demanding well defined performance and repeatability. • Part-to-part skew: 150ps (maximum) • Selectable CLK, nCLK or crystal inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency up to 650MHz • Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input • Output skew: 30ps (maximum) • Propagation delay: 2ns (maximum) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT VEE CLK_EN CLK_SEL CLK nCLK XTAL1 XTAL2 nc nc VCC D CLK_EN Q LE CLK nCLK XTAL1 XTAL2 CLK_SEL 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VCC Q1 nQ1 Q2 nQ2 VCC Q3 nQ3 ICS8533-11 Q3 nQ3 8533AG-11 1 2 3 4 5 6 7 8 9 10 20-Lead TSSOP 6.5mm x 4.4mm x 0.92 Package Body G Package Top View www.icst.com/products/hiperclocks.html 1 REV. D JULY 16, 2001 ICS8533-11 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type 1 VEE Power 2 CLK_EN Input Pullup 3 CLK_SEL Input Pulldown 4 CLK Input Pulldown 5 nCLK Input Pullup 6 XTAL1 Input Pulldown Pullup Description Negative supply pin. Connect to ground. Synchroning clock enable. When HIGH, clock outputs follows clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When LOW, selects CLK, nCLK input. When HIGH, selects XTAL input. LVCMOS / LVTTL interface levels. Non-inver ting differential clock input. Inver ting differential clock input. Crystal oscillator input. 7 XTAL2 Input 8, 9 nc Unused Crystal oscillator input. 10, 13, 18 VCC Power Positive supply pins. Connect to 3.3V. 11, 12 nQ3, Q3 Output Differential clock outputs. LVPECL interface levels. 14, 15 nQ2, Q2 Output Differential clock outputs. LVPECL interface levels. 16, 17 nQ1, Q1 Output Differential clock outputs. LVPECL interface levels. 19, 20 nQ0, Q0 Output Differential clock outputs. LVPECL interface levels. No connect. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Maximum Units CLK, nCLK Test Conditions Minimum Typical 4 pF CLK_EN, CLK_SEL 4 pF CIN Input Capacitance RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ REV. D JULY 16, 2001 2 ICS8533-11 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Outputs CLK_EN CLK_SEL Selected Source Q0 thru Q3 nQ0 thru nQ3 0 0 CLK, nCLK Disabled; LOW Disabled; HIGH 0 1 XTAL1, XTAL2 Disabled; LOW Disabled; HIGH 1 0 CLK, nCLK Enabled Enabled 1 1 XTAL1, XTAL2 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled folowing a rising and falling input clock or crystal oscillator edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and XTAL1, XTAL2 inputs as described in Table 3B. Enabled Disabled nCLK CLK CLK_EN nQ0 - nQ3 Q0 - Q3 FIGURE 1 - CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs CLK nCLK Q0 thru Q3 nQ0 thru nQ3 0 1 LOW HIGH Input to Output Mode Polarity Differential to Differential Non Inver ting 1 0 HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1:Please refer to the Application Information section on page 10, Figure 12, which discusses wiring the differential input to accept single ended levels. 8533AG-11 www.icst.com/products/hiperclocks.html 3 REV. D JULY 16, 2001 ICS8533-11 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCCx Inputs, VI Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5V -0.5V to VCC + 0.5V 73.2°C/W (0lfpm) -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VCC Power Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 50 mA Maximum Units 2 3.765 V -0.3 0.8 V TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical CLK_EN, CLK_SEL CLK_EN, CLK_SEL CLK_EN VIN = VCC = 3.465V 5 µA CLK_SEL VIN = VCC = 3.465V 150 µA CLK_EN VIN = 0V, VCC = 3.465V -150 µA CLK_SEL VIN = 0V, VCC = 3.465V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol IIH IIL Parameter Input High Current Input Low Current Test Conditions nCLK Minimum Typical VCC = VIN = 3.465V Units 5 µA 150 µA CLK VCC = VIN = 3.465V nCLK VCC = 3.465V, VIN = 0V -150 µA CLK VCC = 3.465V, VIN = 0V -5 µA Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE1: For single ended applications the maximum input voltage for CLK and nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. VPP REV. D Maximum JULY 16, 2001 4 1.3 V VCC - 0.85 V ICS8533-11 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units VCC - 1.4 VCC - 1.0 V VCC - 2.0 VCC - 1.7 V 0.6 0.85 V Maximum Units NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Typical Mode of Oscillation Fundamental Frequency Tolerance -50 Frequency Stability -100 Drive Level 50 ppm 100 ppm 0.1 Equivalent Series Resistance (ESR) 80 Ω 7 pF 3 7 nH 50 Shunt Capacitance Series Pin Inductance Operating Temperature Range Aging Per year @ 25°C Frequency Range mW 0 70 °C -5 5 ppm 14 25 MHz Maximum Units 650 MHz 2.0 ns TABLE 6. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Maximum Input Frequency tPD Propagation Delay; NOTE 1 Test Conditions ƒ≤ 650MHz Minimum Typical 1.0 t sk(o) Output Skew; NOTE 2, 5 30 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 5 150 ps tR Output Rise Time 20% to 80% @ 50MHz 300 700 ps tF Output Fall Time 20% to 80% @ 50MHzz 300 700 ps odc Output Duty Cycle; NOTE 4 53 % 47 50 oscTOL Crystal Oscillator Tollerance TBD All parameters measured at 500MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: Measured using CLK. For XTAL input, refer to Application Note. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 8533AG-11 www.icst.com/products/hiperclocks.html 5 REV. D ppm JULY 16, 2001 ICS8533-11 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION V CC SCOPE Qx LVPECL VCC = 2V nQx VEE = -1.3V ± 0.135V FIGURE 2 - OUTPUT LOAD TEST CIRCUIT VCC CLK V PP Cross Points nCLK VEE FIGURE 3 - DIFFERENTIAL INPUT LEVEL REV. D JULY 16, 2001 6 V CMR ICS8533-11 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Qx nQx Qy nQy tsk(o) FIGURE 4 - OUTPUT SKEW 80% 80% V 20% SWING 20% Clock Inputs and Outputs t t R FIGURE 5 - INPUT AND F OUTPUT RISING/FALL TIME CLK nCLK Q0 - Q3 nQ0 - nQ3 t PD FIGURE 6 - PROPAGATION DELAY CLK, Q0 - Q3 nCLK, nQ0 - nQ3 Pulse Width t t odc = t PERIOD PW PERIOD FIGURE 7 - odc & tPERIOD 8533AG-11 www.icst.com/products/hiperclocks.html 7 REV. D JULY 16, 2001 ICS8533-11 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION IINFORMATION CRYSTAL OSCILLATOR CIRCUIT FREQUENCY FINE TUNING A crystal can be characterized for either series or parallel mode operation. The ICS8533-11 and ICS8535-11 fanout buffers have built-in crystal oscillator circuits that can accept either a series or parallel crystal without additional components. The frequency accuracy provided by this configuration is sufficient for most computer applications. For applications requiring highly accurate clock frequencies, the output frequency can be fine tuned by inserting a small series capacitor C1 at the XTAL1 input (Pin 6 for ICS8533-11) as shown in Figure 8. This fine tuning approach can be applied in either parallel or series crystal. The C1 value depends on the crystal type, frequency and the board layout. The parallel crystal fine tuning results in smaller ppm and better performance. It is difficult to provide the precise value of C1. This section provides recommended series capacitor C1 values to start with. This example uses 18pF parallel crystals. Figure 9shows the suggested series capacitor value for a parallel crystal. For a 16.666 MHz crystal, the recommended C1 value is about 33pF. Figure 10 shows frequency accuracy versus series capacitance for 19.44MHz, 16.666MHz and 15MHz crystals. As seen from this figure, a 24pF, 33pF and 43pF series capacitor is used to achieve the lowest ppm error for 19.44MHz, 16.666MHz and 15MHz respectively. Figure 11 shows the experiment results of crystal oscillator frequency drift due to temperature variation. U1 XTAL2 X1 C1 XTAL1 FIGURE 8 - CRYSTAL INTERFACE REV. D JULY 16, 2001 8 WITH SERIES CAPACITOR C1. ICS8533-11 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER 60 Series Capacitor, C1 (pF) 14.318 50 15.000 40 16.666 30 19.440 20.000 20 24.000 10 0 14 15 16 17 18 19 20 21 22 23 24 25 Crystal Frequency (MHz) FIGURE 9 - SUGGESTED SERIES CAPACITOR C1 FOR PARALLEL CRYSTAL Frequency Accuracy (ppm) 100 80 60 40 20 19.44MHz 0 -20 0 16.666MHz 10 20 30 40 50 60 15.00MHz -40 -60 -80 -100 Series Capacitor, C1 (pF) FIGURE 10 - FREQUENCY ACCURACY 8533AG-11 FOR PARALLEL CRYSTAL USING SERIES CAPACITOR C1 www.icst.com/products/hiperclocks.html 9 REV. D JULY 16, 2001 ICS8533-11 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Frequecy Drifted (ppm) 60 40 20 19.44MHz 0 0 10 20 30 40 50 60 70 80 16.666MHz -20 -40 -60 Temperature (deg. C) FIGURE 11 - CRYSTAL OSCILLATOR CRCUIT FREQUENCY DRIFTED DUE TO TEMPERATURE VARIATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 12 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K CLK_IN + V_REF C1 0.1uF R2 1K FIGURE 12: SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT REV. D JULY 16, 2001 10 ICS8533-11 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8533-11. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8533-11 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 50mA = 173.3mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 120.8mW = 294.1mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.294W * 66.6°C/W = 89.58°C. This is well below the limit of 125°C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 7. Thermal Resistance qJA for 20-pin TSSOP, Forced Convection qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 200 98.0°C/W 66.6°C/W 500 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8533AG-11 www.icst.com/products/hiperclocks.html 11 REV. D JULY 16, 2001 ICS8533-11 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 13 - LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX Pd_L = [(V OL_MAX • – (V CC_MAX – (V CC_MAX CC_MAX L - 2V))/R ] * (V CC_MAX L For logic high, VOUT = V OH_MAX Using V CC_MAX • - 2V))/R ] * (V -V OL_MAX =V =V CC_MAX ) ) – 1.0V CC_MAX OH_MAX OL_MAX CC_MAX OH_MAX = 3.465, this results in V For logic low, VOUT = V Using V -V = 2.465V – 1.7V = 3.465, this results in V OL_MAX = 1.765V Pd_H = [(2.465V - (3.465V - 2V))/50Ω] * (3.465V - 2.465V) = 20mW Pd_L = [(1.765V - (3.465V - 2V))/50Ω] * (3.465V - 1.765V) = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW REV. D JULY 16, 2001 12 ICS8533-11 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 200 98.0°C/W 66.6°C/W 500 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8533-11 is: 428 8533AG-11 www.icst.com/products/hiperclocks.html 13 REV. D JULY 16, 2001 ICS8533-11 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER PACKAGE OUTLINE - G SUFFIX TABLE 9. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 BASIC E1 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MS-153 REV. D JULY 16, 2001 14 ICS8533-11 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/ DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8533AG-11 ICS8533AG-11 20 lead TSSOP 72 per tube 0°C to 70°C ICS8533AG-11T ICS8533AG-11 20 lead TSSOP on Tape and Reel 2500 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8533AG-11 www.icst.com/products/hiperclocks.html 15 REV. D JULY 16, 2001