ICS93776 Integrated Circuit Systems, Inc. Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application: DDR Zero Delay Clock Buffer Pin Configuration Switching Characteristics: • CYCLE - CYCLE jitter: <100ps • OUTPUT - OUTPUT skew: <100ps • DUTY CYCLE: 48% - 52% 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ICS93776 Product Description/Features: • Low skew, low jitter PLL clock driver • Max frequency supported = 266MHz (DDR 533) • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT/C input DDRC0 DDRT0 VDD DDRT1 DDRC1 GND SCLK CLK_INT CLK_INC VDDA GND VDD DDRT2 DDRC2 GND DDRC5 DDRT5 DDRC4 DDRT4 VDD SDATA FB_INC FB_INT FB_OUTT FB_OUTC DDRT3 DDRC3 GND 28-Pin 209mil SSOP Block Diagram Functionality INPUTS FB_OUTT FB_OUTC SCLK SDA SD ATA Control DDRT0 Logic DDRC0 DDRT1 OUTPUTS AVDD CLK_INT CLKT CLKC FB_OUTT PLL State 2.5V (nom) L L H L on 2.5V (nom) H H L H on DDRC1 DDRT2 DDRC2 FB_INC DDRT3 FB_INT DDRC3 PLL CLK_INT DDRT4 DDRC4 CLK_INC DDRT5 DDRC5 0793A—03/08/05 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. ICS93776 Pin Descriptions PIN # PIN NAME PIN TYPE DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DDRC0 DDRT0 VDD DDRT1 DDRC1 GND SCLK CLK_INT CLK_INC VDDA GND VDD DDRT2 DDRC2 GND DDRC3 DDRT3 OUT OUT PWR OUT OUT PWR IN IN IN PWR PWR PWR OUT OUT PWR OUT OUT 18 FB_OUTC OUT 19 FB_OUTT OUT 20 FB_INT IN 21 FB_INC IN 22 23 24 25 26 27 28 SDATA VDD DDRT4 DDRC4 DDRT5 DDRC5 GND I/O PWR OUT OUT OUT OUT PWR "Complementary" Clock of differential pair output. "True" Clock of differential pair output. Power supply, nominal 2.5V "True" Clock of differential pair output. "Complementary" Clock of differential pair output. Ground pin. Clock pin of SMBus circuitry, 5V tolerant. "True" reference clock input. "Complementary" reference clock input. 2.5V power for the PLL core. Ground pin. Power supply, nominal 2.5V "True" Clock of differential pair output. "Complementary" Clock of differential pair output. Ground pin. "Complementary" Clock of differential pair output. "True" Clock of differential pair output. Complement single-ended feedback output, dedicated external feedback. It switches at the same frequency as other DDR outputs, This output must be connect to FB_INC. True single-ended feedback output, dedicated external feedback. It switches at the same frequency as other DDR outputs, This output must be connect to FB_INT. True single-ended feedback input, provides feedback signal to internal PLL for synchronization with CLK_INT to eliminate phase error. Complement single-ended feedback input, provides feedback signal to internal PLL for synchronization with CLK_INT to eliminate phase error. Data pin for SMBus circuitry, 5V tolerant. Power supply, nominal 2.5V "True" Clock of differential pair output. "Complementary" Clock of differential pair output. "True" Clock of differential pair output. "Complementary" Clock of differential pair output. Ground pin. 0793A—03/08/05 2 ICS93776 Absolute Maximum Ratings Supply Voltage (VDD & AVDD) . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . -0.5V to 3.6V GND –0.5 V to VDD +0.5 V 0°C to +85°C –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input / Supply / Common Output parameters TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V ± 0.20V (unless otherwise stated) PARAMETER Operating Supply Current Output High Current Output Low Current High Impedance Ouptut Current SYMBOL I DD2.5 I DDPD I OH I OL I OZ High-level Output Voltage VOH Low-level Output Voltage VOL Output Capacitance1 CONDITIONS RT = 120W, CL = 12 pF at 100MHz RT = 120W, CL = 12 pF at 133MHz CL=0 pF VDD = 2.5V, VOUT = 1V VDD = 2.5V, VOUT = 1.2V MIN TYP -48 29 VDD = 2.7V, VOUT = V DD or GND VDD = min to max, I OH = -1mA VDD = 2.3V, I OH = -12mA VDD = min to max, I OH = 1mA VDD = 2.3V, I OH = 12mA VI = V DD or GND MAX 300 300 100 -29 37 UNITS 10 mA mA mA mA mA V 2 0.1 0.4 V pF COUT 1. Guaranteed by design, not 100% tested in production. Recommended Operation Conditions TA = 0 - 70°C; Supply Voltage AV DD, V DD = 2.50V ± 0.20V (unless otherwise stated) PARAMETER SYMBOL Analog / Core Supply Voltage AV DD V IN Input Voltage Level CONDITIONS 0793A—03/08/05 3 MIN 2.3 2 TYP MAX 2.7 3 UNITS V V ICS93776 Timing Requirements TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS 1 freqop Operating Clock Frequency Input Voltage level: 0-2.50V 1 dtin Input Clock Duty Cycle 1 Clock Stabilization tSTAB from VDD = 2.5V to 1% target frequency 1. Guaranteed by design, not 100% tested in production. MIN 22 40 TYP MIN TYP 50 MAX 340 60 100 UNITS MHz % µs MAX UNITS 100 ps Switching Characteristics TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.50V ± 0.20V (unless otherwise stated) PARAMETER 1,2 Cycle to cycle Jitter SYMBOL CONDITIONS tc-c 66 MHz to 266 MHz 1 tpe -150 150 Phase Error 1 Tskew 100 Output to output Skew 1,3 DC 66 MHz to 267 MHz 48 52 Duty Cycle (Sign Ended) 4 t , t 950 Load=120Ω/14pF Rise Time, Fall Time R f Output Differential Pair VOC VDD=2.50V 1.32 1.23 Crossing Voltage 1. Guaranteed by design, not 100% tested in production. 2. Refers to transistion on non-inverting period. 3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formular: duty_cycle=twH/tC, where the cycle time (tC)decreases as the frequency increases. 0793A—03/08/05 4 ps ps % ps V ICS93776 General SMBus serial interface information How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Index Block Read Operation Index Block Write Operation Controlle r (Host) starT bit T Slave Address D4(H ) W Rite WR Controller (host) will send start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Controlle r (Host) T starT bit Slave Address D4(H ) WR W Rite ICS (Sla ve /Re ce ive r) ICS (Sla ve /Re ce ive r) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D5(H ) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 0793A—03/08/05 5 Not acknowledge stoP bit ICS93776 Bytes 2 to 6 are reseved power up default = 1. This allows operation with main clock. Affected Pin Pin # Name Bit 7 2, 1 DDR0(T&C) Bit 6 4, 5 DDR1(T&C) Bit 5 Bit 4 Bit 3 13, 14 DDR2(T&C) Bit 2 26, 27 DDR5(T&C) Bit 1 Bit 0 24, 25 DDR4(T&C) Note: PWD = Power Up Default BYTE 0 BYTE 1 Affected Pin Pin # Name Bit 7 Bit 6 16,17 DDR3(T&C) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Note: PWD = Power Up Default Control Function Type Output Control Output Control Reserved Reserved Output Control Output Control Reserved Output Control RW RW X X RW RW X RW Control Function Type Reserved Output Control Reserved Reserved Reserved Reserved Reserved Reserved X RW X X RW X RW X 0793A—03/08/05 6 Bit Control 0 1 DISABLE ENABLE DISABLE ENABLE DISABLE ENABLE DISABLE ENABLE DISABLE ENABLE PWD 1 1 1 1 1 1 1 1 Bit Control 0 1 DISABLE ENABLE - PWD 1 1 0 0 0 0 0 0 ICS93776 c N In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -2.00 -.079 A1 0.05 -.002 -A2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 SEE VARIATIONS SEE VARIATIONS D E 7.40 8.20 .291 .323 E1 5.00 5.60 .197 .220 0.65 BASIC 0.0256 BASIC e L 0.55 0.95 .022 .037 N SEE VARIATIONS SEE VARIATIONS α 0° 8° 0° 8° L E1 INDEX AREA E 1 2 α D A A2 A1 VARIATIONS -Ce b N SEATING PLANE 28 .10 (.004) C D mm. MIN 9.90 D (inch) MAX 10.50 Reference Doc.: JEDEC Publication 95, MO-150 10-0033 209 mil SSOP Ordering Information ICS93776yFLF-T Example: ICS XXXX y F LF- T Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0793A—03/08/05 7 MIN .390 MAX .413 ICS93776 Revision History Rev. N/A N/A Issue Date Description 8/12/2004 Updated I2c 8/20/2004 Updated I2c Page # 6 6 0793A—03/08/05 8