SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com SCBS481H – JUNE 1994 – REVISED APRIL 2005 FEATURES • • • • • • • • • • • • DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference GTL Buffered CLKAB Signal (CLKOUT) Translates Between GTL/GTL+ Signal Levels and LVTTL Logic Levels Supports Mixed-Mode (3.3 V and 5 V) Signal Operation on A-Port and Control Inputs Equivalent to '16601 Function Ioff Supports Partial-Power-Down Mode Operation Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) OEAB LEAB A1 GND A2 A3 VCC (3.3 V) A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC (3.3 V) A16 A17 GND CLKIN OEBA LEBA 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 CEAB CLKAB B1 GND B2 B3 VCC (5 V) B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VREF B16 B17 GND CLKOUT CLKBA CEBA DESCRIPTION/ORDERING INFORMATION The SN74GTL16616 is a 17-bit UBT™ transceiver that provides LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. Combined D-type flip-flops and D-type latches allow for transparent, latched, clocked, and clocked-enabled modes of data transfer identical to the '16601 function. Additionally, this device provides for a copy of CLKAB at GTL/GTL+ signal levels (CLKOUT) and conversion of a GTL/GTL+ clock to LVTTL logic levels (CLKIN). This device provides an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC™ circuitry. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C SSOP – DL TSSOP – DGG (1) ORDERABLE PART NUMBER TOP-SIDE MARKING Tube SN74GTL16616DL GTL16616 Tape and reel SN74GTL16616DLR GTL16616 Tape and reel SN74GTL16616DGGR GTL16616 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, UBT, OEC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1994–2005, Texas Instruments Incorporated SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com SCBS481H – JUNE 1994 – REVISED APRIL 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port. VCC (5 V) supplies the internal and GTL circuitry, while VCC (3.3 V) supplies the LVTTL output buffers. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CEBA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (1) INPUTS MODE X Z Isolation X B0 (2) L X B0 (3) H X L L L H X H H L L L ↑ L L L L L ↑ H H H L L X X B0 (3) OEAB LEAB X H L L L (1) (2) (3) 2 OUTPUT B CEAB CLKAB A X X L H L L X L X Latched storage of A data Transparent Clocked storage of A data Clock inhibit A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA, and CEBA. The condition when OEAB and OEBA are both low at the same time is not recommended. Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low Output level before the indicated steady-state input conditions were established SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com SCBS481H – JUNE 1994 – REVISED APRIL 2005 LOGIC DIAGRAM (POSITIVE LOGIC) VREF OEAB CEAB CLKAB LEAB LEBA CLKBA CEBA OEBA A1 35 1 56 55 2 28 30 29 27 CE 1D 3 CE 1D C1 CLK 54 C1 CLK B1 1 of 17 Channels 31 CLKIN CLKOUT 26 3 SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com SCBS481H – JUNE 1994 – REVISED APRIL 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range VI Input voltage range (2) VO Voltage range applied to any output in the high or power-off state (2) IO Current into any output in the low state IO Current into any A-port output in the high state (3) MIN MAX 3.3 V –0.5 4.6 5V –0.5 7 A-port and control inputs –0.5 7 B port and VREF –0.5 4.6 A port –0.5 7 B port –0.5 4.6 A port 128 B port 80 Continuous current through each VCC or GND UNIT V V V mA 64 mA ±100 mA IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) DGG package 64 DL package 56 –65 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) (2) (3) (4) VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK Input clamp current IOH High-level output current IOL Low-level output current TA Operating free-air temperature (1) (2) (3) (4) 4 MIN NOM MAX 3.3 V 3.15 3.3 3.45 5V 4.75 5 5.25 GTL 1.14 1.2 1.26 GTL+ 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTL+ 0.87 1 1.1 B port VTT Except B port 5.5 B port Except B port UNIT VREF + 50 mV VREF – 50 mV Except B port V V V V 2 B port V 0.8 V –18 mA A port –32 mA A port 64 B port 40 –40 85 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Normal connection sequence is GND first, VCC = 5 V second, and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. mA °C SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com SCBS481H – JUNE 1994 – REVISED APRIL 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VCC (3.3 V) = 3.15 V, VOH A port A port VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V VCC (5 V) = 4.75 V II = –18 mA –1.2 IOH = –100 µA IOH = –8 mA IOH = –32 mA 2 IOL = 100 µA 0.2 IOL = 16 mA 0.4 IOL = 32 mA 0.5 IOL = 64 mA 0.55 VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V, IOL = 40 mA 0.4 VCC = 0 or 3.45 V, VCC (5 V) = 0 or 5.25 V, VI = 5.5 V 10 VI = 5.5 V 20 VCC (5 V) = 5.25 V VI = VCC (3.3 V) 1 VI = 0 B port Ioff VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V VCC = 0, VI or VO = 0 to 4.5 V –30 VI = VCC (3.3 V) II(hold) A port VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V VI = 0 IOZH IOZL ICC (3.3 V) ICC (5 V) VI = 2 V (1) (2) (3) ±500 VCC (5 V) = 5.25 V, VO = 3 V B port VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 1.2 V A port VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 0.5 V –1 B port VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 0.4 V –10 A or B port VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, IO = 0, VI = VCC (3.3 V) or GND 1 10 Outputs high 1 Outputs low 5 Outputs disabled 1 Outputs high 120 Outputs low 120 Outputs disabled 120 VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, A-port or control inputs at VCC (3.3 V) or GND, One input at 2.7 V ∆ICC (3) Cio µA –75 V) (2) VCC (3.3 V) = 3.45 V, VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, IO = 0, VI = VCC (3.3 V) or GND µA 75 A port A or B port µA –5 100 VI = 0 to VCC (3.3 V 5 VI = 0.8 V Ci V 2.4 Control inputs VCC (3.3 V) = 3.45 V, V VCC – 0.2 B port A port II VCC (5 V) = 4.75 V, VCC (3.3 V) = 3.15 V to 3.45 V, VCC (5 V) = 4.75 V to 5.25 V, VCC (3.3 V) = 3.15 V, VOL MIN TYP (1) MAX UNIT TEST CONDITIONS 1 Control inputs VI = 3.15 V or 0 3.5 A port VO = 3.15 V or 0 12 B port Per IEEE Std 1194.1 µA µA mA mA mA pF 5 pF All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. 5 SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com SCBS481H – JUNE 1994 – REVISED APRIL 2005 Timing Requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2 V and VREF = 0.8 V for GTL (unless otherwise noted) (see Figure 1) MIN fclock tw tsu th 6 Clock frequency Pulse duration Setup time Hold time LEAB or LEBA high 3.3 CLKAB or CLKBA high or low 5.5 A before CLKAB↑ 1.3 B before CLKBA↑ 2.5 A before LEAB↓ 0 B before LEBA↓ 1.1 CEAB before CLKAB↑ 2.2 CEBA before CLKBA↑ 2.7 A after CLKAB↑ 1.6 B after CLKBA↑ 0.4 A after LEAB↓ 4 B after LEBA↓ 3.5 CEAB after CLKAB↑ 1.1 CEBA after CLKBA↑ 0.9 MAX UNIT 95 MHz ns ns ns SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com SCBS481H – JUNE 1994 – REVISED APRIL 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2 V and VREF = 0.8 V for GTL (see Figure 1) PARAMETER TO (OUTPUT) MIN TYP (1) MAX fmax 95 tPLH 1.7 3 4.4 1.4 2.8 4.5 2.3 3.8 5.4 2.2 3.7 5.3 2.4 4 5.7 2.1 3.7 5.4 4.7 6.1 8.1 5.7 7.9 11.3 2.1 3.6 5.1 2.1 3.8 5.6 tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH A B LEAB B CLKAB B CLKAB CLKOUT OEAB B or CLKOUT tr Transition time, B outputs (0.5 V to 1 V) tf Transition time, B outputs (1 V to 0.5 V) tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL ten tdis (1) FROM (INPUT) B A LEBA A CLKBA A CLKOUT CLKIN OEBA A or CLKIN UNIT MHz 1.2 ns ns ns ns ns ns 0.7 ns 1.7 4 6.7 1.4 2.9 4.7 2.4 3.8 5.8 2 3 4.6 2.6 4 6 2.2 3.4 4.9 7.4 10 14.4 6.1 8.1 11.7 2.8 5.3 7.8 2.7 4.3 6.4 ns ns ns ns ns All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C. 7 SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com SCBS481H – JUNE 1994 – REVISED APRIL 2005 Timing Requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (unless otherwise noted) (see Figure 1) MIN fclock tw tsu th 8 Clock frequency Pulse duration Setup time Hold time LEAB or LEBA high 3.3 CLKAB or CLKBA high or low 5.5 A before CLKAB↑ 1.3 B before CLKBA↑ 2.3 A before LEAB↓ 0 B before LEBA↓ 1.3 CEAB before CLKAB↑ 2.2 CEBA before CLKBA↑ 2.7 A after CLKAB↑ 1.6 B after CLKBA↑ 0.6 A after LEAB↓ 4 B after LEBA↓ 3.5 CEAB after CLKAB↑ 1.1 CEBA after CLKBA↑ 0.9 MAX UNIT 95 MHz ns ns ns SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com SCBS481H – JUNE 1994 – REVISED APRIL 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 1) PARAMETER TO (OUTPUT) MIN TYP (1) MAX fmax 95 tPLH 1.7 3 4.4 1.4 2.9 4.6 2.3 3.8 5.4 2.2 3.7 5.4 2.4 4 5.7 2.1 3.8 5.5 4.7 6.1 8.1 5.7 8 11.4 2.1 3.6 5.1 2.1 3.8 5.7 tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL A B LEAB B CLKAB B CLKAB CLKOUT OEAB B or CLKOUT tr Transition time, B outputs (0.5 V to 1 V) tf Transition time, B outputs (1 V to 0.5 V) tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL ten tdis (1) FROM (INPUT) B A LEBA A CLKBA A CLKOUT CLKIN OEBA A or CLKIN UNIT MHz 1.4 ns ns ns ns ns ns 1 ns 1.6 3.9 6.6 1.3 2.8 4.5 2.4 3.8 5.8 2 3 4.6 2.6 4 6 2.2 3.4 4.9 7.3 9.9 14.3 6 8 11.5 2.8 5.3 7.8 2.7 4.3 6.4 ns ns ns ns ns All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C. 9 SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com SCBS481H – JUNE 1994 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VTT = 1.2 V, VREF = 0.8 V FOR GTL AND VTT = 1.5 V, VREF = 1 V FOR GTL+ VTT 6V 500 Ω From Output Under Test S1 Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND CL = 50 pF (see Note A) 500 Ω 25 Ω S1 Open 6V GND From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT FOR A OUTPUTS Test Point LOAD CIRCUIT FOR B OUTPUTS tw 3V 3V VM V Input VM V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION (VM = 1.5 V for A port and VREF for B port)† Input (see Note B) 3V 1.5 V 1.5 V tsu th 3V Data Input A Port 1.5 V Data Input B Port VREF 1.5 V 0V VTT VREF 0V 0V tPLH VOLTAGE WAVEFORMS SETUP AND HOLD TIMES tPHL VTT Output VREF VREF VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port)† Input (see Note B) VREF 0V tPLH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) tPLZ 3V 1.5 V tPZH 1.5 V 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note C) tPHL VOH Output 1.5 V tPZL VTT VREF 3V Output Control (see Note B) Output Waveform 2 S1 at GND (see Note C) VOL + 0.3 V VOL tPHZ VOH 1.5 V VOH − 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port and CLKIN) † All control inputs are TTL levels. NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 10 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74GTL16616DGGRE4 ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTL16616DGGR ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTL16616DL ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTL16616DLG4 ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTL16616DLR ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTL16616DLRG4 ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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