SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES293C – OCTOBER 1999 – REVISED JUNE 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+™ Family TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels LVTTL Interfaces Are 5-V Tolerant Medium-Drive GTLP Outputs (50 mA) • • • • • • LVTTL Outputs (–24 mA/24 mA) GTLP Rise and Fall Times Designed for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion Bus Hold on A-Port Data Inputs Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II DESCRIPTION/ORDERING INFORMATION The SN74GTLPH32945 is a medium-drive, 32-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It is partitioned as four 8-bit transceivers. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 19 Ω. GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH32945 is given only at the preferred higher noise margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies. Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. ORDERING INFORMATION TA –40°C to 85°C (1) PACKAGE (1) LFBGA – GKE Tape and reel ORDERABLE PART NUMMER SN74GTLPH32945KR TOP-SIDE MARKING GM45 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+, TI-OPC, OEC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2005, Texas Instruments Incorporated SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES293C – OCTOBER 1999 – REVISED JUNE 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. GKE PACKAGE (TOP VIEW) 1 2 3 4 5 6 A B C D E F G H J K L M N P R T TERMINAL ASSIGNMENTS 2 1 2 3 4 5 6 A 1A2 1A1 1DIR 1OE 1B1 1B2 B 1A4 1A3 GND GND 1B3 1B4 C 1A6 1A5 1VCC 1BIAS VCC 1B5 1B6 D 1A8 1A7 GND GND 1B7 1B8 E 2A2 2A1 GND GND 2B1 2B2 F 2A4 2A3 1VCC 1VREF 2B3 2B4 G 2A6 2A5 GND GND 2B5 2B6 H 2A7 2A8 2DIR 2OE 2B8 2B7 J 3A2 3A1 3DIR 3OE 3B1 3B2 K 3A4 3A3 GND GND 3B3 3B4 L 3A6 3A5 2VCC 2BIAS VCC 3B5 3B6 M 3A8 3A7 GND GND 3B7 3B8 N 4A2 4A1 GND GND 4B1 4B2 P 4A4 4A3 2VCC 2VREF 4B3 4B4 R 4A6 4A5 GND GND 4B5 4B6 T 4A7 4A8 4DIR 4OE 4B8 4B7 SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES293C – OCTOBER 1999 – REVISED JUNE 2005 FUNCTIONAL DESCRIPTION The SN74GTLPH32945 is a medium-drive (50-mA), 32-bit bus transceiver partitioned as four 8-bit segments and is designed for asynchronous communication between data buses. The device transmits data from the A port to the B port or from the B port to the A port, depending on the logic level at the direction-control (DIR) input. OE can be used to disable the device so the buses are effectively isolated. Data polarity is noninverting. For A-to-B data flow, when OE is low and DIR is high, the B outputs take on the logic value of the A inputs. When OE is high, the outputs are in the high-impedance state. The data flow for B to A is similar to that of A to B, except OE and DIR are low. FUNCTION TABLE INPUTS OUTPUT MODE X Z Isolation L B data to A port H A data to B port OE DIR H L L True transparent LOGIC DIAGRAM (POSITIVE LOGIC) 1DIR A3 A4 1A1 A5 A2 F4 1OE 1B1 1VREF To Seven Other Channels 2DIR H3 H4 2A1 E5 E2 2OE 2B1 To Seven Other Channels (1) 1VCC and 1BIAS VCC are associated with these channels. 3 SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES293C – OCTOBER 1999 – REVISED JUNE 2005 LOGIC DIAGRAM (POSITIVE LOGIC) (CONTINUED)(1) 3DIR J3 J4 3A1 J5 J2 P4 3OE 3B1 2VREF To Seven Other Channels 4DIR T3 T4 4A1 N5 N2 To Seven Other Channels (1) 4 2VCC and 2BIAS VCC are associated with these channels. 4OE 4B1 SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES293C – OCTOBER 1999 – REVISED JUNE 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC BIAS VCC Supply voltage range VI Input voltage range (2) VO Voltage range applied to any output in the high-impedance or power-off state (2) IO Current into any output in the low state IO Current into any A-port output in the high state (3) MIN MAX –0.5 4.6 A-port and control inputs –0.5 7 B port and VREF –0.5 4.6 A port –0.5 7 B port –0.5 4.6 A port 48 B port 100 Continuous current through each VCC or GND UNIT V V V mA 48 mA ±100 mA IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA 40 °C/W 150 °C θJA Package thermal Tstg Storage temperature range (1) (2) (3) (4) impedance (4) –65 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. 5 SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES293C – OCTOBER 1999 – REVISED JUNE 2005 Recommended Operating Conditions (1) (2) (3) (4) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK Input clamp current IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC Power-up ramp rate TA Operating free-air temperature (1) (2) (3) (4) 6 MIN NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 B port VTT Except B port B port Except B port VCC 5.5 VREF + 0.05 VREF – 0.05 Except B port V V V 2 B port V 0.8 V –18 mA A port –24 mA A port 24 B port 50 Outputs enabled 10 ns/V µs/V 20 –40 mA 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable but, generally, GND is connected first. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current drain. SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES293C – OCTOBER 1999 – REVISED JUNE 2005 Electrical Characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port VCC = 3.15 V, II = –18 mA VCC = 3.15 V to 3.45 V, IOH = –100 µA VCC – 0.2 IOH = –12 mA 2.4 IOH = –24 mA 2 VCC = 3.15 V VCC = 3.15 V to 3.45 V, A port VOL VCC = 3.15 V VCC = 3.15 V to 3.45 V, B port II Control inputs IOZH (2) IOZL (2) A port B port MIN TYP (1) TEST CONDITIONS VCC = 3.15 V VCC = 3.45 V, VCC = 3.45 V MAX UNIT –1.2 V V IOL = 100 µA 0.2 IOL = 12 mA 0.4 IOL = 24 mA 0.5 IOL = 100 µA 0.2 IOL = 10 mA 0.2 IOL = 40 mA 0.4 IOL = 50 mA 0.55 VI = 0 or 5.5 V ±10 VO = VCC 10 VO = 1.5 V 10 –10 V µA µA µA A and B ports VCC = 3.45 V, VO = GND (3) A port VCC = 3.15 V, VI = 0.8 V 75 µA IBHH (4) A port VCC = 3.15 V, VI = 2 V –75 µA IBHLO (5) A port VCC = 3.45 V, VI = 0 to VCC 500 µA (6) A port VCC = 3.45 V, VI = 0 to VCC –500 IBHL IBHHO ICC A or B port Cio (1) (2) (3) (4) (5) (6) (7) 100 Outputs low 100 Outputs disabled 100 VCC = 3.45 V, One A-port or control input at VCC – 0.6 V, Other A-port or control inputs at VCC or GND ∆ICC (7) Ci VCC = 3.45 V, IO = 0, VI (A-port or control inputs) = VCC or GND, VI (B port) = VTT or GND µA Outputs high mA 1 mA pF Control inputs VI = 3.15 V or 0 4.5 5 A port VO = 3.15 V or 0 7.5 9 B port VO = 1.5 V or 0 7.5 9 pF All typical values are at VCC = 3.3 V, TA = 25°C. For I/O ports, the parameters IOZH and IOZL include the input leakage current. The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and then raising it to VILmax. The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and then lowering it to VIHmin. An external driver must source at least IBHLO to switch this node from low to high. An external driver must sink at least IBHHO to switch this node from high to low. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Hot-Insertion Specifications for A Port over recommended operating free-air temperature range PARAMETER Ioff TEST CONDITIONS MIN MAX UNIT 10 µA OE = 0 ±30 µA OE = 0 ±30 µA VCC = 0, BIAS VCC = 0, VI or VO = 0 to 5.5 V IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, 7 SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES293C – OCTOBER 1999 – REVISED JUNE 2005 Live-Insertion Specifications for B Port over recommended operating free-air temperature range PARAMETER Ioff TEST CONDITIONS MIN µA ±30 µA VO = 0.5 V to 1.5 V, OE = 0 ±30 µA 5 mA 10 µA VI or VO = 0 to 1.5 V IOZPU VCC = 0 to 1.5 V, BIAS VCC = 0, IOZPD VCC = 1.5 V to 0, BIAS VCC = 0, ICC (BIAS VCC) VCC = 3.15 V to 3.45 V UNIT VO = 0.5 V to 1.5 V, OE = 0 BIAS VCC = 0, VCC = 0 to 3.15 V MAX 10 VCC = 0, BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0 to 1.5 V VO VCC = 0, BIAS VCC = 3.3 V, IO = 0 IO VCC = 0, BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0.6 V 0.95 1.05 V µA –1 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) PARAMETER tPLH tPHL ten tdis A B OE B Rise time, B outputs (20% to 80%) tf Fall time, B outputs (80% to 20%) tPHL ten tdis 8 TO (OUTPUT) tr tPLH (1) FROM (INPUT) B A OE A All typical values are at VCC = 3.3 V, TA = 25°C. MIN TYP (1) MAX 2.1 6.3 2.1 6.3 2 6.9 2 6.9 2.5 UNIT ns ns ns 2.1 ns 2.1 5.3 2.1 5.3 0.3 5.7 0.3 5.7 ns ns SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES293C – OCTOBER 1999 – REVISED JUNE 2005 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 1.5 V 6V Open GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω 25 Ω From Output Under Test CL = 30 pF (see Note A) S1 Open 6V GND Test Point LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS 3V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1V Output 1V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port) 1V 0V tPLH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) tPLZ 3V 1.5 V VOL + 0.3 V VOL tPZH VOH Output 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V 1.5 V tPZL 1.5 V 1V Input 3V Output Control Output Waveform 2 S1 at GND (see Note B) tPHZ VOH 1.5 V VOH − 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 9 SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES293C – OCTOBER 1999 – REVISED JUNE 2005 Distributed-Load Backplane Switching Characteristics The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC load, to help the designer better understand the performance of the GTLP device in this typical backplane. See www.ti.com/sc/gtlp for more information. 38 Ω 0.25” ZO = 70 Ω 2” Conn. 1” Conn. 2” Conn. Conn. 1” 1” 0.25 ” 1” Rcvr Rcvr Rcvr Slot 2 Slot 9 Slot 10 Drvr Slot 1 Figure 2. Medium-Drive Test Backplane 1.5 V 19 Ω From Output Under Test LL = 19 nH Test Point CL = 9 pF Figure 3. Medium-Drive RLC Network 10 38 Ω 1.5 V 1.5 V SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES293C – OCTOBER 1999 – REVISED JUNE 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3) PARAMETER tPLH tPHL ten tdis (1) FROM (INPUT) TO (OUTPUT) A B OE B TYP (1) 4.3 4.3 5 4.4 UNIT ns ns tr Rise time, B outputs (20% to 80%) 1 ns tf Fall time, B outputs (80% to 20%) 2 ns All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models. 11 PACKAGE OPTION ADDENDUM www.ti.com 11-Sep-2007 PACKAGING INFORMATION Status (1) Package Type Package Drawing SN74GTLPH32945KR NRND LFBGA GKE 96 1000 SN74GTLPH32945ZKER ACTIVE LFBGA ZKE 96 1000 Green (RoHS & no Sb/Br) Orderable Device Pins Package Eco Plan (2) Qty TBD Lead/Ball Finish MSL Peak Temp (3) SNPB Level-3-220C-168 HR SNAGCU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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