TI SN74GTLPH16912VR

SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Member of the Texas Instruments Widebus™
Family
UBT™ Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, Clocked, and
Clock-Enabled Modes
TI-OPC™ Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
LVTTL Interfaces Are 5-V Tolerant
Medium-Drive GTLP Outputs (50 mA)
LVTTL Outputs (–24 mA/24 mA)
GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
Ioff, Power-Up 3-State, and BIAS VCC Support
Live Insertion
Bus Hold on A-Port Data Inputs
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SCES288C – OCTOBER 1999 – REVISED JUNE 2005
DGG OR DGV PACKAGE
(TOP VIEW)
OEAB
LEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
LEBA
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
CEAB
CLKAB
B1
GND
B2
B3
BIAS VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VREF
B16
B17
GND
B18
CLKBA
CEBA
DESCRIPTION/ORDERING INFORMATION
The SN74GTLPH16912 is a medium-drive, 18-bit UBT™ transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, and clock-enabled modes of
data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and a
backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL)
backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels,
improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuits
minimize bus-settling time and have been designed and tested using several backplane models. The medium
drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 19 Ω.
GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard
JESD 8-3. The ac specification of the SN74GTLPH16912 is given only at the preferred higher noise-margin
GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP
(VTT = 1.5 V and VREF = 1 V) signal levels.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, TI-OPC, OEC, TI are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2005, Texas Instruments Incorporated
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C – OCTOBER 1999 – REVISED JUNE 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output
connections, preventing disturbance of active data on the backplane during card insertion or removal, and
permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal
integrity, which allows adequate noise margin to be maintained at higher frequencies.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the
driver.
ORDERING INFORMATION
TA
–40°C to 85°C
(1)
2
PACKAGE (1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TSSOP – DGG
Tape and reel
SN74GTLPH16912GR
GTLPH16912
TVSOP – DGV
Tape and reel
SN74GTLPH16912VR
GL912
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C – OCTOBER 1999 – REVISED JUNE 2005
FUNCTIONAL DESCRIPTION
The SN74GTLPH16912 is a medium-drive (50-mA), 18-bit UBT transceiver containing D-type latches and D-type
flip-flops for data-path operation in transparent, latched, clocked, or clock-enabled modes and can replace any of
the functions shown in Table 1. Data polarity is noninverting.
Table 1. SN74GTLPH16912 UBT Transceiver Replacement Functions
8 BIT
9 BIT
10 BIT
16 BIT
18 BIT
Transceiver
FUNCTION
'245, '623, '645
'863
'861
'16245, '16623
'16863
Buffer/driver
'241, '244, '541
'827
'16241, '16244, '16541
'16825
'16543
'16472
'16373
'16843
'16646, '16652
'16474
Latched transceiver
'543
Latch
'373, '573
Registered transceiver
'646, '652
Flip-flop
'374, '574
'843
'841
'821
'16374
Standard UBT
'16500, '16501
Universal bus driver
'16835
Registered transceiver with clock enable
'2952
Flip-flop with clock enable
'377
'16470, '16952
'823
'16823
Standard UBT with clock enable
'16600, '16601
SN74GTLPH16912 UBT transceiver replaces all above functions
Data flow in each direction is controlled by clock enables (CEAB and CEBA), latch enables (LEAB and LEBA),
clock (CLKAB and CLKBA), and output enables (OEAB and OEBA). CEAB and CEBA and OEAB and OEBA
control the 18 bits of data for the A-to-B and B-to-A directions, respectively.
For A-to-B data flow, when CEAB is low, the device operates on the low-to-high transition of CLKAB for the
flip-flop and on the high-to-low transition of LEAB for the latch path, i.e., if CEAB and LEAB are low, the A data is
latched, regardless of the state of CLKAB (high or low). If LEAB is high, the device is in transparent mode. When
OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.
The data flow for B to A is similar to that of A to B, except CEBA, OEBA, LEBA, and CLKBA are used.
FUNCTION TABLE (1)
INPUTS
CEAB
OEAB
LEAB
X
H
L
L
L
(1)
(2)
(3)
OUTPUT
B
MODE
X
Z
Isolation
X
B0 (2)
X
B0 (3)
CLKAB
A
X
X
L
H
L
L
L
X
L
H
X
L
L
X
L
H
X
H
H
L
L
L
↑
L
L
L
L
L
↑
H
H
H
L
L
X
X
B0 (3)
Latched storage of A data
True transparent
Clocked storage of A data
Clock inhibit
A-to-B data flow is shown. B-to-A data flow is similar, but uses CEBA, OEBA, LEBA, and CLKBA.
The condition when OEAB and OEBA are both low at the same time is not recommended.
Output level before the indicated steady-state input conditions were established, provided that
CLKAB was high before LEAB went low
Output level before the indicated steady-state input conditions were established
3
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C – OCTOBER 1999 – REVISED JUNE 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
35
VREF
1
OEAB
CEAB
56
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
CEBA
29
27
OEBA
CE
1D
3
A1
C1
CLK
CE
1D
C1
CLK
To 17 Other Channels
4
54
B1
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C – OCTOBER 1999 – REVISED JUNE 2005
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
VCC
BIAS VCC
Supply voltage range
VI
Input voltage range (2)
VO
Voltage range applied to any output in the
high-impedance or power-off state
IO
Current into any output in the low state
IO
Current into any A-port output in the high state (3)
MIN
MAX
–0.5
4.6
A-port and control inputs
–0.5
7
B port and VREF
–0.5
4.6
A port
–0.5
7
B port
–0.5
4.6
A port
48
B port
100
UNIT
V
V
V
mA
48
mA
±100
mA
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
Continuous current through each VCC or GND
(1)
(2)
(3)
(4)
DGG package
64
DGV package
48
–65
150
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This current flows only when the output is in the high state and VO > VCC.
The package thermal impedance is calculated in accordance with JESD 51-7.
5
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C – OCTOBER 1999 – REVISED JUNE 2005
Recommended Operating Conditions (1) (2) (3) (4)
VCC
BIAS VCC
Supply voltage
VTT
Termination voltage
VREF
Reference voltage
VI
Input voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IIK
Input clamp current
IOH
High-level output current
IOL
Low-level output current
∆t/∆V
Input transition rise or fall rate
∆t/∆VCC
Power-up ramp rate
TA
Operating free-air temperature
(1)
(2)
(3)
(4)
6
MIN
NOM
MAX
UNIT
3.15
3.3
3.45
V
GTL
1.14
1.2
1.26
GTLP
1.35
1.5
1.65
GTL
0.74
0.8
0.87
GTLP
0.87
1
1.1
B port
VTT
Except B port
B port
Except B port
VCC
5.5
VREF + 0.05
VREF – 0.05
Except B port
V
V
V
2
B port
V
0.8
V
–18
mA
A port
–24
mA
A port
24
B port
50
Outputs enabled
10
ns/V
µs/V
20
–40
mA
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V
last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be
connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is
acceptable, but generally, GND is connected first.
VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is
activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current
drain.
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C – OCTOBER 1999 – REVISED JUNE 2005
Electrical Characteristics
over recommended operating free-air temperature range for GTLP (unless otherwise noted)
PARAMETER
VIK
VOH
A port
TEST CONDITIONS
VCC = 3.15 V,
II = –18 mA
VCC = 3.15 V to 3.45 V,
IOH = –100 µA
VCC – 0.2
IOH = –12 mA
2.4
IOH = –24 mA
2
VCC = 3.15 V
VCC = 3.15 V to 3.45 V,
A port
VOL
II
VCC = 3.15 V
VCC = 3.15 V to 3.45 V,
B port
A-port and
control inputs
(2)
MIN
VCC = 3.15 V
VCC = 3.45 V
B port
TYP (1)
MAX
UNIT
–1.2
V
V
IOL = 100 µA
0.2
IOL = 12 mA
0.4
IOL = 24 mA
0.5
IOL = 100 µA
0.2
IOL = 10 mA
0.2
IOL = 40 mA
0.4
IOL = 50 mA
0.55
VI = 0 or VCC
±10
VI = 5.5 V
±20
VI = 0 to 1.5 V
±10
IBHL (3)
A port
VCC = 3.15 V,
VI = 0.8 V
(4)
V
µA
75
µA
A port
VCC = 3.15 V,
VI = 2 V
–75
µA
IBHLO (5)
A port
VCC = 3.45 V,
VI = 0 to VCC
500
µA
IBHHO (6)
A port
VCC = 3.45 V,
VI = 0 to VCC
–500
µA
ICC
A or B port
VCC = 3.45 V, IO = 0,
VI (A-port or control input) = VCC or GND,
VI (B port) = VTT or GND
IBHH
Cio
(1)
(2)
(3)
(4)
(5)
(6)
(7)
50
Outputs low
50
Outputs disabled
50
VCC = 3.45 V, One A-port or control input at VCC – 0.6 V,
Other A-port or control inputs at VCC or GND
∆ICC (7)
Ci
Outputs high
mA
1.5
mA
pF
Control inputs
VI = 3.15 V or 0
4
5.5
A port
VO = 3.15 V or 0
7
8.5
B port
VO = 1.5 V or 0
8.5
9.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
For I/O ports, the parameter II includes the off-state output leakage current.
The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND
and then raising it to VILmax.
The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC
and then lowering it to VIHmin.
An external driver must source at least IBHLO to switch this node from low to high.
An external driver must sink at least IBHHO to switch this node from high to low.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Hot-Insertion Specifications for A Port
over recommended operating free-air temperature range
PARAMETER
Ioff
TEST CONDITIONS
MIN
MAX
UNIT
10
µA
OE = 0
±30
µA
OE = 0
±30
µA
VCC = 0,
BIAS VCC = 0,
VI or VO = 0 to 5.5 V
IOZPU
VCC = 0 to 1.5 V,
VO = 0.5 V to 3 V,
IOZPD
VCC = 1.5 V to 0,
VO = 0.5 V to 3 V,
7
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C – OCTOBER 1999 – REVISED JUNE 2005
Live-Insertion Specifications for B Port
over recommended operating free-air temperature range
PARAMETER
Ioff
TEST CONDITIONS
MIN
µA
±30
µA
VO = 0.5 V to 1.5 V, OE = 0
±30
µA
5
mA
10
µA
VI or VO = 0 to 1.5 V
IOZPU
VCC = 0 to 1.5 V,
BIAS VCC = 0,
IOZPD
VCC = 1.5 V to 0,
BIAS VCC = 0,
ICC (BIAS VCC)
VCC = 3.15 V to 3.45 V
UNIT
VO = 0.5 V to 1.5 V, OE = 0
BIAS VCC = 0,
VCC = 0 to 3.15 V
MAX
10
VCC = 0,
BIAS VCC = 3.15 V to 3.45 V,
VO (B port) = 0 to 1.5 V
VO
VCC = 0,
BIAS VCC = 3.3 V,
IO = 0
IO
VCC = 0,
BIAS VCC = 3.15 V to 3.45 V,
VO (B port) = 0.6 V
0.95
1.05
V
µA
–1
Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted)
MIN
fclock
tw
tsu
th
8
Clock frequency
Pulse duration
Setup time
Hold time
LEAB or LEBA high
2.8
CLKAB or CLKBA high or low
2.8
A before CLKAB↑
1.8
B before CLKBA↑
1.5
A before LEAB↓
1
B before LEBA↓
2
CEAB before CLKAB↑
1.5
CEBA before CLKBA↑
1.4
A after CLKAB↑
0.3
B after CLKBA↑
0.4
A after LEAB↓
1.1
B after LEBA↓
0.4
CEAB after CLKAB↑
1
CEBA after CLKBA↑
1
MAX
UNIT
175
MHz
ns
ns
ns
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C – OCTOBER 1999 – REVISED JUNE 2005
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1)
PARAMETER
TO
(OUTPUT)
MIN TYP (1)
MAX
fmax
175
tPLH
2.1
6
2.1
6
2.2
6.3
2.2
6.3
2.2
6.5
2.2
6.5
2
6.5
2
6.1
tPHL
tPLH
tPHL
tPLH
tPHL
ten
tdis
A
B
LEAB
B
CLKAB
B
OEAB
B
Rise time, B outputs (20% to 80%)
2.4
tf
Fall time, B outputs (80% to 20%)
2
tPHL
tPLH
tPHL
tPLH
tPHL
ten
tdis
B
A
LEBA
A
CLKBA
A
OEBA
A
UNIT
MHz
tr
tPLH
(1)
FROM
(INPUT)
ns
ns
ns
ns
ns
ns
1.8
5.8
1.8
5.8
0.4
5.3
0.4
5.3
0.6
5.6
0.6
5.7
0.3
6.2
0.3
5.9
ns
ns
ns
ns
All typical values are at VCC = 3.3 V, TA = 25°C.
9
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C – OCTOBER 1999 – REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
1.5 V
6V
Open
S1
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 50 pF
(see Note A)
500 Ω
25 Ω
S1
Open
6V
GND
From Output
Under Test
Test
Point
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
tw
3V
3V
1.5 V
Input
1.5 V
Timing
Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu
th
VOH
Data
Input
VM
VM
0V
3V
Input
1.5 V
1.5 V
0V
tPLH
tPHL
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
(VM = 1.5 V for A port and 1 V for B port)
(VOH = 3 V for A port and 1.5 V for B port)
VOH
Output
1V
1V
3V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
1V
1V
0V
tPLH
1.5 V
tPLZ
3V
1.5 V
VOL + 0.3 V
VOL
tPZH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
VOH
Output
1.5 V
tPZL
1.5 V
Input
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
tPHZ
VOH
1.5 V
VOH − 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
10
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C – OCTOBER 1999 – REVISED JUNE 2005
Distributed-Load Backplane Switching Characteristics
The preceding switching characteristics table shows the switching characteristics of the device into a lumped
load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical
representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a
resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum
performance in this RLC circuit. The following switching characteristics table shows the switching characteristics
of the device into the RLC load, to help the designer better understand the performance of the GTLP device in
this typical backplane. See www.ti.com/sc/gtlp for more information.
38 Ω
0.25”
ZO = 70 Ω
2”
Conn.
1”
Conn.
2”
Conn.
Conn.
1”
1”
0.25”
38 Ω
1.5 V
1.5 V
1”
Rcvr
Rcvr
Rcvr
Slot 2
Slot 9
Slot 10
Drvr
Slot 1
Figure 2. Medium-Drive Test Backplane
1.5 V
19 Ω
From Output
Under Test
LL = 19 nH
Test
Point
CL = 9 pF
Figure 3. Medium-Drive RLC Network
11
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C – OCTOBER 1999 – REVISED JUNE 2005
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
tdis
(1)
12
FROM
(INPUT)
TO
(OUTPUT)
A
B
LEAB
B
CLKAB
B
OEAB
B
TYP (1)
4.5
4.5
4.7
4.7
4.7
4.7
4.8
4.4
UNIT
ns
ns
ns
ns
tr
Rise time, B outputs (20% to 80%)
1.2
ns
tf
Fall time, B outputs (80% to 20%)
2.5
ns
All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74GTLPH16912GRE4
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74GTLPH16912GRG4
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74GTLPH16912VRE4
ACTIVE
TVSOP
DGV
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74GTLPH16912VRG4
ACTIVE
TVSOP
DGV
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74GTLPH16912GR
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74GTLPH16912VR
ACTIVE
TVSOP
DGV
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74GTLPH16912GR
DGG
56
SITE 41
330
24
8.6
15.6
1.8
12
24
Q1
SN74GTLPH16912VR
DGV
56
SITE 41
330
24
6.8
10.1
1.6
12
24
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74GTLPH16912GR
DGG
56
SITE 41
346.0
346.0
41.0
SN74GTLPH16912VR
DGV
56
SITE 41
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an
unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties
may be subject to additional restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would
reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement
specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications
of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related
requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any
applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its
representatives against any damages arising out of the use of TI products in such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is
solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in
connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products
are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any
non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Telephony
www.ti.com/telephony
Low Power
Wireless
www.ti.com/lpw
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated