TPS3513 PC POWER SUPPLY SUPERVISORS SLVS313 – FEBRUARY 2001 Overvoltage Protection and Lockout for D OR N PACKAGE (TOP VIEW) 12 V, 5 V, and 3.3 V Overcurrent Protection and Lockout for PGI GND FPO PSON IS12 RI NC 12 V, 5 V, and 3.3 V Undervoltage Protection and Lockout for 12 V, and Undervoltage Detect for 5 V and 3.3 V Fault-Protection Output With Open Drain Output Stage Open-Drain, Power Good Output Signal for Power-Good Input, 3.3 V and 5 V 300-ms Power-Good Delay 75-ms Delay for 5-V and 3.3-V Power Supply Short-Circuit Turnon Protection 2.3 ms PSON Control to FPO Turnoff Delay 38 ms PSON Control Debounce Wide Supply Voltage Range From 4.5 V to 15 V 1 14 2 13 3 12 4 11 5 10 6 9 7 8 PGO VDD VS5 VS33 VS12 IS33 IS5 NC – No internal connection description The TPS3513 is designed to optimize PC switching power supply system with minimum external components. It provides undervoltage lockout (UVLO), protection circuits, power good indicator, and on/off control. typical application IO 0.01 Ω 12 V 12 V 0.01 Ω 5V 3.3 V 5 V VSB PG From Transformer 0.01 Ω R1 Ω R2 Ω System Side 560 Ω 470 kΩ 5V 3.3 V 5 V VSB 1 kΩ TPS3513 PGI PGO GND VDD FPO VS5 PSON VS33 IS12 VS12 RI IS33 NC IS5 Power Supply Output Side 820 Ω 56 kΩ Max Output Current 1.5 kΩ Over Current Protection Trip Point† 12 V 6A 9.2 A 5V 16 A 24.6 A 3.3 v 9A 13.5 A † Over current protection trip point can be programmable. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS3513 PC POWER SUPPLY SUPERVISORS SLVS313 – FEBRUARY 2001 description (continued) UVLO thresholds are 4.45 V (on) and 3.65 V (off). Overcurrent protection (OCP) and overvoltage protection (OVP) monitor 3.3 V, 5 V, and 12 V. When an OC or OV condition is detected, the power-good output (PGO) is asserted low and the fault protection output (FPO) is latched high. PSON from low-to-high resets the latch. The OCP function will be enabled 75 ms after PSON goes low, and a debounce of typically 38 ms. A built-in 2.3-ms delay with 38-ms debounce from PSON to FPO output is enabled at turnoff. An external resistor is connected between the RI pin and the GND pin. This will introduce an accurate I(ref) for OCP function. The I(ref) range is from 12.5 µA to 62.5 µA. The formula for choosing RI resistor is V(RI)/I(ref). Three OCP comparators and the I(ref) section are supplied by VS12. The current draw from the VS12 pin is less than 1 mA. The power good feature monitors PGI, 3.3 V and 5 V, and issues a power good signal when the output is ready. The TPS3513 is characterized for operation from –40°C to 85°C. FUNCTION TABLE PGI PSON UV CONDITION 3.3 V / 5 V OV CONDITIONS UV CONDITION 12 V OC CONDITIONS FPO PGO < 0.9 V L No No No L L < 0.9 V L No No Yes L L < 0.9 V L No Yes No H L < 0.9 V L No Yes Yes H L < 0.9 V L Yes No No L L < 0.9 V L Yes No Yes L L < 0.9 V L Yes Yes No H L < 0.9 V L Yes Yes Yes H L 1.0 V < PGI < 1.1 V L No No No L L 1.0 V < PGI < 1.1 V L No No Yes H L 1.0 V < PGI < 1.1 V L No Yes No H L 1.0 V < PGI < 1.1 V L No Yes Yes H L 1.0 V < PGI < 1.1 V L Yes No No H L 1.0 V < PGI < 1.1 V L Yes No Yes H L 1.0 V < PGI < 1.1 V L Yes Yes No H L 1.0 V < PGI < 1.1 V L Yes Yes Yes H L >1.2 V L No No No L H >1.2 V L No No Yes H L >1.2 V L No Yes No H L >1.2 V L No Yes Yes H L >1.2 V L Yes No No H L >1.2 V L Yes No Yes H L >1.2 V L Yes Yes No H L >1.2 V L Yes Yes Yes H L x H x x x H L x = don’t care FPO = L means: fault is not latched FPO = H means: fault is latched PGO = L means: fault PGO = H means: No fault 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3513 PC POWER SUPPLY SUPERVISORS SLVS313 – FEBRUARY 2001 schematic VDD VS12 12 V OV + _ UVLO POR VS5 R 5 V OV FPO + _ 73 µ s Debounce VS33 S 2.3 ms Delay VDD 38 ms Debounce 3.3 V OV + _ PSON 3.3 V UV + _ 75 ms Delay 5 V UV VDD + _ PGO PGI1 150 µ s Debounce + _ 300 ms Delay 12 V UV + _ Band-Gap Reference 1.153 V PGI 150 µ s Debounce and 4.8 ms Delay + PGI2 _ 150 µ s Debounce Band-Gap Reference 1.153 V _ IS12 + Iref x 8 I(ref) Constant Current Source _ IS5 RI + Iref x 8 _ IS33 + Iref x 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS3513 PC POWER SUPPLY SUPERVISORS SLVS313 – FEBRUARY 2001 timing requirements VDD (SB5V) PSON PFO PGI 3.3 V / 5 V 12 V 300 ms 2.3 ms 300 ms 38 ms 38 ms PGO 300 ms PSON Off PSON On OVP Occurs PGO Off Figure 1. AC Turnon and Overvoltage Protect VDD PSON FPO PGI 3.3 V/5 V 12 V 300 ms 300 ms PGO 38 ms 38 ms 300 ms 3.3-V or 5-V Drop OCP Occurs 300 ms 12-V UVP Occurs Figure 2. Overcurrent and Undervoltage Detect/Protect 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3513 PC POWER SUPPLY SUPERVISORS SLVS313 – FEBRUARY 2001 Terminal Functions TERMINAL NAME I/O NO. O DESCRIPTION FPO 3 Inverted fault protection output, open-drain, output stage GND 2 IS12 5 I 12-V overcurrent protection IS5 8 I 5-V overcurrent protection IS33 9 I 3.3-V overcurrent protection NC 7 Ground No internal connection PGI 1 I Power-good input PGO 14 O Power-good output, open drain output stage PSON 4 I On/off control RI 6 I Current sense setting VDD VS12 13 I Supply voltage 10 I 12-V overvoltage/undervoltage protection VS33 11 I 3.3-V overvoltage protect/undervoltage detect VS5 12 I 5-V overvoltage protect/undervoltage detect detailed description power-good and power-good delay A PC power supply is commonly designed to provide a power-good signal, which is defined by the computer manufacturers. PGO is a power-good signal and should be asserted high by the PC power supply to indicate that the 5-VDC and 3.3-VDC outputs are above the undervoltage threshold limit. At this time the converter should be able to provide enough power to assure continuous operation within the specification. Conversely, when either the 5-VDC or the 3.3-VDC output voltages fall below the undervoltage threshold, or when main power has been removed for a sufficiently long time so that power supply operation is no longer assured, PGO should be deasserted to a low state. The power-good (PGO), DC enable (PSON), and the 5-V/3.3-V supply rails are shown in Figure 3. PSON On Off 75% 5-V/3.3-V Output 10% PGO t5 t4 t3 t2 Figure 3. Timing of PSON and PGO Although there is no requirement to meet specific timing parameters, the following signal timings are recommended: 2 ms ≤ t2 ≤ 20 ms, 100 ms < t3 < 2000 ms, t4 > 1 ms, t5 ≤ 10 ms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS3513 PC POWER SUPPLY SUPERVISORS SLVS313 – FEBRUARY 2001 power-good and power-good delay (continued) Furthermore, motherboards should be designed to comply with the above recommended timing. If timings other than these are implemented or required, this information should be clearly specified. The TPS3513 family of power-supply supervisors provides a power-good output (PGO) for the 3.3-V and 5-V supply voltage rails and a separate power-good input (PGI). An internal timer is used to generate a 300-ms power-good delay. If the voltage signals at PGI, VS33, and VS5 rise above the undervoltage threshold, the open-drain, power-good output (PGO) will go high after a delay of 300 ms. When the PGI voltage or any of the 3.3-V, 5-V rail drops below the undervoltage threshold, PGO will be disabled immediately. power-supply remote on/off (PSON) and fault protect output (FPO) Since the latest personal computer generation focuses on easy turnon and power saving functions, the PC power supply will require two characteristics. One is a dc power supply remote on/off function; the other is standby voltage to achieve very low power consumption of the PC system. Thus, the main power needs to be shut down. The power supply remote on/off (PSON) is an active-low signal that turns on all of the main power rails including the 3.3-V, 5-V, –5-V, and –12-V power rails. When this signal is held high by the PC motherboard or left open circuited, the signal of the fault protect output (FPO) also goes high. Thus, the main power rails should not deliver current and should be held at 0 V. When the FPO signal is held high due to an occurring fault condition, the fault status will be latched and the outputs of the main power rails should not deliver current and should be held at 0 V. Toggling the power-supply remote on/off (PSON) from low-to-high will reset the fault-protection latch. During this fault condition only the standby power is not affected. When PSON goes from high to low or low-to-high, the 38-ms debounce block will be active to avoid that a glitch on the input will disable/enable the FPO output. During this period, the undervoltage function is disabled to prevent turnon failure. Power should be delivered to the rails only if the PSON signal is held at ground potential, thus, FPO is active low. The FPO pin can be connected to 5 VDC (or up to 15 VDC) through a pullup resistor. under-voltage protection The TPS3513 provides undervoltage protection (UVP) for the 12-V rail and undervoltage detect for the 3.3-V and 5-V rails. When an undervoltage condition appears at the VS12 input pin for more than 150 µs, the FPO output goes high and PGO goes low. Also, this fault condition will be latched until PSON is toggled from low-to-high or VDD is removed. In flyback or forward type off-line switching power supplies, usually designed for small power, the overload protection design is very simple. Most of these type of power supplies are only sensing the input current for an overload condition. The trigger-point needs to be set much higher than the maximum load in order to prevent false turnon. However, this will cause one critical issue. In case that the connected load is larger than the maximum allowable load but smaller than the trigger-point, the system will always become over-heated and cause failure and damage. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3513 PC POWER SUPPLY SUPERVISORS SLVS313 – FEBRUARY 2001 detailed description (continued) overcurrent protection In bridge or forward type, off-line switching power supplies, usually designed for medium to large power, the overload protection design needs to be very precise. Most of these types of power supplies are sensing the output current for an overload condition. The trigger-point needs to be set higher than the maximum load in order to prevent false turnon. The TPS3513 provides overcurrent protection (OCP) for the 3.3-V, 5-V, and 12-V rails. When an over current condition appears at the OCP comparator input pins for more than 73 µs, the FPO output goes high and PGO goes low. Also, this fault condition will be latched until PSON is toggled from low-to-high or VDD is removed. The resistor connected between the RI pin and the GND pin will introduce an accurate I(ref) for the OCP function. Of course, a more accurate resistor tolerance will be better. The formula for choosing the RI resistor is V(RI)/I(ref). The I(ref) range is from 12.5 µA to 62.5 mA. Three OCP comparators and the I(ref) section are supplied by VS12. Current drawn from the VS12 pin is less than 1 mA. Following is an example on calculating OCP for the 12-V rail: RI = V(RI)/I(ref) = 1.15 V/20 µA = 56 KΩ I(ref) x C x R(IS12) = R(sense) x I(OCP_Trip) I(OCP_Trip) = 20 µA x 8 x 560 Ω/0.01 Ω = 9.2 A C = Current ratio (see recommended operating conditions) overvoltage protection The overvoltage protection (OVP) of the TPS3513 monitors 3.3 V, 5 V, and 12 V. When an overvoltage condition appears at one of the 3.3-V, 5-V, or 12-V input pins for more than 73 µs, the FPO output goes high and PGO goes low. Also, this fault condition will be latched until PSON is toggled from low-to-high or VDD is removed. During fault conditions, most power supplies have the potential to deliver higher output voltages than those normally specified or required. In unprotected equipment, it is possible for output voltages to be high enough to cause internal or external damage of the system. To protect the system under these abnormal conditions, it is common practice to provide overvoltage protection within the power supply. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V Input voltage, VI (PSON, IS5, IS33, PGI) (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V Input voltage, VI (VS33, VS5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V Output voltage: VO (FPO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V VO (PGO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V All other pins (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPS3513 PC POWER SUPPLY SUPERVISORS SLVS313 – FEBRUARY 2001 DISSIPATION RATING TABLE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D 956 mW 7.65 mW/°C 612 mW 497 mW N 1512 mW 12.1 mW/°C 968 mW 786 mW PACKAGE recommended operating conditions at specified temperature range Supply voltage, VDD MIN MAX 4.5 15 PSON, VS5, VS33, IS5, IS33 15 VDD + 0.3 V (max = 7 V) PGI Output voltage, voltage VO FPO 15 PGO 7 FPO 20 Output sink current, current IO(Sink) PGO 10 Supply voltage rising time, tr See Note 2 Output current, IO(RI) RI Operating free-air temperature range, TA V 7 VS12, IS12 Input voltage, voltage VI UNIT 1 V V V mA ms 12.5 62.5 µA –40 85 °C NOTE 2: VDD rising and falling slew rate must be less than 14V/ms. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) over-voltage protection and over-current protection PARAMETER TEST CONDITIONS VS33 Overvoltage threshold Ilkg VOL V(RI) MIN TYP MAX 3.7 3.9 4.1 VS5 5.7 6.1 6.5 VS12 13.2 13.8 14.4 7.6 8 8.4 UNIT V Ratio of current sense sink current to current sense setting pin (RI) source current, I(ref) Resistor at RI = 30 kΩ, 0.1% resistor Leakage current (FPO) Low-level output voltage (FPO) V(FPO) = 5 V I(sink) = 20 mA, VDD = 5 V 0.7 V Noise deglitch time OVP VDD = 5 V 35 73 110 µs Current source reference voltage VDD = 5 V 1.1 1.15 1.2 V MIN TYP MAX UNIT 4.45 V 5 µA undervoltage lockout section PARAMETER TEST CONDITIONS Start threshold voltage Minimum operation voltage after start-up 8 POST OFFICE BOX 655303 3.65 • DALLAS, TEXAS 75265 V TPS3513 PC POWER SUPPLY SUPERVISORS SLVS313 – FEBRUARY 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PGI and PGO PARAMETER VIT(PGI) Input threshold voltage MIN TYP MAX PGI1 TEST CONDITIONS 1.10 1.15 1.20 PGI2 0.9 0.95 1 VS33 Undervoltage threshold 2 2.2 2.4 VS5 3.3 3.5 3.7 VS12 8.5 9 9.5 Input offset voltage for OCP comparators Ilkg VOL –5 Leakage current (PGO) PGO = 5 V Low-level output voltage (PGO) I(sink) = 10 mA, VDD = 4.5 V Short-circuit protection delay 3.3 V, 5 V PGI to PGO td(1) Delay time PGI to FPO UNIT V V 5 mV 5 µA 0.4 V ms 49 75 114 200 300 450 VDD = 5 V 3.2 4.8 7.2 VDD = 5 V 88 150 225 µs TYP MAX UNIT ms PGI to PGO Noise deglitch time PGI to FPO 12-V UVP to FPO PSON control PARAMETER II VIH Input pullup current VIL t(b) Low-level input voltage td(2) Delay time (PSON to FPO) TEST CONDITIONS MIN PSON = 0 V High-level input voltage µA –120 2.4 Debounce time (PSON) VDD = 5 V VDD = 5 V V 1.2 V 24 38 57 ms tb+1.1 tb+2.3 tb+4 ms TYP MAX UNIT total device PARAMETER IDD TEST CONDITIONS Supply current PSON = 5 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN 1 mA 9 TPS3513 PC POWER SUPPLY SUPERVISORS SLVS313 – FEBRUARY 2001 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE INPUT CURRENT (PSON) vs INPUT VOLTAGE (PSON) 400 20 VDD = 4 V TA = –40°C 0 TA = 85°C TA = 25°C 200 I I – Input Current – µ A I DD – Supply Current – µ A 300 100 TA = 0°C 0 –100 –20 –40 –60 –80 TA = –40°C TA = 0°C TA = 25°C TA = 85°C –100 –200 PGI = 1.4 V PSON = 5 V –120 –300 0 2.5 5 10 7.5 12.5 –140 15 0 1 VDD – Supply Voltage – V 2 Figure 4 VOL– Low-Level Output Voltage – mV VOL – Low-Level Output Voltage – V 7 800 3 TA = 85°C 2 TA = 25°C TA = –40°C 1 TA = 0°C VDD = 4 V PSON = GND Exploded View 700 600 TA = 85°C 500 400 300 0 20 40 60 80 100 IOL – Low-Level Output Current – mA 120 TA = –40°C TA = 25°C 200 TA = 0°C 100 0 0 5 10 15 20 IOL – Low-Level Output Current – mA Figure 6 10 6 LOW-LEVEL OUTPUT VOLTAGE (FPO) vs LOW-LEVEL OUTPUT CURRENT (FPO) VDD = 4 V PSON = GND 0 5 Figure 5 LOW-LEVEL OUTPUT VOLTAGE (FPO) vs LOW-LEVEL OUTPUT CURRENT (FPO) 4 4 3 VI – Input Voltage – V Figure 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TPS3513 PC POWER SUPPLY SUPERVISORS SLVS313 – FEBRUARY 2001 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE (PGO) vs LOW-LEVEL OUTPUT CURRENT (PGO) LOW-LEVEL OUTPUT VOLTAGE (PGO) vs LOW-LEVEL OUTPUT CURRENT (PGO) 4 600 VOL – Low-Level Output Voltage – mV VOL – Low-Level Output Voltage – V VDD = 4 V PSON = GND TA = 85°C 3 2 TA = –40°C TA = 25°C 1 TA = 0°C 0 0 25 50 75 100 125 IOL – Low-Level Output Current – mA VDD = 4 V PSON = GND Exploded View 500 400 TA = 85°C 300 TA = 25°C 200 TA = –40°C 100 TA = 0°C 0 150 0 5 10 15 IOL – Low-Level Output Current – mA Figure 9 NORMALIZED SENSE THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE AT VDD CURRENT RATIO vs FREE-AIR TEMPERATURE 8 1.001 VDD = 4 V PSON = GND 1 7.99 RI = 30 kΩ I(IS5) I(ref) 0.999 Current Ratio Normalized Input Threshold Voltage – VIT(TA)/VIT(25 °C) Figure 8 20 0.998 0.997 7.98 7.97 0.996 7.96 0.995 0.994–40 60 –15 10 35 TA – Free-Air Temperature – °C 85 7.95 –40 –20 0 20 40 60 TA – Free-Air Temperature – °C Figure 10 80 Figure 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPS3513 PC POWER SUPPLY SUPERVISORS SLVS313 – FEBRUARY 2001 MECHANICAL DATA N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 16 PINS SHOWN PINS ** 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23,37) 0.975 (24,77) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21,59) 0.940 (23,88) DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 8 0.070 (1,78) MAX 0.035 (0,89) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gauge Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 14/18 PIN ONLY 4040049/D 02/00 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001). 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS3513 PC POWER SUPPLY SUPERVISORS SLVS313 – FEBRUARY 2001 MECHANICAL DATA (CONTINUED) D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°–8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS3513D ACTIVE SOIC D 14 50 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS3513DR ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TPS3513N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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