TI TPS65124RGT

TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
SINGLE-INDUCTOR QUADRUPLE-OUTPUT
TFT LCD POWER SUPPLY
•
FEATURES
•
•
•
•
Main Output, VMAIN
– Adjustable Voltage, 3.0 V to 5.6 V/25 mA
– Post-Regulated for Low Ripple (5mVPP)
– ±0.8% Typical Accuracy
– Efficiency up to 83%
Positive Output, VGH
– Adjustable Voltage up to 20 V/2 mA
– ±3% Typical Accuracy
Negative Output, VGL
– Adjustable Voltage down to -18 V/2 mA
– ± 3% Typical Accuracy
Auxiliary 1.8 V/3.3 V Linear Regulator
•
•
•
•
Automatic or Programmable Power Sequencing
Complete 1 mm Component Profile Solution
2.5 V to 5.5 V Input Voltage Range
Output Short Circuit Protected
16-Pin QFN Package (3 × 3 × 0,9 mm)
APPLICATIONS
•
•
•
•
•
•
•
•
Small Form Factor a-Si and LTPS TFT LCD
Cell Phones, Smart Phones
PDAs, Pocket PCs
Portable DVD
Digital-Still Cameras, Camcorders
Handheld Instruments
Portable GPS
Car Navigation Systems
DESCRIPTION
The TPS6512x DC-DC converter supplies all three voltages required by amorphous-silicon (a-Si) and
low-temperature poly-silicon (LTPS) TFT-LCD displays. The compact layout of the TPS6512x uses a single
inductor to generate independently-regulated positive and negative outputs. A free-running variable peak current
PWM control scheme time-multiplexes the inductor between outputs. This control architecture operates at a
pseudo-fixed-frequency to provide fast response to line and load transients while maintaining a relatively
constant switching frequency and high efficiency over a wide range of input and output voltages. Due to the high
switching frequency capability of the device, inexpensive and ultra-thin 8.2 or 10 µH inductors can be used.
The main output, VMAIN, is post-regulated to provide a low-ripple source drive voltage for the LCD display. The
auxiliary outputs generate a boosted output voltage, VGH, up to 20 V, and a negative output voltage, VGL, down to
-18 V for the LCD gate drive. The device has internal current limiting for high reliability under fault conditions.
Additionally, the device offers a fixed output linear regulator for the LCD logic circuitry.
VIN
2.7 V to 5.5 V
VIN
C1
2.2 µ F
D1
GATE
VGH
up to 20 V/2 mA
C2
100 nF
R1
FBH
80
VGL
SWN
R3
L1
10 µ H
RUN
EN
VGH
90
R4
down to −18 V/2 mA
70
C3
100 nF
60
50
SWP
FBL
40
VMAIN
VMAIN
FBM
BOOT
R5
C4 R6
1µ F
R2
30
3.0 V to 5.3 V/25 mA
20
C5
220 nF
10
Core Converter Efficiency − %
100
TPS65123
24.0
16.0
20.0
8.0
12.0
0.9
Figure 1. Typical Application
VIN − Input Voltage − V
0.1
A
4.0
PGND
0.5
AGND
A
5.5
5.2
4.7
4.0
3.2
2.8
2.6
2.4
2.3
0
IBOOT − Load Current − mA
Figure 2. Core Converter Efficiency
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
INTEGRATED
LINEAR REGULATOR
POWER SEQUENCING
PACKAGE
PART NUMBER (1)
PACKAGE
MARKING
Fixed 3.3V output voltage
Automatic Power-Up/Down
3 × 3 QFN-16
TPS65120RGT
BKA
Fixed 1.8V output voltage
Automatic Power-Up/Down
3 × 3 QFN-16
TPS65121RGT
BKB
NO
Automatic Power-Up/Down
3 × 3 QFN-16
TPS65123RGT
BKC
NO
Programmable
Power-Up/Down
3 × 3 QFN-16
TPS65124RGT
BKD
TA
-40 to 85°C
(1)
The xyz package is available in tape and reel. Add R suffix (xyzR) to order quantities of TBD parts. Add T suffix (xyzT) to order
quantities of 250 parts.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VIN
Input voltage (2)
Voltage (2)
-0.3 V to +6 V
SWN
VIN - 24 V to VIN +0.3 V
SWP
- 0.3 V to +23 V
VGH
- 0.3 V to +21 V
VMAIN, LDOIN, LDOOUT, ENVGL, ENVGH
- 0.3 V to +6 V
BOOT
- 0.3 V to +6.2 V
(2)
-0.3 V to VIN + 0.3 V
Input voltage at GATE, EN, RUN
Power dissipation
Internally limited
Operating temperature range
-40°C to 85°C
Maximum operating junction temperature, TJ(max)
135°C
Storage temperature range
(1)
(2)
65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS (1)
(1)
2
PACKAGE
RθJA
DERATING FACTOR ABOVE TA = 25°C
RGT
68°C/W
15mW/°C
Maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power
dissipation at any allowable ambient temperature is PD = [TJ(max)-TA]/ θJA.
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
ELECTRICAL CHARACTERISTICS
VIN = 3.6 V, EN = RUN = VIN, L = 10 µH, TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CONVERTER STAGE
Input voltage for full load operation
RL_MAIN≥ 330 Ω at VMAIN = 5 V,
RL_VGH≥ 12 kΩ at VGH = 12 V,
RL_VGL≥ 12 kΩ at VGL = -12 V,
VLDOIN= GND, TA = -40°C to 85°C
2.7
Minimum input voltage for start-up
RL_MAIN≥ 660 Ω at VMAIN = 5 V,
RL_VGH≥ 24 kΩ at VGH = 12 V,
RL_VGL≥ 24 kΩ at VGL = -12 V,
VLDOIN= GND, TA = -20°C to 85°C
2.5
f
Switching frequency
RL_MAIN = 250 Ω at VMAIN = 5 V
VLDOIN= ENVGH = ENVGL = GND
PGH
Output power on VGH
PGL
Output power on VGL
PTOT
Total output power on
VBOOT + VGH + VGL
VIN
5.5
V
4.0
VIN≥ 2.7 V
35
VIN≥ 2.5 V
15
VIN≥ 2.7 V
35
VIN≥ 2.5 V
15
VIN≥ 2.5 V
60
VIN≥ 2.7 V
120
VIN≥ 3 V
150
VIN≥ 4.5 V
250
MHz
mW
mW
mW
η
Power efficiency
VMAIN = 5.0 V, IBOOT = 20 mA,
VGH = 15 V, VGL = -10 V,
IGH = IGL = 100 µA, VLDOIN = GND
ILIM
P-MOS1 current limit
2.7 V ≤ VIN≤ 5.5 V
150
ISTART-UP
P-MOS1 start-up current limit
2.7 V ≤ VIN≤ 5.5 V
65
VIN = VGS = 3.6 V
2.5
4.3
VIN = VGS = 2.5 V
3.8
6.9
VBOOT = VGS = 3.7 V
1.9
3.5
VBOOT = VGS = 5 V
1.4
2.3
0.01
1
0.01
1
P-MOS1 switch on-resistance
rDS(ON)
N-MOS1 switch on-resistance
P-MOS1 leakage current
N-MOS1 leakage current
VDS = 6 V
V
83%
200
mA
mA
Ω
Ω
µA
N-MOS2 + P-MOS2 forward voltage drop
VGS = VBOOT = 5.5 V, VSWP = 2 V,
IBOOT = ID = 50 mA
400
600
mV
N-MOS3 + D1 forward voltage drop
VGS = VBOOT = 5.5 V, VSWP = 2 V,
IGH = ID = 50 mA
900
1100
mV
IMAIN = IGH = IGL = 0 mA,
VGH = +15 V, VGL = -15 V,
VMAIN = 5 V, VFBH = VFBM = +1.5 V,
VFBL = -0.2 V, VBOOT = 5.25 V,
VLDOIN = GND, EN = RUN = VIN,
TA = 25°C
140
170
30
60
0.1
1
TA = 25°C
0.1
1
CONVERTER SUPPLY CURRENT
Quiescent current into VIN
Quiescent current into BOOT
IQ
Quiescent current into VGH
ISD
Shutdown current
µA
µA
3
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.6 V, EN = RUN = VIN, L = 10 µH, TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MAIN OUTPUT
VMAIN
IMAIN
VFBM
IFBM
Main output voltage range
Maximum main output current
Feedback regulation voltage
3.0
VMAIN≤ 5.3 V
25
VMAIN≥ 5.3 V
7.5
5.6
V
mA
2.7 V ≤ VIN≤ 5.5 V, 100 µA ≤ IMAIN≤ 25 mA,
TA = -20°C to 50°C
1.203
1.213
1.223
V
2.7 V ≤ VIN≤ 5.5 V,
0 mA ≤ IMAIN≤ 25 mA
1.195
1.213
1.231
V
0.01
0.1
Feedback input bias current
VFBM= VREF
Load regulation
IMAIN = 0 to 25 mA, VMAIN = 5 V
Minimum dropout voltage
IMAIN = 10 mA
130
5
Main output voltage ripple
IMAIN = 10 mA
ISC_MAIN
Short-circuit current limit
VBOOT = 5.5 V
RDIS_VMAIN
Discharge resistor for power-down sequence
0.006
µA
%/mA
mV
mVP-P
50
10
mA
kΩ
VGH OUTPUT
VGH
VGH output voltage range
IGH
Maximum DC output current
VIN + 0.5
VGH precharge resistor
V
6
mA
1
VFBH
Feedback regulation voltage
2.7 V ≤ VIN≤ 5.5 V, 0 mA ≤ IGH≤ 2 mA
IFBH
Feedback input bias current
VFBH = 0 V
Load regulation
IGH = 0 to 2 mA, VGH = 15 V
Line regulation
VIN = 2.7 V to 5.5 V, IGH = 100 µA
VGH output voltage ripple
200 µA load, VGH = 15 V,
COUT = 220 nF, CFF = 10 pF
RDIS_VGH
20
1.177
Discharge resistor for power-down sequence
kΩ
1.213
1.249
V
0.01
0.1
µA
-0.11
%/mA
0.01
%/V
20
mV
10
kΩ
VGL OUTPUT
VGL
VGL Output voltage range
IGL
Maximum DC output current
VFBL
Feedback regulation voltage
2.7 V ≤ VIN≤ 5.5 V, 0 mA ≤ IGL≤ 2 mA
0
0.036
V
IFBL
Feedback input bias current
VFBL = 0 V
0.01
0.1
µA
Load regulation
IGL = 0 to 2 mA, VGL = -15 V
0.13
%/mA
Line regulation
VIN = 2.7 V to 5.5 V, IGL = 100 µA
0.1
%/V
VGL output voltage ripple
200 µA load, VGL = -15 V,
COUT = 220 nF
20
mV
4
-18
-2.5
6
-0.036
V
mA
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.6 V, EN = RUN = VIN, L = 10 µH, TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LINEAR REGULATOR STAGE - AUXILIARY OUTPUT
VLDOIN
Input voltage range
2.5
5.8
V
1.8
VLDOIN
-0.5
V
VLDOOUT
Output voltage range
ILDOOUT
Maximum output current
ISC_LDO
Short-circuit current limit
VLDOOUT = 0 V
Minimum dropout voltage
ILDOOUT = 10 mA
Total accuracy
2.5 V ≤ VLDOIN ≤ 5.5 V,
0 mA ≤ ILDOOUT≤ 20 mA
Load regulation
ILDOOUT = 0 to 20 mA
0.006
%/mA
Line regulation
VLDOIN = VLDOOUT + 0.5 V (min 2.5 V)
to 5.5 V, ILDOOUT = 20 mA
0.013
%/V
IQ_LDO
Linear regulator quiescent current
VLDOIN = VLDOOUT + 0.4 V (min 2.5 V),
TA = 25°C
11
20
µA
ISD_LDO
Linear regulator shutdown current
GATE = VIN
0.2
1
µA
VGATE < 500 mV
100
kΩ
100
kΩ
20
mA
50
mA
400
mV
±3%
GATE DRIVER
Gate output pull-down resistance
Gate output pull-up resistance
VIH
High level input voltage
VIL
Low level input voltage
1.4
V
0.4
V
2.3
V
UNDERVOLTAGE LOCKOUT
VUVLO
Undervoltage lockout threshold
VIN falling
2.15
LOGIC SIGNALS EN, RUN, ENVGL, ENVGH
VIH
High level input voltage
VIL
Low level input voltage
ILKG
Logic input leakage current
EN, RUN pin pull-down resistance
1.4
V
0.4
ENVGL, ENVGH = VIN or GND (TPS65124)
0.01
0.1
EN, RUN = VIN
0.01
0.1
EN, RUN ≤ 0.4 v
100
V
µA
kΩ
5
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
PIN ASSIGNMENTS
FBH
AGND
4
9
5
6
7
8
2
VGH
FBH
SWP
3
RUN
16
15
14
13
12
PGND
BOOT
ENVGL
Exposed
11
Thermal Die*
3
10
AGND
ENVGH
4
FBH
9
5
6
7
8
VMAIN
AGND
BOOT
SWN
VGH
Exposed
11
Thermal Die*
10
AGND
GATE
2
1
VIN
SWN
SWP
VIN
RUN
EN
AGND
8
BOOT
PGND
FBL
7
1
FBM
6
13
12
EN
VMAIN
5
15 14
PGND
AGND
9
GATE
SWP
SWN
Exposed
11
Thermal Die*
10
AGND
16
TPS65124
(TOP VIEW)
FBM
LDOOUT
4
TPS65123
(TOP VIEW)
FBL
3
13
12
VMAIN
LDOIN
VIN
2
15 14
AGND
RUN
16
FBL
1
FBM
EN
GATE
TPS65120/1/2
(TOP VIEW)
VGH
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
VIN
15
I
This is the input voltage pin of the device.
GATE
16
I/O
RUN
2
I
RUN controls the external P-Channel MOSFET. This pin must be terminated and not be left floating. Forcing
this pin to a logic-high level turns on the external MOSFET switch.
EN
1
I
This is the enable pin of the multiple-output dc-to-dc converter. This pin must be terminated and not be left
floating. A simultaneous logic-high level on EN and RUN enables the converter and a logic-low shuts down
the device.
SWN
14
I/O
Connect the inductor to this pin. This pin is connected to the source of the high-side MOSFET switch.
SWP
13
I/O
Connect the inductor to this pin. This pin is connected to the drain of the low-side MOSFET switch.
PGND
12
O
Power ground. Connect to AGND underneath the IC.
VGH
10
O
Positive output
BOOT
11
O
Provides a bootstrapped supply for the rectifier MOSFET driver, enabling the gate of the MOSFET to be
driven above the output voltage.
VMAIN
8
I
Main output
FBH
9
I
Feedback pin for the positive output voltage divider. Regulates to 1.213 V nominal.
FBL
5
I
Feedback pin for the negative output voltage divider. Regulates to 0 V nominal. Connect feedback resistor
divider between VGL and main output.
FBM
6
I
Feedback pin for the main output voltage divider. Regulates to 1.213V nominal.
This pin can either be the gate driver output to an external small P-Channel MOSFET (see application
section), or an active high control input. Pulling GATE above the 1.4 V logic-high level and RUN to a logic-low
level disables the integrated active power-down sequencing.
Analog ground. Connect to power ground (PGND) underneath IC. Pins 3 and 4 are only used for AGND in
TPS65123.
AGND
7, 3, 4
LDOIN
3
I
Auxiliary linear regulator input. If this pin is connected to GND, the voltage regulator is disabled
(TPS65120/1/2). The low-dropout series-pass regulator (LDO) is enabled according to the GATE signal
timing.
LDOOUT
4
O
Auxiliary linear regulator output (TPS65120/1/2).
ENVGL
3
I
Enable pin for negative output (TPS65124). This pin should be terminated and not be left floating.
ENVGH
4
I
Enable pin for positive output (TPS65124). This pin should be terminated and not be left floating.
6
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
FUNCTIONAL BLOCK DIAGRAM - TPS65120/1/2/3
VIN
GATE
Power Down Seq Off
100kR
Undervoltage
Lockout
Bias Supply
Current Limit
Comparator
VMAIN
Oscillator
P−MOS1
Ton
RUN
S
EN
Min Off Time
SWN
EN
V REF
R
BOOT
SWP
N−MOS3
D1
VGH
BOOT
V REF
RDIS_VGH
R
FBH
R
N−MOS2
P−MOS2
FBL
BOOT
Control
Logic
VMAIN
BOOT
FBM
Power Up/Down
Sequencer
LDO
EN
VMAIN
R DIS_VMAIN
Power Down Seq Off
V REF= 1.213V
Bandgap
BOOT
N−MOS1
AGND
PGND
LDOIN
LDO
LDOOUT
EN_LDOAUX
NOT PRESENT IN TPS65123
7
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
FUNCTIONAL BLOCK DIAGRAM - TPS65124
GATE
VIN
Power Down Seq Off
Undervoltage
Lockout
Bias Supply
100kR
Current Limit
Comparator
VMAIN
P−MOS1
Ton
Oscillator
RUN
S
Min Off Time
SWN
EN
EN
V REF
R
BOOT
SWP
N−MOS3
D1
VGH
BOOT
V REF
RDIS_VGH
R
Control
FBH
Logic
P−MOS2
R
N−MOS2
BOOT
FBL
BOOT
FBM
Power Up/Down
VMAIN
EN
Sequencer
LDO
VMAIN
RDIS_VMAIN
Power Down Seq Off
ENVGH
BOOT
ENVGL
N−MOS1
AGND
Bandgap
8
V REF = 1.213V
PGND
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
PARAMETER MEASUREMENT INFORMATION
TPS65120
V IN
2.7 V to 5.5 V
VIN
C1
2.2 F
SWN
VGH
R1
C2
220 nF
L1
10 H
RUN
EN
GATE
V GH
up to 20 V/2 mA
D1
FBH
R3
R4
SWP
FBL
VMAIN
FBM
BOOT
C4
1F
R2
VGL
down to −18 V/2 mA
C3
220 nF
R5
V MAIN
3.0 V to 5.3 V/20 mA
R6
C5
220 nF
LDOIN
VAUX
3.3 V/20 mA
LDOOUT
AGND
A
PGND
A
C6
220 nF
List of Components:
U1 = TPS6512x
L1 = EPCOS SIMID1812-C
D1 = ZETEX ZUMD54C
CX = X5R/X7R
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
η
Core converter efficiency
Main output efficiency
VMAIN
vs Load current
3
vs Input voltage
4
vs Load current
5
vs Input voltage
6
Output ripple voltage
DC output voltage
7
vs Load current
Load transient response
8
9
VGH, VGL
Positive, negative output ripple voltage
VGH
DC output voltage
vs Load current
10, 11
12
VGL
DC output voltage
vs Load current
13
fs
Switching frequency
vs Load current
14
IQ
No load quiescent current
vs Input voltage
15
Power-Up Sequencing (TPS65120)
16
Power-Down Sequencing (TPS65120)
17
9
TPS65120, TPS65121, TPS65123, TPS65124
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SLVS531 – JUNE 2004
TPS65124
CORE CONVERTER EFFICIENCY
vs
LOAD CURRENT
TPS65124
CORE CONVERTER EFFICIENCY
vs
INPUT VOLTAGE
100
100
VMAIN = 5 V
70
60
50
40
30
20
1
10
IBOOT = 15 mA
85
80
IBOOT = 5 mA
75
70
60
0
0.1
90
65
VIN = 3.6 V
ENVGL = ENVGH = GND
10
VIN = 3.6 V,
VMAIN = 5 V,
ENVGL = ENVGH = GND
95
80
Core Converter Efficiency − %
Core Converter Efficiency − %
90
2.7
100
3.1
IBOOT − Output Current − mA
Figure 3.
Figure 4.
MAIN OUTPUT EFFICIENCY
vs
LOAD CURRENT
MAIN OUTPUT EFFICIENCY
vs
INPUT VOLTAGE
100
5.1
5.5
100
VIN = 3.6 V
95
VMAIN = 5 V,
VGH = 15 V @ 200 A,
VGL = −10 V @ 200 A
90
Main Output Efficiency − %
90
Main Output Efficiency − %
3.5
3.9
4.3
4.7
VIN − Input Voltage − V
80
70
60
VMAIN = 3.3 V,
VGH = 7.5 V @ 200 A,
VGL = −3 V @ 200 A
50
80
75
70
VMAIN = 5 V @ 5 mA,
VGH = 15 V @ 200 A,
VGL = −10 V @ 200 A
65
60
55
50
40
VMAIN = 5 V @ 10 mA,
VGH = 15 V @ 200 A,
VGL = −10 V @ 200 A
85
VMAIN = 3.3 V @ 10 mA,
VGH = 7.5 V @ 200 A,
VGL = −3 V @ 200 A
45
30
0
2
4
6
8
10
12
14
IMAIN − Output Current − mA
Figure 5.
10
16
18
20
40
2.7
3.1
3.5
3.9
4.3
4.7
VIN − Input Voltage − V
Figure 6.
5.1
5.5
TPS65120, TPS65121, TPS65123, TPS65124
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SLVS531 – JUNE 2004
MAIN DC OUTPUT VOLTAGE
vs
LOAD CURRENT
MAIN OUTPUT RIPPLE VOLTAGE
5.05
VIN = 3.6 V,
VGH = 15 V @ 200 A,
VGL = −10 V @ 200 A
5.04
5.03
VMAIN
(10 mV/div,
5 V Offset)
V MAIN − Output Voltage − V
VBOOT
(50 mV/div,
5.8 V Offset)
VIN = 3.6 V,
VMAIN = 5 V @ 20 mA,
ENVGL = ENVGH = LOW
5.02
5.01
5
4.99
4.98
4.97
4.96
t − Time − 5 s/div
4.95
0
2
4
6
8
10 12 14 16
IMAIN − Output Current − mA
Figure 7.
Figure 8.
MAIN OUTPUT LOAD
TRANSIENT RESPONSE
POSITIVE, NEGATIVE OUTPUT RIPPLE
VIN = 3.6 V,
VMAIN = 5 V,
ENVGL = ENVGH = LOW
18
20
VIN = 3.6 V,
VMAIN = 5 V @ 5 mA,
VGH = 15 V @ 100 A,
VGL = −10 V @ 100 A
VMAIN
(50 mV/div,
5 V Offset)
VGH
(50 mV/div,
AC Coupled)
VGL
(20 mV/div,
AC Coupled)
IMAIN
(10 mA/div)
COUT = 220 nF
t − Time − 20 s/div
t − Time − 10 s/div
Figure 9.
Figure 10.
11
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
POSITIVE, NEGATIVE OUTPUT
RIPPLE VOLTAGE
POSITIVE OUTPUT (VGH) LOAD REGULATION
15.15
VIN = 3.6 V,
VMAIN = 5 V @ 5 mA,
VGH = 15 V @ 100 A,
VGL = −10 V @ 100 A
10 pF Feed-Forward
Capacitor Across R1
15.10
VGH − DC Output Voltage − V
VGH
(20 mV/div,
AC Coupled)
VGL
(20 mV/div,
AC Coupled)
15.05
15
14.95
14.90
14.85
t − Time − 10 s/div
1
IGH − Output Current − mA
Figure 12.
NEGATIVE OUTPUT (VGL) LOAD REGULATION
SWITCHING FREQUENCY
vs
LOAD CURRENT
10
10
VIN = 3.6 V,
VMAIN = 5 V @ 5 mA,
VGH = 15 V @ 200 A
VIN = 3.6 V,
VMAIN = 5 V,
ENVGH = ENVGL = GND
−9.94
Switching Frequency − MHz
VGL − DC Output Voltage − V
0.1
Figure 11.
−9.90
−9.92
VIN = 3.6 V,
VMAIN = 5 V, @ 5 mA
VGL = −10 V @ 200 A
−9.96
−9.98
−10
−10.02
−10.04
−10.06
−10.08
−10.10
0.1
1
IGL − Output Current − mA
Figure 13.
12
10
1
0.1
1
10
IMAIN − Output Current − mA
Figure 14.
100
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
QUIESCENT CURRENT
vs
INPUT VOLTAGE
TPS65120
POWER-UP SEQUENCING
300
RUN
VLOGIC
(5 V/div)
250
I Q − Quiescent Current − A
VLOGIC
200
VMAIN
VMAIN
(2 V/div)
150
VGH
VGH
(5 V/div)
100
50
VMAIN = 3.3 V, VGH = 7.5 V, VGL = −3 V
No-Load Quiescent Current Includes
Output Voltage Divider Network Bias Current
VGL
(5 V/div)
VGL
VIN = 3.6 V, EN = HIGH,
RMAIN = 1 k,
RGH = 120 k,
RGL = 100 k,
0
2.5 2.8 3 3.3 3.5 3.8 4
4.3 4.5 4.8 5 5.3 5.5
t − Time − 100 s/div
VIN − Input Voltage − V
Figure 15.
Figure 16.
TPS65120
POWER-DOWN SEQUENCING
RUN
VLOGIC
VLOGIC
(5 V/div)
VMAIN
(2 V/div)
VGH
(5 V/div)
VGL
(5 V/div)
VMAIN
VGH
VGL
VIN = 3.6 V, EN = HIGH,
RMAIN = 1 k,
RGH = 120 k,
RGL = 100 k,
t − Time − 5 ms/div
Figure 17.
13
TPS65120, TPS65121, TPS65123, TPS65124
SLVS531 – JUNE 2004
www.ti.com
DETAILED DESCRIPTION
The standard application circuit (Figure 1) of the TPS65120 is a complete power supply for TFT LCD displays.
The circuit generates four independent supplies for the source driver (VMAIN), the gate drivers (VGH, VGL) and a
logic supply for the timing controller. The input voltage range is from 2.5 V to 5.5 V.
The TPS65120/1/2 contains a high-performance switching regulator and two low-dropout linear regulators
(LDOs). One of the LDOs generates VMAIN and the other powers the logic inside the panel. The TPS65123
includes only one linear regulator to provide the main output with low ripple voltage and can be set from 3.0 V to
5.3 V with an external resistor voltage divider. The TPS65124 integrates programmable power sequencing for
highest flexibility.
OPERATION
The TPS6512x generates both positive and negative supply voltages using a single inductor. It alternates
between acting as a step-up converter and an inverting converter on a cycle-by-cycle basis. All output voltages
are independently regulated.
A free-running, variable-peak-current PWM control scheme is used to time-multiplex the inductor between BOOT,
VGH, and VGL outputs. This inherently-stable control architecture operates at a pseudo fixed frequency, providing
fast response to line and load transients while maintaining a relatively constant switching frequency and high
efficiency over a wide range of input and output voltages.
During the first cycle of operation, internal switches N-MOS1 and P-MOS1 are turned on. SWN connects to VIN,
SWP pulls to ground and the inductor current rises. Once the inductor current reaches the DC current limit (ILIM)
of 150 mA (typ) the internal control logic can either turn off N-MOS1 or P-MOS1 to service the requesting output.
Depending on the required output power, the converter starts another cycle or enters a pulse-skipping
modulation scheme to increase efficiency under light loads. The current into the SWN pin measures the inductor
current. The TPS6512x controls the inductor current to regulate BOOT, VGH, and VGL output voltages.
To achieve low ripple voltage and high accuracy, the main output (VMAIN) is post-regulated by an integrated LDO.
This LDO regulator regulates energy from the BOOT output down to 5.3 V (max). To achieve the highest
efficiency, the BOOT voltage is regulated to minimize the dropout voltage across the LDO to approximately VMAIN
+ 0.5 V.
In addition, the VMAIN, VGH, VGL outputs are monitored for fault conditions that last longer than the fault-timer
period of 100 µs (typ). The device goes into a latched shutdown state in case of a fault condition.
Soft Start
The TPS6512x has an internal soft-start circuit that limits the inrush current during startup. This prevents possible
voltage drops of the input voltage in case the battery or a high impedance power source is connected to the input
of the device.
The device powers up by precharging the BOOT output capacitor to VIN. During the precharge phase, the
current through the rectifying switch N-MOS2 is limited. This also limits the output current under short-circuit
conditions on the BOOT output. To ensure proper startup of the device, the BOOT output must be left unloaded
during the precharge phase.
After the precharge phase, the converter operates with an ISTART-UP current limit of 65 mA (typ), then increases
gradually to the full current limit of 150 mA (typ).
Undervoltage Lockout
To ensure that the input voltage is high enough for reliable operation, the TPS6512x includes an under-voltage
lockout (UVLO) circuit. The UVLO threshold at the VIN pin is 2.15 V (typ) falling and 2.25 V (typ) rising. The 100
mV (typ) hysteresis prevents supply transients from causing restarts.
Once the input voltage exceeds the UVLO rising threshold, the controller can enable the reference voltage and
precharges BOOT. When the input voltage falls below the UVLO falling threshold, the controller turns off the
reference and all the regulator outputs, and pulls GATE high with an internal 100 kΩ resistor to turn off P1
(Figure 18).
14
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
DETAILED DESCRIPTION (continued)
Enable and Power Sequencing (TPS65120/1/2/3)
To correctly power up most TFT panels, the gate-drive supplies must be sequenced such that the negative
supply (VGL) powers up before the positive supply (VGH). The TPS65120/1/2/3 controls this sequence through an
enable pin.
Once RUN is high, the TPS65120/1/2/3 turns on the external P-channel MOSFET P1 (see Figure 18) by pulling
GATE low. GATE is pulled down with a 100 kΩ resistor. The DC/DC converter then starts, enabling the BOOT
output.
Pulling the enable pin (EN) high enables the MAIN output. When the output voltage VMAIN has reached 90% of its
nominal value, the negative output enables. VGH is delayed until the negative voltage has reached 90% of its
nominal value.
Pulling the RUN pin low shuts down the device. Power-down sequencing starts by switching off VGH and VGL.
The VGH output capacitor is actively discharged by an internal resistor while VGL is only discharged by its
feedback voltage divider. The required time to discharge the output capacitor at VGL output depends on the load
current. Once VFBL has reached 1.2 V (typ) the main output is turned off followed by the output voltage VLOGIC.
This sequence is shown in Figure 19.
When no power sequencing is required on the digital supply voltage (VLOGIC), tie EN and RUN signals together
and GATE can be connected to a logic-high level to disable the power-down sequencer. Each output turns off
depending upon load current and output capacitance.
P1
VLOGIC = 3.3 V
R9
R10
TPS65120
VIN = 3.3 V
VIN
C1
GATE
VGH
R1
C2
FBH
RUN
C7
GATE, EN_LDOAUX
D1
5.75V
VGL
SWN
R3
L1
RUN
EN
VGH
VIN
VBOOT
C3
R4
SWP
FBL
VLOGIC, EN
VMAIN
VMAIN
FBM
BOOT
R5
VMAIN
C5
C4
R2
R6
VGL
LDOIN
LDOOUT
AGND
A
PGND
A
VGH
Figure 18. Power Sequencing on Digital Supply Voltage,
VLOGIC
Figure 19. TPS65120/1/2/3 Power Sequence
15
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
DETAILED DESCRIPTION (continued)
Enable and Power Sequencing (TPS65124)
The TPS65124 controls the power sequencing of VLOGIC, VMAIN, VGH and VGL with four separate enable pins.
These pins must be terminated and not be left floating to prevent instability.
Once RUN is pulled high and the input voltage on VIN exceeds the rising input UVLO threshold, the reference is
turned on and the external P-channel MOSFET P1 (see Figure 20) is switched on by pulling GATE low. The
GATE is pulled down with a 100 kΩ resistor. The DC/DC converter then starts up, enabling the BOOT output.
Pulling enable pin high (EN) powers on the MAIN output. This power sequencing must occur before the gate
voltages are enabled. Conversely VGL and VGH output voltages must be turned off by pulling ENVGL and ENVGH
inputs to ground before the MAIN output is switch off.
To clamp the VGLoutput near zero when the MAIN output is still on, an external diode (D2) can be used. In some
applications this diode may already be implemented in the display.
P1
VLOGIC = 3.3V
VIN
D2
TPS65124
VIN = 3.3V
VIN
EN
VGH
R1
C2
FBH
R4
VBOOT
VMAIN
VMAIN
FBM
R5
ENVGH
ENVGL
AGND
A
VLOGIC
C5
BOOT
C4
ENVGL
5.75V
C3
SWP
FBL
R2
ENVGH
GATE
R3
L1
RUN
GATE
VGH
RUN
VGL
C1
EN
optional
D1
SWN
R6
EN
VMAIN
PGND
ENVGH
A
VGH
ENVGL
VGL
Figure 20. Power Sequencing on Digital Supply Voltage,
VLOGIC
Figure 21. TPS65124 Programmable Power Sequence
Fault Protection
All TPS6512x outputs are protected against a short circuit to ground. During steady-state operation, if the output
VMAIN, VGH or VGL falls below its fault detection threshold the device simultaneously turns off all three outputs.
Once VMAIN comes down to 700 mV typ, the GATE output is pulled to VIN, the auxiliary LDO (TPS65120/1/2) is
disabled and the device enters a shutdown state.
The auxiliary LDO present in TPS65120/1/2 has an integrated current foldback circuit for reliable short-circuit
protection.
The device can be enabled again by toggling the enable pins (RUN, EN) below 0.4 V or by cycling the input
voltage below the UVLO falling threshold (2.15 V typ).
16
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
APPLICATION INFORMATION
OUTPUT POWER CAPABILITY
The first step in the design procedure is to calculate the maximum output current for each output under certain
input and output voltage conditions. The TPS6512x uses time-multiplex operation to share the inductive storage
element between BOOT, VGH and VGL outputs. To avoid complex calculations it is recommended to use the
specified output-power data from the electrical characteristics table to determine the maximum output-power
capability.
The following example shows how to proceed for given requirements:
• Input Voltage = 3.0 V
• MAIN Output = 5.0 V @ 10 mA
• VGH output = 12 V @ 500 µA
• VGL output = -12 V @ 300 µA
1. Calculate Maximum Output Power on VGH Output
PGH = VGH × I GH
2. Calculate Maximum Output Power on VGL Output
PGL = VGL × IGL
3. Calculate Maximum Output Power on BOOT Output
2
PBOOT = PMAIN × ηLDO _ MAIN ≈
VMAIN
× IMAIN
VMAIN + 0.5
PBOOT = PMAIN × ηLDO _ MAIN ≈
VMAIN
× IMAIN
VIN
for VIN < VMAIN + 0.5
2
for VIN > VMAIN
4. Maximum Output Power Verification
The electrical characteristics table states that for VIN > 3.0 V, the maximum power on VGH and VGL outputs
must be lower than 35 mW each. Furthermore, the total output power (PBOOT + PGH + PGL) must be lower than
150 mW.
In our design example, PGH = 6 mW, PGL = 3.6 mW, and PBOOT = 55 mW. Since these numbers are well below
the specified values, we can conclude that TPS6512x can reasonably power such a display.
SETTING THE OUTPUT VOLTAGE
The output voltages are defined as shown in Figure 22.
R5 + R6
R6
with an internal reference voltage VFBM typical = 1.213V.
VMAIN = VFBM ×
R1+ R2
R2
with an internal reference voltage VFBH typical = 1.213V.
VGH = VFBH ×
VGL = VMAIN ×
R3
R4
To minimize the operating quiescent current, set R2, R4 and R6 in the range 100 kΩ to 300 kΩ. Great care
should be taken to route the FBx lines away from noise sources such as the inductor or the SWN and SWP lines.
A feed-forward capacitor across the upper feedback resistor (R1, R3) on VGH and VGL outputs can be used to
provide more overdrive for the error comparator. This feed-forward capacitor helps to reduce the output ripple
voltage. A good starting value is 10 pF.
17
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
APPLICATION INFORMATION (continued)
The larger the feed-forward capacitor the worse the load regulation of the device. Therefore, when concern for
load regulation is paramount, select a capacitor value as small as possible. Another possibility to further reduce
ripple voltage on VGH and VGL outputs is to increase output-capacitor values (C2, C3).
VIN
2.7 V to 5.5 V
TPS65120
VIN
C1
2.2 µF
L1
10 µ H
RUN
EN
VGH
up to 20 V/2 mA
GATE
VGH
R1
C2
100 nF
D1
FBH
VGL
down to −18 V/2 mA
SWN
R3
C3
100 nF
R4
SWP
FBL
VMAIN
FBM
BOOT
VMAIN
3.0 V to 5.3 V/25 mA
R5
C4
1 µF
R2
C5
220 nF
R6
LDOIN
VAUX
3.3 V/20 mA
LDOOUT
AGND
A
C6
PGND
A
220 nF
Figure 22. Typical Application
INDUCTOR SELECTION
Since the control scheme of the TPS6512x device is inherently stable, the inductor value does not affect the
stability of the converter. To operate the TPS6512x properly at full performance, choose inductors in the range
8.2 µH to 10 µH.
The selection of the inductor is primarily based on the required output power. The variable peak current PWM
control scheme used in TPS6512x automatically adapts the peak inductor current (between 65mA typ. and
150mA typ.) depending on output power and input voltage.
At moderate loads, the converter typically operates with a peak inductor current in the range of 65mA to 100mA,
allowing the use of inductors in the 0603 case size. In order not to saturate the inductor when operating at a
higher output power, select an inductor with a higher saturation-current rating.
The inductor series in Table 1 from various suppliers have been used with the TPS6512x converter.
Table 1. List of Inductors
MANUFACTURER
TAIYO YUDEN
TDK
18
SERIES
DIMENSIONS
LQ LB1608
1.6 x 0.8 x 0.8 = 1.02 mm3
LQ CB2012
2.0 x 1.2 x 1.2 = 2.88 mm3
LQ CBL2012
2.0 x 1.2 x 1.0 = 2.40 mm3
GLF1608
1.6 x 0.8 x 0.8 = 1.02 mm3
GLF2012
2.0 x 1.2 x 1.2 = 2.88 mm3
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
DIODE SELECTION
To achieve high efficiency, use a Schottky diode. The voltage rating must be higher than the input voltage plus
the absolute value of the negative output. The current rating of the diode must meet the converter peak
inductor-current rating when servicing the VGL output. The main parameter affecting the efficiency of the
converter is the forward voltage and the reverse leakage current of the diode, both should be as low as possible.
The following diodes from different suppliers listed in Table 2 have been used with the TPS6512x converter.
Table 2. List of Diodes
MANUFACTURER
REFERENCE
REVERSE VOLTAGE
ROHM
RB521G-30
30 V
VISHAY
BAT54-HT3
30 V
ZETEX
ZUMD54
30 V
CAPACITOR SELECTION
The TPS65120 converter requires six capacitors. The input capacitor is primarily a function of the board layout.
In designs with long traces, for good input filtering, we recommend a ceramic input capacitor (X5R/X7R type) of
at least 1 µF placed as close as possible to the converter.
To operate properly, the TPS6512x requires a bootstrap capacitor of 1 µF (or larger) on the BOOT output.
Additionally the minimum BOOT capacitance must be larger than two times the capacitor value connected to the
MAIN and AUXILIARY LDO outputs (in case LDO AUX is connected to the BOOT output).
The TPS6512x peak-current control scheme is inherently stable. The filtering capacitors on VGH and VGL
outputs are basically determined as a function of the required current and permissible ripple voltage. For small
form-factor TFT-LCD applications, typical values in the range of 100 nF to 1 µF are usually required. A good
starting point is 220 nF. For high output power on VGH and VGL outputs, the capacitance may need to approach
2 µF.
For stable operation, TPS6512x requires a 220-nF ceramic capacitor on the MAIN and AUXILIARY LDO outputs.
Larger capacitor values can be used to achieve lower output-voltage noise without sacrificing stability.
In general, ceramic X5R types are strongly recommended for their low ESR and ESL and capacitance-versus-bias-voltage stability. Be certain that the capacitors used are rated for the maximum voltage with
adequate safety margin.
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design. If the layout is not carefully
done, the regulator could become unstable, displaying double or missing pulses as well as EMI problems.
Therefore, use wide, short traces for the main current paths. Route these traces first.
Place the input capacitor as close as possible to the IC pins as well as the inductor and output capacitors. Place
the inductor and diode as close as possible to the switch pins to minimize noise coupling into other circuits.
Use a common ground node for power ground and a different one for control ground (AGND) to minimize the
effects of ground noise. Connect these ground nodes together (star point) at any place close to one of the
ground pins of the IC and make sure that small-signal components returning to the AGND pin do not share the
switching-current paths.
Feedback pins and divider networks are high-impedance nodes and should therefore be routed away from the
inductor and shielded with a ground plane or trace to minimize noise coupling into the control loop.
19
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
APPLICATION EXAMPLES
TPS65120
C1
2.2 µF
D1
SWN
VIN
VIN
2.7 V to 5.5 V
RUN
EN
GPIO
VGH
VMAIN
FBM
BOOT
R1
C2
220 nF
R4
C3
220 nF
SWP
FBL
GATE
VGH
up to +20 V/2 mA
VGL
down to −18 V/2 mA
R3
L1
10µH
FBH
VMAIN
3.0 V to 5.3 V/25 mA
R5
C4 R6
1µF
R2
C5
220 nF
LDOIN
VLOGIC = 3.3 V
LDOOUT
C6
220 nF
PGND
AGND
A
A
Figure 23. Complete TFT-LCD Power Supply from 1 cell Li-Ion
TPS65123
VIN
2.7 V to 5.5 V
VIN
D1
VGL
SWN
C1
L1
RUN
EN
RUN
GATE
VGH
R3
C3
220 nF
SWP
FBL
VGH
FBH
R4a
R2
A
R3
R 4a
VMAIN
VMAIN
FBM
BOOT
PGND
AGND
VGL = VMAIN ×
RUN
N−MOS
VISHAY SI1032
R4b
R1
C2
220 nF
R5
C5
220 nF
C4
1 µF R6
A
1.2 − VMAIN


R 4b = R3 
 − R 4a
 VGL _ OFFThreshold − 1.2 
VMAIN = 5.0 V, VGH = 15 V, VGL = −10 V
R3 = 540 kΩ, R4a = 270 kΩ, R4b = 680 kΩ
Figure 24. VGL→ VMAIN Power Down-Sequencing Threshold Shifting
EN
Negative
LDO
VGL2
C7
TPS65121
VIN
VIN
D1
SWN
L1
RUN
EN
GPIO
GATE
VGH
VGH
R1
C2
220 nF
FBH
VGL1
R3
C1
C3 > C7
R4
SWP
FBL
VMAIN
FBM
BOOT
VMAIN
R5
C4 R6
1µ F
R2
C5
220 nF
LDOIN
VLOGIC
LDOOUT
AGND
A
C6
220 nF
PGND
A
Negative LDO = TPS723xx series
Figure 25. Additonal Negative Gate Driver Voltage
20
TPS65120, TPS65121, TPS65123, TPS65124
www.ti.com
SLVS531 – JUNE 2004
TPS65124
VIN
VIN
C1
2.2 µ F
D1
VGL
SWN
L1
RUN
GATE
GPIO1
10 pF
SWP
FBL
R4
VMAIN
FBM
BOOT
R5
EN
VGH
C7
R3
C3
220 nF
VGH
C6
C2
220 nF
R1
10 pF
FBH
R2
GPIO2
ENVGH
GPIO3
ENVGL
VMAIN
C5
C4
2.2 µ F
R6
4.7 µF
PGND
AGND
N&P MOS
C8
100 nF
GPIO4
A
A
N&P MOS = VISHAY Si1016
D1 = VISHAY BAT54A−HT3
Figure 26. Fully Programmable Sequencing Featuring Very Low Gate Ripple Voltage
TPS65124
VIN
VIN
D1
C1
VPOS
R1
FBH
VREF
VMAIN
FBM
BOOT
R2
EN
C5
220 nF
C4
1 µF R6
ENVGH
AGND
VGL
(5V/div)
R5
ENVGL
= 887 kΩ
= 100 kΩ
= R4 = 680 kΩ
= 845 kΩ
= 270 kΩ
VGH
VGH
(5V/div)
VGH
C2
220 nF
R1
R2
R3
R5
R6
C3
220 nF
R4
SWP
FBL
EN
−12 V
R3
L1
RUN
GATE
VPOS
12 V
ENVGH,
ENVGL
(2V/div)
VNEG
SWN
VIN = 3.6V
EN = RUN = HIGH
RGH = 60 kΩ
RGL = 60 kΩ
PGND
A
VGL
A
Figure 27. Dual Output Tracking Regulator with High Accuracy Reference Voltage
TPS65123
VIN
VIN
D1
VGL
SWN
C1
RUN
EN
RUN
GATE
VGH
L1
EN TPS65120 LDO
EN
IN
BOOT
FBH
R2
R4
VMAIN
VMAIN
FBM
A
OUT
C4
2.2
µF
C2
AGND
C3
FBL
VGH
R1
R3
SWP
R5
C5
1uF
PGND
R6
A
External LDO = TPS792xx series
Ext. LDO nominal output voltage setting recommended at 1% lower than VMAIN.
Figure 28. Boosting Main Output Current, IMAIN > 25mA
21
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