TPS22949 TPS22949A www.ti.com SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 CURRENT-LIMITED LOAD SWITCH WITH LOW NOISE REGULATION CAPABILITY Check for Samples: TPS22949, TPS22949A FEATURES 1 • • • • • • Integrated Current Limiter – Input Voltage Range: 1.62 V to 4.5 V – Low ON-Resistance – rON = 300-mΩ at VIN = 4.5 V – rON = 350-mΩ at VIN = 3.3 V – rON = 400-mΩ at VIN = 2.5 V – rON = 600-mΩ at VIN = 1.8 V – Integrated 100-mA Minimum Current Limit – Undervoltage Lockout – Fast-Current Limit Response Time – Integrated Fault Blanking and Auto Restart Stable Without Current Limiter Output Capacitor (TPS22949A Only) Integrated Low-Noise RF LDO – Input Voltage Range: 1.62 V to 4.5 V – Low Noise: 50 μVrms (10 Hz to 100 kHz) – 80-dB VIN PSRR (10 Hz to 10 kHz) – Fast Start-Up Time: 130 μs – Low Dropout 100 mV at Iload =100 mA – Integrated Output Discharge – Stable With 2.2-μF Output Capacitor 1.8-V Compatible Control Input Threshold ESD Performance Tested Per JESD 22 – 3500-V Human-Body Model (A114-B, Class II) – 1000-V Charged-Device Model (C101) Tiny 8-Terminal YZP Package (1.9 mm × 0.9 mm, 0.5-mm Pitch, 0.5-mm Height) and SON-8 (DRG) 3.0 mm × 3.0 mm APPLICATIONS • • • • • Fingerprint Module Protection Portable Consumer Electronics Smart Phone Notebooks Control Access Systems DESCRIPTION The TPS22949 and TPS22949A are devices that provides protection to systems and loads in high-current conditions. The device contains a 500-mΩ current-limited P-channel MOSFET that can operate over an input voltage range of 1.62 V to 4.5 V as well as a low-dropout (LDO) regulator with a fixed output voltage of 1.8 V. The switch is controlled by an on/off input (EN1), which is capable of interfacing directly with low-voltage control signals. When the switch current reaches the maximum limit, the TPS22949/TPS22949A operates in a constant-current mode to prohibit excessive currents from causing damage. If the constant current condition still persists after 12 ms, these devices shut off the switch and pull the fault signal pin (OC) low. The TPS22949/TPS22949A has an auto-restart feature that turns the switch on again after 70 ms if the EN1 pin is still active. The output of the current limiter is internally connected to a RF low-dropout (LDO) regulator that offers good ac performance with very low ground current, good power-supply rejection ratio (PSRR), low noise, fast start-up, and excellent line and load transient response. The output of the regulator is stable with ceramic capacitors. This LDO uses a precision voltage reference and feedback loop to achieve overall accuracy of 2% over all load, line, process, and temperature variations. The TPS22949A integrates additional internal circuitry that increases the current limit of the switch during the power-up sequence. This feature allows the TPS22949A to operate without a storage capacitor at the input of the LDO. The TPS22949 and TPS22949A are available in a space-saving 8-terminal WCSP (YZP) or in a 8-pin SON package (DRG). Both are characterized for operation over the free-air temperature range of –40°C to 85°C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2010, Texas Instruments Incorporated TPS22949 TPS22949A SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 www.ti.com ORDERING INFORMATION (1) PACKAGE (2) TA SON – DRG –40°C to 85°C (1) (2) (3) ORDERABLE PART NUMBER Tape and reel WCSP – YZP Tape and reel TOP-SIDE MARKING (3) TPS22949ADRGR ZUG TPS22949YZPR _ _ _4Y_ TPS22949AYZPR _ _ _4Z_ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). YZP PACKAGE Table 1. YZP PACKAGE TERMINAL ASSIGNMENTS D D C C D EN1 OC B B C VIN VOUTCL A A B GND VOUTLDO A EN2 V+ 2 1 2 1 Laser Marking View 1 2 Bump View DRG PACKAGE (TOP VIEW) EN2 1 GND 2 VIN 3 EN1 4 Exposed Thermal Die Pad on Underside 8 V+ 7 VOUTLDO 6 VOUTCL 5 OC The exposed center pad, if used, must be connected as a secondary GND or left electrically open. TERMINAL FUNCTIONS TERMINAL NO. (1) 2 DESCRIPTION NAME YZP DRG A1 8 V+ A2 1 EN2 LDO control input. Active high. Do not leave floating. B1 7 VOUTLDO LDO output. Output of the RF LDO fixed to 1.8 V (1). Supply voltage B2 2 GND C1 6 VOUTCL Ground C2 3 VIN Supply input. Input to the power switch; bypass this input with a ceramic capacitor to ground. D1 5 OC Over current output flag. Active low, open-drain output that indicates an over-current, supply undervoltage, or over-temperature state. D2 4 EN1 Power switch control input. Active high. Do not leave floating. Switch output. Output of the power switch Output voltages from 0.9 V to 3.6 V in 50-mV increments are available through the use of innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A TPS22949 TPS22949A www.ti.com SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 FUNCTION TABLE STATE OF THE DEVICE EN1 EN2 Current limiter and LDO disabled 0 X Current limiter enabled/LDO disabled 1 0 Current limiter and LDO enabled 1 1 TYPICAL APPLICATIONS VIN VIN VOUTCL VOUTCL EN1 CIN = 4.7 µF CCL = 4.7 µF EN2 V+ V+ VOUTLDO VOUTLDO TPS22949 GND CLDO = 2.2 µF OC OC RPU VIN VIN VOUTCL VOUTCL EN1 CIN = 4.7 µF CCL = 0.1 µF EN2 V+ V+ TPS22949A GND VOUTLDO VOUTLDO CLDO = 2.2 µF OC OC RPU Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A Submit Documentation Feedback 3 TPS22949 TPS22949A SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 www.ti.com BLOCK DIAGRAMS V+, Supply bias (2.5 V to 5.5 V) OC, Over-current flag Current Limiter with Auto-Restart Feature VIN, Current limiter input (1.62 V to 4.5 V) VOUTCL, Current limiter output EN1, Active high VOUTLDO, LDO output (Fixed, 1.8 V max, 100 mA) Low-Noise LDO EN2, Active high GND Figure 1. Simplified Block Diagram VIN C2 (3) UVLO + – EN1 EN2 D2 (4) A2 (1) Control Logic Current Limit C1 (6) VOUTCL UVLO V+ A1 (8) Bandgap + – output discharge B1 (7) Thermal Shutdown D1 (5) VOUTLDO OC GND Figure 2. Detailed Block Diagram 4 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A TPS22949 TPS22949A www.ti.com SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 ABSOLUTE MAXIMUM RATINGS (1) VI Input voltage VIN, EN1, EN2, V+ VOUTCL Current limiter output voltage TJ Operating junction temperature range Tstg Storage temperature range Electrostatic discharge protection (ESD) (1) MIN MAX –0.3 6 V VIN + 0.3 V –40 105 °C –65 150 °C Human-Body Model UNIT 3.5 Charged-Device Model kV 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS DERATING FACTOR ABOVE BOARD PACKAGE RθJC RθJA TA = 25°C TA < 25°C TA = 70°C TA = 85°C High-K (JESD 51-7) YZP 13.79°C/W 101.92°C/W 98.1 mW/°C 784 mW 343 mW 196 mW High-K (JESD 51-5) DRG 56.6°C/W 52.44°C/W 19 mW/°C 1525 mW 667 mW 381 mW RECOMMENDED OPERATING CONDITIONS MIN (1) VIN Input voltage VOUTCL Current limiter output voltage 1.62 V+ Supply voltage 2.6 CIN Input capacitor 1 TA Ambient free-air temperature MAX UNIT 4.5 V VIN V 5.5 V μF –40 85 °C 1.4 5.5 V 0.4 V Control Inputs (EN1, EN2) VIH High-level input voltage VIL Low-level input voltage (1) See the Application Information section ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT IGND Ground pin current EN1 and EN2 = V+ V+ = VOUT + 1.4 V or 2.5, whichever > 5.5 V, VOUTCL ≥ VOUTLDO + 0.5 V IOUT2 = 0 mA 85 110 μA IGNDCL Ground pin current (current limiter only) EN1 = V+ and EN2 = 0 40 75 μA IGND(OFF) OFF-state ground pin current EN1 and EN2 = GND, VOUTCL = Open, VOUTLDO = Open IEN2 Enable pin 2 current, enabled VEN2 = V+ =5.5 V, VIN = 4.5 V 1 μA IEN1 Enable pin 1 current, enabled VEN1 = V+ = 5.5 V, VIN = 4.5 V 1 μA Shutdown threshold (TA) Thermal shutdown Return from shutdown Hysteresis (1) VIN = V+ = 3.3 V 2 VIN = 3.6 V, V+ = 5.5 V 6 TPS22949 122 TPS22949A 135 TPS22949 112 TPS22949A 120 TPS22949 10 TPS22949A 10 μA °C Typical values are at VIN = 3.3 V and TA = 25°C. Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A Submit Documentation Feedback 5 TPS22949 TPS22949A SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 www.ti.com CURRENT LIMITER ELECTRICAL CHARACTERISTICS over operating free-air temperature range, V+ = 3.3 V, EN1 = V+, EN2 = GND (unless otherwise noted) PARAMETER TEST CONDITIONS TA VIN = 4.5 V VIN = 3.3 V rON ON-state resistance IOUT = 20 mA VIN = 2.5 V VIN = 1.8 V YZP PACKAGE MIN 25°C 0.3 0.4 0.35 Full 0.4 Full 0.6 Full VIN = 3.3 V Full ILIM (INRUSH) Power-ON inrush current limit (TPS22949A only) VOUT = 3 V VIN = 3.3 V Full UVLO-CL Undervoltage shutdown VIN increasing 0.4 0.5 0.7 0.6 0.45 150 0.5 1.49 Undervoltage shutdown hysteresis 0.9 0.7 1.0 VIN = 4.5 V VIN = 1.8 V Full 1 0.8 1.1 150 200 1.2 200 100 mA 750 1.59 Ω 1.1 1.39 1.49 30 ISINK = 10 mA 0.8 0.9 750 1.39 0.7 0.8 0.7 1.1 100 UNIT 0.6 1.0 Full VOUT = 3 V MAX 0.8 25°C Current limit TYP 0.7 25°C 25°C MIN 0.5 25°C ILIM OC output logic low voltage MAX Full VIN = 1.62 V DRG PACKAGE TYP 1.59 30 V mV 0.1 0.3 0.1 0.3 0.2 0.4 0.2 0.4 V CURRENT LIMITER SWITCHING CHARACTERISTICS VIN = 3.3 V, TA = 25°C, RL = 500 Ω, CL = 0.1 μF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tON Turn-ON time RL = 500 Ω, CCL = 0.1 μF 95 μs tOFF Turn-OFF time RL = 500 Ω, CCL = 0.1 μF 2 μs tr VOUT rise time RL = 500 Ω, CCL = 0.1 μF 25 μs tf VOUT fall time RL = 500 Ω, CCL = 0.1 μF 10 μs tBLANK Overcurrent blanking time tRSTRT Auto-restart time tINRUSH Power-ON inrush current limit time (TPS22949A only) Short-circuit response time 6 Submit Documentation Feedback RL = 500 Ω, CCL = 0.1 μF 6 12 18 ms 40 80 120 ms 150 VIN = VEN1 = 3.3 V, moderate over-current condition VIN = VEN1 = 3.3 V, hard short 11 5 μs μs Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A TPS22949 TPS22949A www.ti.com SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 LOW-NOISE LDO REGULATOR ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER VOUTLDO ΔVOUTLDO/ΔVIN ΔVOUTLDO/ΔV+ ΔVOUTLDO/ΔIOUT2 VDO VIN PSRR V+ PSRR TEST CONDITIONS Output voltage (1) MAX 1.8 1.84 VIN = VOUTLDO + 0.5 V to 4.5 V, IOUT = 1 mA VIN line transient ΔVIN = 400 mV, tr = tf = 1 μs V+ line regulation VIN = VOUTLDO + 1.4 V or 2.5 V, whichever is > 5.5 V, IOUT = 1 mA V+ line transient ΔVIN = 600 mV, tr = tf = 1 μs Load regulation IOUT2 = 0 to 100 mA (no load to full load) Load transient IOUT2 = 0 to 100 mA, tr = tf = 1 μs Dropout voltage (VDO = VIN – VOUTLDO) VIN = VOUTLDO(NOM) – 0.1 V, V+ – VOUTLDO(NOM) = 1.4 V, IOUT = 100 mA 110 Power-supply rejection ratio Power-supply rejection ratio VOUTCL – VOUTLDO ≥ 0.5 V, V+ = VOUTLDO + 1.4 V, IOUT = 100 mA, VOUTCL – VOUTLDO ≥ 0.5 V, V+ = VOUTLDO + 1.4 V, IOUT = 100 mA, ±2 mV ±0.1 %/V ±5 mV ±0.01 %/V ±35 mV 75 75 f = 1 kHz 80 f = 10 kHz 80 f = 100 kHz 85 f = 1 MHz 85 f = 10 Hz 80 f = 100 Hz 80 f = 1 kHz 75 f = 10 kHz 65 f = 100 kHz 55 f = 1 MHz 35 BW = 10 Hz to 100 kHz 50 tSTR Startup time VOUT = 95%, VOUT(NOM), IOUT = 100 mA, COUT = 2.2 μF Undervoltage lockout V+ rising Hysteresis V+ falling 2.3 V %/V f = 100 Hz Output noise voltage UNIT ±0.1 f = 10 Hz VN (1) TYP VIN line regulation V+ ≥2.5 V, VOUTLDO = VOUTCL + 0.5 V UVLO-V+ MIN 1.76 200 mV dB dB μVrms 130 250 μs 2.45 2.55 V 150 mV LDO output voltage is fixed at 1.8 V. However, output voltages from 0.9 V to 3.6 V in 50 mV increments are available through the use of innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability. Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A Submit Documentation Feedback 7 TPS22949 TPS22949A SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 www.ti.com TYPICAL CHARACTERISTICS 0.9 V+ = 2.5 V V+ = 3.3 V V+ = 4.5 V 0.8 ON-State Resistance, rON (W) ON-State Resistance, rON (W) 0.9 0.7 0.6 0.5 0.8 0.7 0.6 0.5 VIN = 1.8 V VIN = 3.6 V VIN = 4.5 V VIN = 5 V 0.4 0.4 0.3 0.3 1.5 2.5 3.5 4.5 –40 5.5 –10 Input Voltage, VIN (V) 25 55 85 Temperature, TA (°C) Figure 3. ON-State Resistance vs Input Voltage, TA = 25°C Figure 4. ON-State Resistance vs Temperature, V+ = 5.5 V –30 –85 –86 –50 –87 –70 –89 IGND (mA) IGND (mA) –88 –90 –91 –90 –110 –92 –93 –130 –94 –95 2.0 –150 2.5 3.0 3.5 4.0 4.5 5.0 2.2 2.4 Figure 5. Ground Pin Current vs Input Voltage V+ = 5.5 V 8 Submit Documentation Feedback 2.6 2.8 3.0 3.2 3.4 Input Voltage, VIN (V) Input Voltage, VIN (V) Figure 6. Ground Pin Current vs Input Voltage, V+ = 3.3 V Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A TPS22949 TPS22949A www.ti.com SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 TYPICAL CHARACTERISTICS (continued) –80 -38.0 –85 -38.5 -39.0 –90 –100 VIN = 3.3 V VIN = 4.5 V –105 IGND (mA) IGND (mA) -39.5 –95 -40.0 -40.5 -41.0 –110 -41.5 –115 -42.0 -42.5 –120 –40 –10 55 25 1.5 85 2.0 2.5 3.5 4.0 4.5 5.0 Input Voltage, VIN (V) Temperature, TA (°C) Figure 7. Ground Pin Current vs Temperature, V+ = 5.5 V Figure 8. Ground Pin Current vs Input Voltage (Current Limiter Only), V+ = 5.5 V 0 -3.00 -5 -3.05 VIN = 1.8 V VIN = 3.3 V VIN = 4.5 V -10 -3.10 -3.15 IGND(OFF) (nA) -15 IGND (mA) 3.0 -20 -25 -30 -3.20 -3.25 -3.30 -35 -3.35 -40 -3.40 -45 -3.45 -3.50 -50 –40 –10 55 25 85 1.5 2.0 3.0 3.5 4.0 4.5 5.0 Input Voltage, VIN (V) Temperature, TA (°C) Figure 9. Ground Pin Current vs Temperature (Current Limiter Only), V+ = 5.5 V 2.5 Figure 10. OFF-State Ground Current vs Input Voltage, V+ = 5.5 V Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A Submit Documentation Feedback 9 TPS22949 TPS22949A SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) 0 0 -100 -0.5 -1.0 -300 -1.5 IGND(OFF) (mA) -400 -500 -600 -700 -2.0 -2.5 -3.0 -800 -3.5 -900 -4.0 -1000 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -4.5 6.0 –40 –10 Input Voltage, VIN (V) 0.18 1.795 0.16 IOUT = 0 mA IOUT = 1 mA IOUT = 100 mA 1.780 1.775 1.770 1.765 LDO Dropout Voltage, VLDO (V) TA = –40°C TA = –10°C TA = 25°C TA = 55°C TA = 85°C 0.14 0.12 0.10 0.08 0.06 0.04 0.02 Figure 13. Output Voltage vs Temperature 10 Submit Documentation Feedback 00 0. 2 .0 1 -0 .0 -0 4 .0 3 -0 .0 -0 6 .0 5 -0 7 8 Temperature, TA (°C) -0 .0 .0 9 85 -0 55 25 .0 –10 -0 –40 0 0.00 1.760 -0 .1 VOUTLDO (V) Figure 12. OFF-State Ground Current vs Temperature 1.800 1.785 85 Temperature, TA (°C) Figure 11. OFF-State Ground Current vs Input Voltage, VIN = V+ 1.790 55 25 .0 2.0 -0 IGND(OFF) (nA) -200 VIN = 3.6 V VIN = 4.5 V LDO Output Current, IOUTLDO (A) Figure 14. LDO Dropout Voltage vs Output Current Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A TPS22949 TPS22949A www.ti.com SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 TYPICAL CHARACTERISTICS (continued) 1.797 1.82 1.796 1.80 VOUTLDO (V) VOUTLDO (V) 1.795 TA = –40°C TA = –10°C TA = 25°C TA = 55°C TA = 85°C 1.794 1.793 1.78 1.76 TA = –40°C TA = –10°C TA = 25°C TA = 55°C TA = 85°C 1.74 1.792 1.72 1.791 2.0 2.0 2.5 3.0 3.5 4.0 4.5 2.5 5.0 3.0 3.5 4.0 Input Voltage, VIN (V) 4.5 5.0 Input Voltage, VIN (V) Figure 15. Input Voltage, VIN, Line Regulation, IOUT = 0 mA Figure 16. Input Voltage, VIN, Line Regulation, IOUT = 100 mA 1.779 1.797 1.796 1.778 VOUTLDO (V) VOUTLDO (V) 1.795 TA = –40°C TA = –10°C TA = 25°C TA = 55°C TA = 85°C 1.794 1.793 TA = –40°C TA = –10°C TA = 25°C TA = 55°C TA = 85°C 1.776 1.775 1.792 1.791 3.0 1.777 1.774 3.5 4.0 4.5 5.0 5.5 6.0 3.0 3.5 Input Voltage, V+ (V) Figure 17. Input Voltage, V+, Line Regulation, IOUT = 0 mA 4.0 4.5 5.0 5.5 6.0 Input Voltage, V+ (V) Figure 18. Input Voltage, V+, Line Regulation, IOUT = 100 mA Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A Submit Documentation Feedback 11 TPS22949 TPS22949A SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) 1.797 1.800 1.796 1.795 1.795 VOUTLDO (V) 1.785 TA = –40°C TA = –10°C TA = 25°C TA = 55°C TA = 85°C 1.780 1.775 1.794 TA = –40°C TA = –10°C TA = 25°C TA = 55°C TA = 85°C 1.793 1.792 1.791 IOUTLDO (A) LDO Output Response Figure 20. Load Regulation Under Light Loads, IOUT = 10 mA Load Transient Signal,LDO Output Response 50 mV/DIV Load Transient Signal,LDO Output Response 50 mV/DIV Load Transient Signal Load Transient Signal LDO Output Response 100 µs/DIV 100 µs/DIV Figure 21. Load Transient Submit Documentation Feedback 00 IOUTLDO (A) Figure 19. Load Regulation, IOUT = 100 mA 12 0. 00 0. -0 .1 0 -0 .0 9 -0 .0 8 -0 .0 7 -0 .0 6 -0 .0 5 -0 .0 4 -0 .0 3 -0 .0 2 -0 .0 1 1.790 0 -0 .0 9 -0 .0 8 -0 .0 7 -0 .0 6 -0 .0 5 -0 .0 4 -0 .0 3 -0 .0 2 -0 .0 1 1.770 -0 .1 VOUTLDO (V) 1.790 Figure 22. VIN Load Transient Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A TPS22949 TPS22949A www.ti.com SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 TYPICAL CHARACTERISTICS (continued) VOUTLDO VIN 1 mV/div VIN = 2.1 V to 2.5 V VOUT = 1.8 V V+ = 3.2 V IOUTLDO = 100 mA 200 mV/div Output Spectral Noise Density ( Vrms/RTHz) 1.41E-6 1.21E-6 1.01E-6 810E-9 610E-9 410E-9 210E-9 10E-9 100 1000 10000 100000 Frequency (Hz) 100 µs/DIV Figure 23. V+ Load Transient Figure 24. Output Spectral Noise Density vs Frequency 0 -10 IOUTLDO = 0 mA IOUTLDO = 50 mA IOUTLDO = 100 mA -30 IOUTLDO = 1 mA IOUTLDO = 100 mA -10 -20 -50 -40 PSRR PSRR (dB) -30 -70 -50 -60 -70 -90 -80 -110 10 100 1000 10000 100000 1000000 -90 -100 10 Frequency (Hz) Figure 25. PSRR vs Frequency 0 100 1000 10000 100000 Frequency (Hz) 1000000 Figure 26. V+ PSRR vs Frequency Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A Submit Documentation Feedback 13 TPS22949 TPS22949A SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) 180 80 160 70 Tfall TON 60 120 trise /tfall (µs) tON /tOFF (µs) 140 100 CL = 0.1 µF, RL = 330 Ω ILOAD = 10 mA VIN = V+ = 3.3 V 80 60 CL = 0.1 µF RL = 330 Ω ILOAD = 10 mA 50 40 30 20 40 Trise TOFF 20 10 -50 -25 0 25 50 Temperature (°C) 75 -50 100 Figure 27. tON/tOFF vs Temperature 0 25 50 Temperature (°C) 75 100 Figure 28. trise/tfall vs Temperature 5.5 2.0 5.0 1.8 Vin = 1.8VVin = 2.5VVin = 3.0VVin = 3.3VVin = 4.5VVin = 5.0V- 4.0 3.5 3.0 1.6 1.4 1.2 LDO_out (V) 4.5 Vout (V) -25 2.5 2.0 1.5 1.0 V+ = 2.5VV+ = 3VV+ = 3.3VV + = 3.6VV+ = 4.5VV+ = 5VV + = 5.5V- 0.8 0.6 1.0 0.4 0.5 0.2 0.0 0.0 -0.5 0.0 0.5 1.0 1.5 2.0 Input Voltage, EN1 (V) -0.2 0.0 0.5 1.0 1.5 2.0 Input Voltage, EN2 (V) Figure 29. EN1 (Current Limiter) Input Thresholds, V+ = 5.5 V 14 A. VDRV signal forces the device to go into over-current mode B. VDRV signal forces the device to go into over-current mode Submit Documentation Feedback Figure 30. EN2 (LDO) Input Thresholds, VIN = 3.3 V Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A TPS22949 TPS22949A www.ti.com SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 TYPICAL CHARACTERISTICS (continued) V DRV(*) 2V/DIV V DRV(A) 2 V/DIV V OUTCL V OUTCL 2V/DIV 2 V/DIV I OUTCL 100 mA/DIV I OUTCL 100mA/DIV V OC 2 V/DIV V OC 2V/DIV 2 ms/DIV 20 ms/DIV Figure 31. tBLANK Response Figure 32. tRESTART Response COUTCL = 0.1uF ROUTCL = 500-W VIN = 3.3 V IOUTCL 1 mA/DIV IOUTCL 1mA/DIV COUTCL = 0.1uF ROUTCL = 500-! VIN = 3.3-V VEN1 1V/DIV VEN1 1V/DIV 50uS/DIV 50 us/DIV Figure 33. Current Limiter tON Response VIN 2V/DIV Figure 34. Current Limiter tOFF Response VIN 2V/DIV CIN = 10uF COUTCL = 1uF IOUTCL 400mA/DIV IOUTLDO 400mA/DIV VOUTLDO 2V/DIV VOUTCL 2V/DIV 10uS/DIV 10uS/DIV Figure 35. Short-Circuit Response Time (VOUTCL Shorted to GND) Figure 36. Short-Circuit Response Time (VOUTLDO Shorted to GND) Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A Submit Documentation Feedback 15 TPS22949 TPS22949A SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) VIN/VEN2 1V/DIV VIN/VEN1 1V/DIV IOUTCL 100mA/DIV CIN = 10uF COUTCL = 1uF IOUTLDO 100mA/DIV 20uS/DIV 20uS/DIV Figure 37. Short-Circuit Response Time (Switch Power-Up to Hard Short) (TPS22949) CIN = 10uF COUTCL = 1uF Figure 38. Short-Circuit Response Time (LDO Power-Up to Hard Short) (TPS22949) VIN 1V/DIV V IN 1V/DIV IOUTCL 200mA/DIV IOUTLDO 200mA/DIV CIN = 10uF COUTCL = 0.1uF CIN = 10uF COUTCL = 0.1uF 20uS/DIV 20uS/DIV Figure 39. Short-Circuit Response Time (Switch Power-Up to Hard Short) (TPS22949A) 16 Submit Documentation Feedback Figure 40. Short-Circuit Response Time (LDO Power-Up to Hard Short) (TPS22949A) Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A TPS22949 TPS22949A www.ti.com SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 TYPICAL CHARACTERISTICS (continued) VIN 2V/DIV VIN 2V/DIV CIN = 10uF COUTCL = 1uF VEN1 2V/DIV IOUTCL 100mA/DIV VEN2 2V/DIV IOUTLDO 100mA/DIV VOUTCL (Shorted to Ground) VOUTLDO (Shorted to Ground) 20uS/DIV 20uS/DIV Figure 41. Current Limit Response Time (Current Limiter) Figure 42. Current Limit Response Time (LDO) Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A Submit Documentation Feedback 17 TPS22949 TPS22949A SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 www.ti.com APPLICATION INFORMATION Undervoltage Lockout (UVLO) The undervoltage lockout turns off the switch if the input voltage drops below the undervoltage lockout threshold. With the ON pin active, the input voltage rising above the undervoltage lockout threshold causes a controlled turn-on of the switch, which limits current over-shoots. The TPS22949/TPS22949A also has a UVLO on the V+ bias voltage and keep the output of the LDO shut off until the internal circuitry is operating properly. Fault Reporting When an overcurrent, input undervoltage, or overtemperature condition is detected, OC is set active low to signal the fault mode. OC is an open-drain MOSFET and requires a pullup resistor between VIN and OC. During shutdown, the pulldown on OC is disabled, reducing current draw from the supply. Current Limiting When the switch current reaches the maximum limit, the TPS22949/TPS22949A operates in a constant-current mode to prohibit excessive currents from causing damage. TPS22949/TPS22949A has a minimum current limit of 100 mA. Input Voltage The input voltage (VIN) of the current limiter is set from 1.62 V to 4.5 V, however if both the current limiter and the LDO are enabled, the user must be careful to keep the input voltage (VIN) greater than 1.8 V + (voltage drop through the switch) + (voltage drop through the LDO); otherwise, the LDO does not have a high enough internal input signal to operate properly. A current limiter input voltage ramp time less than the blanking time (~10 ms typical) is recommended. If the ramp time extends beyond the blanking period, then the current limiter goes into recycle, and the system may not start or operate properly. Input/Output Capacitors Although an input capacitor is not required for stability of on the input pin (VIN), it is good analog design practice to connect a 0.1-μF to 1-μF low equivalent series resistance (ESR) capacitor across the IN pin input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher value capacitor may be necessary if large, fast rise time load transients are anticipated, or if the device is located close to the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure stability. The V+ bias pin does not require an input capacitor because it does not source high currents. However, if source impedance is not sufficiently low, a small 0.1-μF bypass capacitor is recommended. A 0.1-μF capacitor CCL, should be placed between VOUTCL and GND. This capacitor prevents parasitic board inductances from forcing VOUTCL below GND when the switch turns off. For the TPS22949, the total output capacitance must be kept below a maximum value, CCL(max), to prevent the part from registering an over-current condition and turning off the switch. The maximum output capacitance can be determined from the following formula: CCL = ILIM(MAX) × tBLANK(MIN) ÷ VIN Due to the integral body diode in the PMOS switch, a CIN greater than CCL is highly recommended. A CCL greater than CIN can cause VOUTCL to exceed VIN when the system supply is removed. This could result in current flow through the body diode from VOUTCL to VIN. On TPS22949, a storage capacitor (CCL) at the output of the current limiter is recommended to provide enough current to the LDO during the start-up sequence. The storage capacitor is needed to reduce the amount of inrush current supplied through the current-limited load switch to the LDO during the power-up sequence (see Figure 44). If the CCL capacitor is too small, the inrush current needed to start the LDO and charge CLDO could be interpreted by the current limiter as an over-current and, therefore, trigger the current-limiting feature of the switch. The switch would then try to limit the current to the 100-mA limit, and the user would see an undesired drop on the supply line (see Figure 45). 18 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A TPS22949 TPS22949A www.ti.com SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 On TPS22949A, the storage capacitor (CCL) is not required. TPS22949A integrates an additional internal circuitry that increases the current limit of the switch to approximately 750 mA (i.e ILIM(INRUSH)) for about 250 μs (i.e tINRUSH), initiated when the internal circuitry of the LDO is operating properly (i.e., when the UVLO of the LDO bias (V+) is disabled (V+ > 2.6 V). Because the current limit is increased during the power-up sequence, a potential inrush current through the LDO is not interpreted by the current limiter as an over-current. The current needed by the LDO is then be supplied by the input capacitor (CIN) of the current limiter (see Figure 45). The TPS22949 LDO (VOUTLDO) is designed to be stable with standard ceramic capacitors with values of 2.2 μF or larger at the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR should be less than 250 mΩ. Figure 43, Figure 44, and Figure 45 illustrate the behavior of the TPS22949 and TPS22949A with a 100-mA sinking load and different capacitor values for a typical application where both enables are tied to the same input voltage (see Figure 43). TPS22949 TPS22949A VIN VIN VOUTCL VOUTCL EN1 CIN CCL EN2 V+ V+ VOUTLDO (1.8 V, 100 mA) VOUTLDO CLDO GND OC OC RPU Figure 43. TPS22949/TPS22949A Typical Application With Both Enable Pins Tied to the Input Voltage 3.5 3.0 VIN VOUTCL VLDO Voltage(V) 2.5 2.0 1.5 VIN = V+ = VEN1 = VEN2 = 3.3 V CIN = 4.7 mF, CCL = 2.2 mF 1.0 CLDO = 2.2 mF 0.5 0.0 0 0.0005 0.001 0.0015 0.002 0.0025 Time (s) Figure 44. TPS22949 Power-Up Sequence Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A Submit Documentation Feedback 19 TPS22949 TPS22949A SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010 www.ti.com 3.5 3.0 VIN VOUTCL VLDO Voltage (V) 2.5 2.0 1.5 VIN = V+ = VEN1 = VEN2 = 3.3 V CIN = 4.7 mF, CCL = 0 mF CLDO = 2.2 mF 1.0 0.5 0.0 0 0.0005 0.001 0.0015 0.002 0.0025 Time (s) Figure 45. TPS22949 Power-Up Sequence 3.5 3.0 VIN VOUTCL VLDO Voltage (V) 2.5 2.0 1.5 VIN = V+ = VEN1 = VEN2 = 3.3 V CIN = 4.7 mF, CCL = 0 mF 1.0 CLDO = 2.2 mF 0.5 0.0 -0.5 0 0.0005 0.001 0.0015 Time (s) 0.002 0.0025 Figure 46. TPS22949A Power-Up Sequence 20 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TPS22949 TPS22949A PACKAGE OPTION ADDENDUM www.ti.com 5-Jan-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS22949ADRGR ACTIVE SON DRG 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS22949AYZPR ACTIVE DSBGA YZP 8 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM TPS22949YZPR ACTIVE DSBGA YZP 8 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS22949ADRGR Package Package Pins Type Drawing SON DRG 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 3.3 B0 (mm) K0 (mm) P1 (mm) 3.3 1.1 8.0 W Pin1 (mm) Quadrant 12.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS22949ADRGR SON DRG 8 3000 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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