MICRONAS UAC3552A

PRELIMINARY DATA SHEET
MICRONAS
Edition Nov. 9, 1999
6251-487-1PD
UAC 3552A
Universal Serial Bus
DAC
MICRONAS
UAC 3552A
PRELIMINARY DATA SHEET
Contents
Page
Section
Title
4
5
1.
1.1.
Introduction
Features
6
6
6
6
6
6
6
6
6
6
7
8
8
8
9
9
9
10
10
10
10
10
10
10
10
10
10
11
11
11
11
12
12
13
13
13
13
13
2.
2.1.
2.1.1.
2.1.1.1.
2.1.1.2.
2.1.1.3.
2.1.2.
2.1.3.
2.1.4.
2.1.5.
2.1.5.1.
2.1.5.2.
2.1.5.3.
2.1.5.4.
2.1.5.5.
2.1.5.6.
2.1.6.
2.1.7.
2.1.7.1.
2.1.7.2.
2.1.7.3.
2.1.8.
2.2.
2.2.1.
2.2.1.1.
2.2.1.2.
2.2.1.3.
2.2.1.4.
2.2.2.
2.2.2.1.
2.2.2.2.
2.2.2.3.
2.2.2.4.
2.2.2.5.
2.2.2.6.
2.2.2.7.
2.2.3.
2.2.3.1.
Functional Description
Hardware
USB Interface
Transceiver
Interface Engine
Microcontroller
Audio Control Interface
Audio Streaming Interface
Audio Processing Unit
Analog Back-end
DAC
Analog Low-pass
Postfilter Op Amps
Input Mixer
Analog Volume Control
Line-out/Headphone Amplifier
General Purpose I/O
Special I/O
SOF (Start of Frame)
AUXEN
SUSPEND
Clock System
Software
USB Microcontroller Software
Chapter 9 Functions
Device Descriptor
String Descriptor
HID Report Descriptor
Audio Processing Software
Sample Rate Converter
Automatic Gain Control
Bass Control
Treble Control
Bass Boost Control
Parametric Equalizer
Volume and Balance Control
Mute Control
Oversampling
2
Micronas
PRELIMINARY DATA SHEET
UAC 3552A
Contents, continued
Page
Section
Title
14
14
14
16
16
16
17
17
18
19
19
20
22
3.
3.1.
3.2.
3.3.
3.3.1.
3.3.2.
3.3.3.
3.4.
3.5.
3.6.
3.6.1.
3.6.2.
3.6.3.
Specifications
Outline Dimensions
Pin Connections and Short Descriptions
Pin Descriptions
Power Supply Pins
Analog Audio Pins
Other Pins
Pin Configuration
Pin Circuits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Characteristics
26
26
27
4.
4.1.
4.2.
Applications
Recommended Low-Pass Filters for Analog Outputs
Typical Application
28
5.
Data Sheet History
Micronas
3
UAC 3552A
PRELIMINARY DATA SHEET
Universal Serial Bus DAC
1. Introduction
The UAC 3552A is the first member of Micronas’ USB
audio controller family of ICs targeting a wide variety of
audio applications on the USB. The UAC 3552A is a
single-chip, high-precision digital-to-analog audio converter. It includes a high-quality audio sample rate converter and is able to support a wide range of sample
rates, as well as different audio formats.
The IC contains a complete USB transceiver that
allows direct connection to the USB. An on-chip
EEPROM allows storing of manufacturer-specific data
or product identification. The EEPROM can be programmed directly via the USB.
The audio DAC uses Micronas’ proprietary multibit
sigma-delta technique. It features very low sensitivity
to clock jitter, high linearity, and a superior S/N ratio.
The UAC 3552A provides an on-chip headphone/
speaker amplifier. Moreover, mixing additional analog
audio sources to the D/A-converted signal is supported.
The IC is designed for all kinds of USB audio applications, such as USB active speakers, USB headphones,
and USB interfaces to home stereo equipment, etc.
Any existing analog speaker set can easily be
upgraded to USB by just including the UAC 3552A
according to the application circuit on page 27. No
software development is required, because all drivers
are already part of the operating system which supports USB (e. g. Windows™ 98).
Baseband audio processing is handled by an internal,
powerful DSP. Apart from basic audio features, like
tone and volume control, there is enough processing
power left to realize customer-specific applications.
HID IO
Analog Input
External Loop-through Filter
EEPROM
D+
D−
USB
Interface
DSP
ROM
ROM
DAC
Input
Select
and
Mixing
Volume
and
Headphone
Amplifier
OUTL
OUTR
+5 V GND
Fig. 1–1: Block diagram of the UAC 3552A
4
Micronas
UAC 3552A
PRELIMINARY DATA SHEET
1.1. Features
– single-chip, USB specification 1.0/1.1 compliant,
stereo audio D/A converter
– 12-Mbit/s USB transceiver
– adaptive isochronous endpoint for USB Audio
– USB-programmable vendor IDs (1024-bit EEPROM
on chip)
– four general purpose input pins and four output pins
(human interface pins)
– customizable I/O functionality by download-software
– supports 16-bit mono/stereo and 24-bit stereo audio
data
– adaptive sample rate converter for 5 to 50 kHz input
sampling rate
– audio baseband control: bass, treble, volume, and
balance, additional analog volume, mute
– bass boost
– automatic gain control (AGC)
– “PerfectSpeaker” digital speaker equalizer
– THD better than 0.01 %, SNR of 96 dB
– integrated low-power stereo headphone amplifier
– on-chip op amps for external analog filter
– analog stereo input (AUX) with source selection and
mixing
– single 5-V power supply
Active Stereo Speakers
USB
UAC
Headphones
Stereo Equipment
Fig. 1–2: System application diagram
Micronas
5
UAC 3552A
2. Functional Description
2.1. Hardware
A detailed block diagram of the UAC 3552A is depicted
in Fig. 2–1. The functions of the blocks are explained
in the following sections.
2.1.1. USB Interface
2.1.1.1. Transceiver
The differential input receiver is used to accept the
USB data signal according to the full-speed (12 MB/s)
USB driver characteristics (USB SPEC 1.1 - 7.1.4).
2.1.1.2. Interface Engine
The interface engine comprises two major sections:
the transceiver logic and the receiver logic. The transceiver logic transmits data packets built in memory by
the microcontroller. These packets are converted from
a serial to a parallel data stream. This includes NRZI
encoding, bit stuffing, CRC-computation, and addition
of SYNC field and EOP. The receiver logic will receive
USB data and stores these packets in its memory for
processing by the microcontroller. Serial USB data is
converted to a byte-wide parallel data stream and
stored in system memory. In addition to USB basic
data decoding, the Rx logic performs a PID check and
protocol layer checks.
PRELIMINARY DATA SHEET
The ROM contains the USB drivers for the microcontroller as well as the complete descriptor table including the report descriptor for the HID-class. Some parts
of the descriptor which are subjected to be changed by
the customer, however, reside in the EEPROM.
The EEPROM is built to keep static customer-related
data that will customize the UAC 3552A-based USB
device during production.
The 128×8 bit EEPROM contains the customer specific information of the USB device descriptor, like vendor ID, product ID, as well as strings for manufacturer,
product and serial number. Apart from this USBrelated information, the EEPROM holds customer-specific parameters for the PerfectSpeaker equalizer.
The UAC 3552A is shipped with a preprogrammed
EEPROM that allows normal USB functionality even if
no reprogramming is performed on the customer’s
side.
The EEPROM can be programmed via USB by means
of UAC 3552A application tools.
2.1.2. Audio Control Interface
The audio control interface links the microcontroller to
the DSP and is used to initialize the DSP and to transmit audio-related USB control data, like volume setting,
tone control etc.
2.1.3. Audio Streaming Interface
2.1.1.3. Microcontroller
The microcontroller manages buffers for all enabled
endpoints and interacts with the interface engine. The
buffers are built and decoded in memory. This way, the
microcontroller realizes the USB protocol handling, like
USB reset, enumeration, and all chapter 9 processing,
error handling, as well as class-specific endpoint handling, like audio class and HID class. The audio-class
processing consists of interpreting the USB audio
commands and accordingly controlling the DSP-audio
function through a dedicated audio-control-interface to
the DSP. HID class processing means polling keys providing the corresponding key-codes to the host-computer’s requests. These keys are connected to the
GPIO-pins. The RAM can be accessed by the microcontroller and by the interface-engine’s DMA-controller. All endpoint communication is realized with intelligent buffer management built up in the RAM.
A part of the RAM is reserved for download software.
This allows adding extra functionality to the GPIO pins,
like I2C-handling or any other control of external components via USB. Downloading is handled by an extra
driver which allows direct RAM/ROM access via USB.
6
The audio streaming interface directly connects the
serial interface engine to the DSP in order to transmit
the digital audio data. The interface collects and buffers the burst audio data for further processing by the
audio processing unit.
2.1.4. Audio Processing Unit
The audio processing unit is a powerful DSP core
which allows high-quality sample conversion, baseband audio processing, and interpolation filtering used
for oversampling DAC, as well as customized algorithms. For more details on the software see Section
2.2.2. “Audio Processing Software” on page 11.
2.1.5. Analog Back-end
The analog back-end comprises the audio DAC, analog filters, input mixer, op amps for optimal external
postfiltering, analog volume and mute, and the output
amplifier.
Micronas
UAC 3552A
PRELIMINARY DATA SHEET
2.1.5.1. DAC
The DAC uses oversampling technique with 3rd-order
multibit noise-shaping. This technique results in
extremely low quantization noise in the audio band.
DMINUS
24
DPLUS
25
Transceiver
26
VREG
14
15
16
17
19
20
21
22
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
29
30
31
32
33
TEST
RESQ
SUSPEND
SOF
AUXEN
27
VDD
28
VSS
Interface
Engine
µC
RAM
ROM
XTI
8
XTO
9
Oscillator
GP I/O
EEPROM
Control
I/O
Audio Streaming
Interface
Audio Control
Interface
Audio Processing Unit
DAC
Digital Supply
AUXL
36
AUXR
37
Analog Input
Input Mixer
Volume
Analog
Supply
Headphone
Amplifier
4
OUTL
6
AVDD0
7
AVDD1
3
AVSS0
2
AVSS1
44
VREF
1
AGNDC
5
OUTR
Fig. 2–1: Detailed block diagram of the UAC 3552A
Micronas
7
UAC 3552A
PRELIMINARY DATA SHEET
2.1.5.2. Analog Low-pass
Table 2–1: AUXEN pin
The output of the DAC is filterted by an analog lowpass filter with a cut-off frequency of approximately
1.4 MHz. This filter removes the high-frequency components of the noise-shaping signal.
AUXEN
0
AUX not selected
1
AUX selected
2.1.5.3. Postfilter Op Amps
This block contains the active components for the
optional analog postfilters. It is recommended to use a
second-order filter (see Section 4. “Applications” on
page 26) in order to attenuate the out-of-band noise
caused by the noise shaper The op amps and all I/Opins for this block are shown in Fig. 2–2.
This allows to use a jack that switches the AUXEN to
low when an analog source is plugged in, according to
the application note Section 4. “Applications” on page
26. The DAC-signal is permanently connected to the
mixer because the DAC is extremely quiet if no USB
audio is applied.
The AUXEN pin also keeps the UAC 3552A from
entering the low-power mode when an analog source
is connected. Please note that in this mode, the
UAC 3552A is not USB-compliant. If the USB is not
connected the GPIO pins work as an USB-independent volume control (see Table 2–2). BassBoost is not
supported in this mode.
2.1.5.4. Input Mixer
This block is used to mix the auxiliary inputs and the
signals coming from the DAC. This allows to use an
UAC 3552A-based USB speaker in a non-USB environment, like WIN 3.11 or other operating systems. On
the other hand, it allows to connect additional analog
sources, like CD-player or Walkman even while the
speaker is connected to the USB. The input mixer is
hardware-controlled by the AUXEN pin.
For external components,
see section “Applications”
FOUTL
FOPL
FINL
Analog Vol. L
UAC 3552A (Back-end)
OUTL
−
−
from switch matrix
−
OUTR
−
Analog Vol. R
AVSS
VREF
AGNDC
FOUTR
FOPR
FINR
For external components,
see section “Applications”
Fig. 2–2: Postfilter op amps and analog volume
8
Micronas
UAC 3552A
PRELIMINARY DATA SHEET
2.1.5.5. Analog Volume Control
2.1.6. General Purpose I/O
The analog volume control covers a range from 0 dB to
−75 dB plus an additional mute position.
The GPIO pins are used to connect keys which are
related to the USB HID class or for vendor-specific
control functions and LEDs in order to indicate on/off
states for example. The standard configuration defines
the GPIOs as four input pins (GPIO0...GPIO3) and
four output pins (GPIO4...GPIO7). The function of the
input pins is shown in Table 2–2.
The analog step size is split into a 3-dB and a 1.5-dB
range:
−75 dB...−54 dB:
−54 dB...0 dB:
3 dB step size
1.5 dB step size
The overall volume system, however, consists not only
of the analog volume. An additional digital volume control allows a step size of 0.5 dB over the complete
range. See Section 2.2.2.7. “Volume and Balance Control” on page 13.
Please note that analog input signals (AUXL, AUXR)
do not have the additional digital volume control.
2.1.5.6. Line-out/Headphone Amplifier
The line-out/headphone amplifier output is provided at
the OUTL and OUTR pins connected either to stereo
headphones or to the power amplifier within an USB
speaker. The stereo headphones require external
47-Ω serial resistors in both channels. See Section 4.
“Applications” on page 26.
Table 2–2: Standard Key Configuration
Pin
Function
Key
Code
Usage
ID
GPIO0
Volume Up
1
E9
GPIO1
Volume Down
2
EA
GPIO2
MuteToggle
4
E2
GPIO3
BassBoost Toggle
8
E5
The keys are polled by the microcontroller and the corresponding key codes are transmitted to the host on
request. The relation between key code and usage ID
(see Universal Bus HID Usage Tables, Version 1.0,
Chapter 14 – Consumer Page) is defined in the HID
report descriptor (see Section 2.2.1.4. “HID Report
Descriptor” on page 11) which is transmitted to the
host along with the configuration descriptor during the
bus enumeration.
When the device is not connected to USB, the functionality of the volume-control and mute pins are preserved. In this case, however, the parameters are
directly transferred to the DSP-core. This allows using
the device in stand-alone mode providing volume and
mute control for analog sources.
The output pins are not predefined and therefore not
related to any USB functions. They can be set or reset
by vendor-specific software.
The standard configuration can be changed also by
vendor-specific USB software, but in this case, Table
2–2 is no longer valid.
Micronas
9
UAC 3552A
PRELIMINARY DATA SHEET
2.1.7. Special I/O
2.2. Software
2.1.7.1. SOF (Start of Frame)
The functionality of the UAC 3552A is mainly defined
by software. The internal µ-controller handles the USB
requests whereas the Audio Processing Unit processes the sound features.
The SOF-pin provides a 1-ms signal which is synchronous to the USB 1-ms frame rate. It can be used for
test purpose or as an USB-synchronous reference for
vendor-specific external circuitry.
2.2.1. USB Microcontroller Software
2.1.7.2. AUXEN
2.2.1.1. Chapter 9 Functions
This is a digital input that has to be used if an analog
signal is connected to the AUX R/L pins. It triggers the
microcontroller to switch the input mixer to the analog
input (the DAC signal always remains active!) and it
keeps the device from entering the low-power mode
which can be requested by the host PC or by disconnecting the device from the USB.
The chapter 9 of the USB Spec 1.1 defines the USB
device framework which is the middle layer of the USB
protocol hierarchy (see USB Spec 1.1 page 175). It
handles routing data between the bus interface and
various endpoints. The endpoint is a source or sink for
data within the device.
2.2.1.2. Device Descriptor
2.1.7.3. SUSPEND
The SUSPEND pin indicates the low-power mode. It
can be used to power down external circuitry, like
power amplifiers in an USB speaker.
Unlike the configuration descriptor, which is located in
ROM, the device descriptor is more flexible. The manufacturer-related data are stored in the on-chip
EEPROM, and can be adapted individually. In detail
these data are
Table 2–3: SUSPEND pin
– vendor ID
– product ID
SUSPEND
– device release number
low
normal power
– manufacturer string
high
low power
– product string
– serial number string
2.1.8. Clock System
The UAC 3552A requires a 12-MHz clock source,
which is realized as an on-chip oscillator with external
crystal. Also an external oscillator can be used. In this
case, the clock has to be connected to XTI. The
12 MHz is the input clock for a PLL circuit which generates all clocks needed within the IC.
A comfortable programming tool allows this data to be
defined and writes it into the corresponding EEPROM
location.
The UAC 3552A is shipped with the Micronas device
descriptor and allows USB functionality without any
EEPROM reprogramming.
2.2.1.3. String Descriptor
The string descriptor is located in the EEPROM. The
UAC 3552A holds three strings. The programming tool
handles the programming of strings and will take care
of string length control also.
The UAC 3552A is shipped with the Micronas string
descriptor and allows USB functionality without any
EEPROM reprogramming.
10
Micronas
UAC 3552A
PRELIMINARY DATA SHEET
2.2.1.4. HID Report Descriptor
2.2.2.1. Sample Rate Converter
The HID report descriptor defines the functionality of
the GPIO Pins. The basic information here are the
usage IDs for the key inputs. These IDs are stored in
the EEPROM and can therefore be modified if the
default configuration does not fit the application. The
UAC 3552A, however, only supports the default functions: volume up/down, mute on/off and BassBoost on/
off. This means, that all nonstandard usage IDs will be
transmitted to the host on request and can be used
with vendor specific software, but only the default IDs
will work together with the operating system.
The purpose of the sample rate converter is first to
transform the block transferred audio data into a continuous data stream and second to convert all incoming sample rates to a fixed 50-kHz sample rate. This
technique eliminates input data jitter. Furthermore, all
audio algorithms and the DAC run on a single sample
rate and no parameter switching is required on change
of audio sampling rate. Furthermore, all audio clocks,
such as sampling clock, noise-shaping clock, and
DAC-clock can be derived from a single free-running
12-MHz oscillator. This mechanism allows continuous
input sampling rates from 5 kHz up to 50 kHz.
2.2.2. Audio Processing Software
2.2.2.2. Automatic Gain Control
All audio processing is realized by DSP-software,
apart from volume control which is located in the analog back-end. The audio building blocks split into USBindependent features, like sample rate conversion and
oversampling filters and blocks which belong to the so
called USB feature unit, defined in the USB Device
Class Definition for Audio Devices. The feature unit
provides basic manipulation of the incoming logical
channels. The UAC 3552A supports two logical channels (i.e. left & right). Multichannel or surround systems, however, can also be realized using more than
one UAC 3552A, because phase or delay distortion is
eliminated by locking the audio processing to the USB
frame rate. An overview of the architecture is given in
Fig. 2–3.
The Automatic Gain Control (AGC) is one of the building blocks of the feature unit (USB Device Class Definition for Audio Devices 1.0, page 39).
Different sound sources fairly often do not have the
same volume level. The Automatic Gain Control solves
this problem by equalizing the volume levels within a
defined range. Below a theshold level the signals are
not affected. The level-adjustment is performed with
time constants in order to avoid short-time adjustments
due to signal peaks.
Feature Unit
Sample Rate
Converter
AGC
Bass/Treble
Bass Boost
Equalizer
Volume/
Balance
OverSampling
Fig. 2–3: Audio processing
Micronas
11
UAC 3552A
PRELIMINARY DATA SHEET
2.2.2.3. Bass Control
2.2.2.4. Treble Control
The bass control provides gain or attenuation to frequency components below a corner frequency of
120 Hz. The characteristic is shown in Fig. 2–4.
The treble control provides gain or attenuation to frequency components above a corner frequency of
6 kHz. The characteristic is shown in Fig. 2–5.
dB
dB
15
15
10
10
5
5
0
0
-5
-5
-10
-10
-15
-15
10.
50.
100.
500.
1000.
5000.
10000.
10.
50.
100.
500.
1000.
5000.
Hz
10000.
Hz
Fig. 2–4: Bass control
Fig. 2–5: Treble control
The bass control works identically on both channels.
The treble control works identically on both channels.
Table 2–4: Bass Control Characteristics
Table 2–5: Treble Control Characteristics
Min
Max
Step
Min
Max
Step
−12 dB
+12 dB
0.5 dB
−12 dB
+12 dB
0.5 dB
12
Micronas
UAC 3552A
PRELIMINARY DATA SHEET
2.2.2.5. Bass Boost Control
2.2.2.7. Volume and Balance Control
The bass boost algorithm provides an additional 12-dB
gain for the low-frequency components. The characteristic is shown in Fig. 2–6.
The volume and balance control operate separately on
the left and right channel.
Table 2–7: Volume and Balance Control
dB
14
12
Min
Max
Step
−75 dB
0 dB
0.5 dB
10
8
6
4
2
0
10.
20.
50.
100.
200.
500.
1000.
Hz
The volume control is realized in the analog back-end.
This preserves high audio quality (SNR) at low volume
settings because signal and noise are attenuated in
the same way, which is not the case for pure digital volume control. The UAC 3552A uses digital volume control only for the fine tuning of the 0.5 dB step size. The
volume setting is smoothed by an internal ramping
algorithm in order to avoid audible clicks during volume
change.
Fig. 2–6: Bass boost
The splitting between analog and digital volume is handled by the UAC 3552A automatically.
The bass boost works on both channels and can be
switched on and off under USB control.
2.2.3. Mute Control
2.2.2.6. Parametric Equalizer
The parametric equalizer is a non-USB audio feature.
It allows the compensation of unwanted frequency
responses of a speaker. Alternatively, frequency
responses can be set to suit individual tastes. The
equalizer consists of 5 individually adjustable bands.
The control parameters and the parameter range for
each band is shown in Table 2–6.
Table 2–6: Equalizer Parameters
Parameter
Min
Max
center frequency
50 Hz
15 kHz
The mute control is part of the volume system in the
UAC 3552A. It functions simultaneously on both channels and can be switched on and off under USB control. As with the volume control, clicks are avoided by a
ramping algorithm.
2.2.3.1. Oversampling
The oversampling filter increases the audio sampling
rate by a factor of 4. The final upsampling to the noiseshaping rate is handled by a sample and hold circuit.
The pass-band characteristic of the oversampling filter
is shown in Fig. 2–7.
dB
gain/attenuation
−6 dB
+6 dB
filter quality (Q)
0.5
3
0
-0.1
-0.2
The adjustment of the equalizer is supported by an
application program that allows to set up frequency
responses and to download the corresponding filter
coefficients into the UAC 3552A. When the frequency
response fits the target, it can be programmed into the
on-chip EEPROM. The UAC 3552A is shipped with a
flat frequency response.
-0.3
-0.4
-0.5
0
5000
10000
15000
20000
kHz
Fig. 2–7: 1 to 4 Oversampling filter, pass-band
Micronas
13
UAC 3552A
PRELIMINARY DATA SHEET
3. Specifications
3.1. Outline Dimensions
10 x 0.8 = 8 ± 0.1
0.17 ± 0.06
12
44
1
11
1.75
10 ± 0.1
0.375 ± 0.075
13.2 ± 0.2
1.3
0.8
22
34
1.75
0.8
23
10 x 0.8 = 8 ± 0.1
33
2.0 ± 0.1
13.2 ± 0.2
2.15 ± 0.2
10 ± 0.1
0.1
SPGS0006-3(P44)/1E
Fig. 3–1:
44-Pin Plastic Metric Quad Flat Pack
(PMQFP44)
Weight approximately 0.4 g
Dimensions in mm
3.2. Pin Connections and Short Descriptions
NC = not connected, leave vacant
LV = if not used, leave vacant
VSS = if not used, connect to VSS
= obligatory; connect as described in
circuit diagram
VDD = connect to VDD
Pin
No.
Pin Name
1
AGNDC
IN/OUT
X
Analog reference voltage
2
AVSS1
IN
X
VSS 1 for audio back-end
3
AVSS0
IN
X
VSS 0 for audio output amplifiers
4
OUTL
OUT
LV
Audio Output: Headphone left or Speaker +
5
OUTR
OUT
LV
Audio Output: Headphone right or Speaker −
6
AVDD0
IN
X
VDD 0 for audio output amplifiers
7
AVDD1
IN
X
VDD 1 for audio back-end
8
XTI
IN
X
quartz oscillator pin 1
9
XTO
OUT
X
quartz oscillator pin 2
10
NC
LV
Not connected
11
NC
LV
Not connected
12
NC
LV
Not connected
13
NC
LV
Not connected
14
GPIO 0
IN
VSS
HID IO 0
15
GPIO 1
IN
VSS
HID IO 1
14
Type
X
Connection
Short Description
(If not used)
Micronas
UAC 3552A
PRELIMINARY DATA SHEET
Pin
No.
Pin Name
16
GPIO 2
IN
VSS
HID IO 2
17
GPIO 3
IN
VSS
HID IO 3
18
NC
LV
Not connected
19
GPIO 4
OUT
LV
HID IO 4
20
GPIO 5
OUT
LV
HID IO 5
21
GPIO 6
OUT
LV
HID IO 6
22
GPIO 7
OUT
LV
HID IO 7
23
TRDY
OUT
LV
Test Output Pin
24
DMINUS
IN/OUT
X
USB DATA MINUS
25
DPLUS
IN/OUT
X
USB DATA PLUS
26
VREG
OUT
X
Capacitor for internal supply
27
VDD
IN
X
digital VDD
28
VSS
IN
X
digital VSS
29
TEST
IN
X
Test Enable
30
RESQ
IN
VDD
Power On Reset, active low
31
SUSPEND
OUT
LV
Low-Power Mode Indicator
32
SOF
OUT
LV
1-ms Start-Of-Frame Signal
33
AUXEN
IN
VSS
Enable AUX Input
34
NC
LV
Not connected
35
NC
LV
Not connected
36
AUXL
IN
VSS
AUX Input Left
37
AUXR
IN
VSS
AUX Input Right
38
FOUTL
OUT
X
Output to left external filter
39
FOPL
IN/OUT
X
Filter op amp inverting input, left
40
FINL
IN/OUT
X
Input for FiltoutL or
filter op amp output (line out)
41
FOUTR
OUT
X
Output to right filter op amp
42
FOPR
IN/OUT
X
Right Filter op amp inverting input
43
FINR
IN/OUT
X
Input for FILTOUTR or
Filter op amp output (line out)
44
VREF
IN
X
Analog reference Ground
Micronas
Type
Connection
Short Description
(If not used)
15
UAC 3552A
3.3. Pin Descriptions
3.3.1. Power Supply Pins
The UAC 3552A combines various analog and digital
functions which may be used in different modes. For
optimized performance, major parts have their own
power supply pins. All VSS power supply pins must be
connected.
VDD (27)
VSS (28)
The VDD and VSS power supply pair are connected
internally with all digital parts of the UAC 3552A.
AVDD0 (6)
AVSS0 (3)
AVDD0 and AVSS0 are separate power supply pins
that are exclusively used for the on-chip headphone/
loudspeaker amplifiers.
AVDD1 (7)
AVSS1 (2)
The AVDD1 and AVSS1 pins supply the analog audio
processing parts, except the headphone/loudspeaker
amplifiers.
3.3.2. Analog Audio Pins
AGNDC (1)
Reference for analog audio signals. This pin is used as
reference for the internal op amps. This pin must be
blocked against VREF with a 3.3-µF capacitor.
Note: The pin has a typical DC-level of 2.25 V. It can
be used as reference input for external op amps when
no current load is applied.
VREF (44)
Reference ground for the internal band-gap and biasing circuits. This pin should be connected to a clean
ground potential. Any external distortions on this pin
will affect the analog performance of the UAC 3552A.
PRELIMINARY DATA SHEET
AUXL (36)
AUXR (37)
The AUX pins provide two analog stereo inputs. Auxiliary input signals, e.g. the output of a conventional
receiver circuit or the output of a tape recorder can be
connected with these inputs. The input signals have to
be connected by capacitive coupling.
FOUTL (38)
FOPL (39)
FINL (40)
FOUTR (41)
FOPR (42)
FINR (43)
Filter op amps are provided in the analog baseband
signal paths. These inverting op amps are freely
accessible for external use by these pins.
The FOUTL/R pins are connected with the buffered
output of the internal switch matrix. The FOPL/R-pins
are directly connected with the inputs of the inverting
filter op amps. The FINL/R pins are connected with the
outputs of the op amps.
OUTL (4)
OUTR (5)
The OUTL/R pins are connected to the internal output
amplifiers. They can be used for either line-out or stereo headphones.
Caution: A short circuit at these pins for more than a
momentary period may result in destruction of the
internal circuits.
XTI (8)
XTO (9)
The XTI pin is connected to the input of the internal
crystal oscillator; the XTO pin to its output. Both pins
should be directly connected to the crystal and two
ground-connected capacitors (see application diagram).
DMINUS (24)
DPLUS (25)
Differential USB port pins.
16
Micronas
UAC 3552A
PRELIMINARY DATA SHEET
3.3.3. Other Pins
3.4. Pin Configuration
TEST (29)
Test enable. This pin is for test purposes only and must
always be connected to VSS.
VSS
TEST
VDD
RESQ
VREG (26)
This pin is used to connect an external buffer capacitor
to stabilize the internal supply for the USB transceiver.
RESQ (30)
This pin may be used to reset the chip.
GPIO 0 ... GPIO 7 (14,15,16,17,19,20,21,22)
These pins are configurable to be either input or output
and can be used to connect audio function keys or signalling LEDs.
SUSPEND (31)
This pin indicates that the host PC sets the USB bus to
the suspend-mode state.
DPLUS
SOF
DMINUS
AUXEN
TRDY
33 32 31 30 29 28 27 26 25 24 23
NC
34
22
GPIO 7
NC
35
21
GPIO 6
AUXL
36
20
GPIO 5
AUXR
37
19
GPIO 4
FOUTL
38
18
NC
FOPL
39
17
GPIO 3
FINL
40
16
GPIO 2
FOUTR
41
15
GPIO 1
FOPR
42
14
GPIO 0
FINR
43
13
NC
VREF
44
12
NC
UAC 3552A
1
SOF(32)
Start of Frame Signal. 1-ms signal that can be used for
external application circuits.
VREG
SUSPEND
2
3
4
5
6
7
8
9
AGNDC
NC
AVSS1
NC
AVSS0
AUXEN (33)
Aux enable. This pin must be connected to VSS if an
analog source is connected to the AUX input. Otherwise connect to VDD.
10 11
XTO
OUTL
XTI
OUTR
AVDD1
AVDD0
Fig. 3–2: 44-pin PMQFP package
TRDY (23)
Test Output Pin. This pin is intended for test purposes
only and must not be connected.
Micronas
17
UAC 3552A
PRELIMINARY DATA SHEET
3.5. Pin Circuits
ext. filter network
FOPn
FOUTn
AUXL/R
FINn
AGNDC
Fig. 3–8: Input Pins AUXL/R
AGNDC
Fig. 3–3: Pins FINR, FOPR, FINL, FOPL
OUTn
AGNDC
AGNDC
Fig. 3–9: Output Pins OUTL, OUTR
125 kΩ
VREF
DVSUP
AVSS0/1
P
Fig. 3–4: Pins AGNDC, VREF
N
GND
Fig. 3–10: Digital Output Pins SOF, SUSPEND
FOUTn
DPLUS
AGNDC
DMINUS
Fig. 3–5: Output Pins FOUTL, FOUTR
XTO
500 kΩ
XTI
Fig. 3–11: Digital Input/Output Pins DMINUS,
DPLUS
Fig. 3–6: Output/Input Pins XTI, XTO
DVSUP
P
Fig. 3–7: Input Pins RESQ, TEST, AUXEN
N
GND
Fig. 3–12: Input/Output Pins GPIO0...GPIO7
18
Micronas
UAC 3552A
PRELIMINARY DATA SHEET
3.6. Electrical Characteristics
3.6.1. Absolute Maximum Ratings
Symbol
Parameter
TA
Min.
Max.
Unit
Ambient Operating Temperature
0
70
°C
TS
Storage Temperature
−40
125
°C
PPmax
Power Dissipation
−
900
mW
VSUPA
Analog Supply Voltage1)
−0.3
6
V
VSUPD
Digital Supply Voltage
−0.3
6
V
VIdig
Input Voltage, all digital inputs
−0.3
VSUPD + 0.3
V
IIdig
Input Current, all digital inputs
−5
+0.5
mA
IIdig
Input Current, all digital outputs
−8
8
mA
IOdig
Output Current, all digital outputs
−14.8
14.8
mA
VIana
Input Voltage, all analog inputs
−0.3
VSUPA + 0.3
V
IIana
Input Current, all analog inputs
−5
−5
mA
IOaudio
Output Current, audio output2)
0.2
A
1)
2)
Pin
Name
AVDD0/1
OUTL/R
Both have to be connected together!
These pins are NOT short-circuit proof!
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.
Micronas
19
UAC 3552A
PRELIMINARY DATA SHEET
3.6.2. Recommended Operating Conditions
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
70
°C
Temperature Ranges and Supply Voltages
TA
Ambient Temperature Range
VSUPA1
Analog Audio Supply Voltage
AVDD0/1
4.5
5.0
5.5
V
VSUPD
Digital Supply Voltage
VDD
4.5
5.0
5.5
V
VSUPD
−0.25 V
0
Relative Supply Voltages
VSUPA
Analog Audio Supply Voltage in
relation to the Digital Supply Voltage
AVDD0/1
VIL
Input Voltage Low
GPI[7:0],
AUXEN,
VIH
Input Voltage high
GPI[7:0],
AUXEN
VRIL
Reset Input high-low transition
voltage
RESQ
VRIH
Reset Input low-high transition
voltage
RESQ
0.8
VSUPD
TRL
Reset low time after VDD stable
and oscillator start-up
RESQ
5
µs
1.0
5.5 V
0.25
0.75
VSUPD
VSUPD
0.45
VSUPD
Analog Reference
3.3
µF
AGNDC
10
nF
AUXL/R
0.525
CAGNDC1
Analog Reference Capacitor
AGNDC
CAGNDC2
Analog Reference Capacitor
Analog Audio Inputs
VAI
Analog Input Voltage AC
1.05
Vrms
6
kΩ
pF
7.5
kΩ
pF
Analog Filter Input and Output
ZAFLO
ZAFLI
Analog Filter Load Output1)
Analog Filter Load Input1)
FOUTL/R
FINL/R
7.5
5.0
Analog Audio Output
ZAOL_HP
20
Analog Output Load HP
(47 Ω Series Resistor required)
OUTL/R
32
400
Ω
pF
Micronas
UAC 3552A
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
70
°C
Quartz Characteristics
TAC
Ambient Temperature Range
FP
Load Resonance Frequency
at Cl = 20 pF
∆F/Fs
Accuracy of Adjustment
−20
20
ppm
∆F/Fs
Frequency Variation
versus Temperature
−20
20
ppm
REQ
Equivalent Series Resistance
12
30
Ω
C0
Shunt (parallel) Capacitance
3
5
pF
0
12
MHz
Voltage Regulator
3.3
µF
10
nF
CVREG1
Voltage Regulator Capacitor
VREG
CVREG2
Voltage Regulator Capacitor
VREG
RUSB
Input Serial Resistance
DPLUS/
DMINUS
24
(±0.5 %)
Ω
CUSB
Shunt Capacitor
DPLUS/
DMINUS
22
pF
1.0
Transceiver
1)
Please refer to Section 4.1. “Recommended Low-Pass Filters for Analog Outputs” on page 26.
Micronas
21
UAC 3552A
PRELIMINARY DATA SHEET
3.6.3. Characteristics
At TA = 0 to 70 °C, VSUPD = 4.75 V to 5.25 V, VSUPA = 4.75 V to 5.25 V; typical values at TJ = 27 °C,
VSUPD = VSUPA = 5.0 V, quartz frequency = 12 MHz, duty cycle = 50 %, positive current flows into the IC
bass/treble: 0 dB, bass boost: off, AGC: off, equalizer: off
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
100
125.5
mA
VSUPD =5 V
±1
µA
VGND ≤ VI ≤ VSUP
V
Iout =8 mA
Digital Supply
IVDD
Current Consumption1)
VDD
Digital Input Pin – Leakage
Input Leakage Current
II
GPIO[7:0],
AUXEN,
RESQ
Digital Output Pin
VOH
Output High Voltage
VOL
Output Low Voltage
GPIO[7:0],
SUSPEND,
SOF
VSUPD
− 0.4
0.4
V
15
mA
mA
SUSPD = 0, Mute
SUSPD = 1, Mute
50
dB
1 kHz sine at
100 mVrms
20
dB
≤ 100 kHz sine at
100 mVrms
Analog Supply
IAVDD
Current Consumption
Analog Audio
PSRRAA
Power Supply Rejection
Ratio for Analog Audio
Output
11
2
AVDD0/1,
OUTL/R
Reference Frequency Generation
VDCXTI
DC Voltage at Oscillator
Pins
XTI/O
0.5 *
VSUPA
V
CLI
Input Capacitance at
Oscillator Pin
XTI
3
pF
CLO
Input Capacitance at
Oscillator Pin
XTO
3
pF
VXTALOUT
Voltage Swing at Oscillator
Pins (peak-peak)
XTI/O
0.6 *
VSUPA
Oscillator Start-Up Time
1.0 *
VSUPA
V
10
ms
EEPROM
1)
22
EEPROM unpowered data
retention
10
Number of write cycles
100
year
no load attached to GPIO’s
Micronas
UAC 3552A
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
3.4
3.55
V
CL=1µF
USB Transceiver
VREG
Regulator Voltage
VREG
3.25
RO
Driver Output Resistance
including the 24-Ω external
serial resistor
DPLUS/
DMINUS
28
43
Ω
static, LOW or HIGH
tr / tf
Rise and Fall Times
DPLUS/
DMINUS
4
20
ns
CL=50 pF,
driver mode
MA_TRTF
Rise/Fall Time Matching
DPLUS/
DMINUS
90
111.1
%
CL=50 pF,
driver mode
VXOVER
Crossover Voltage
DPLUS/
DMINUS
1.3
2.0
V
CL=50 pF,
driver mode
VCM_DREC
Differential Receiver
Common-Mode Range
DPLUS/
DMINUS
0.8
2.5
V
VT_SREC
Single-ended Receiver
Threshold Voltage
DPLUS/
DMINUS
0.8
2.0
V
Analog Audio
VAGNDC
Analog Reference Voltage
AGNDC
RIAUX
Input Resistance at
Input Pins
AUXL/R
2.25
V
RL >> 10 MΩ,
referred to VREF
12.1
11.6
15
17.9
19.0
kΩ
kΩ
TJ = 27 °C
TA = 0 to 70 °C
Input selected,
SUSPD = 0
i = ± 10 µA,
referred to VREF
24.2
23.3
30
35.8
37.9
kΩ
kΩ
TJ = 27 °C
TA = 0 to 70 °C
Input not selected
SUSPD = 1
i = ± 10 µA,
referred to VREF
ROOUT
Output Resistance at
Output Pins
OUTL/R
700
Ω
TJ = 27 °C
SUSPD = 1
i = ± 200 µA,
referred to VREF
ROFILT
Output Resistance of
Filter Pins
FINL
15
kΩ
FINR
11.25
kΩ
SUSPD = 1, Mute
i = ± 10 µA,
referred to VREF
VOffI
Offset Voltage at Input Pins
AUXL/R
−20
20
mV
SUSPD = 0,
referred to AGNDC
VOffO
Offset Voltage at
Output Pins
OUTL/R
−10
10
mV
SUSPD = 0, Mute
referred to AGNDC
VOffFI
Offset Voltage at
Filter Output Pins
FOUTL/R
−20
20
mV
SUSPD = 0,
referred to AGNDC
VOffFO
Offset Voltage at
Filter Input Pins
FINL/R
−20
20
mV
SUSPD = 0,
referred to AGNDC
dVDCPD
Difference of DC Voltage at
Output Pins after Back-end
Low Power Sequence
OUTL/R
−10
10
mV
Analog Gain = Mute,
SUSPD switched from
0 to 1
Micronas
23
UAC 3552A
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
RD/A
D/A Pass Band Ripple
OUTL/R,
FOUTL/R
AD/A
D/A Stop Band Attenuation
BWAUX
Bandwidth for
Auxiliary Inputs
AUXL/R,
FINL/R
THDHP
Total Harmonic Distortion
OUTL/R
SNRAUX
Signal-to-Noise Ratio from
Analog Input to Outputs
AUXn,
OUTL/R
SNR1
Signal-to-Noise Ratio
OUTL/R
SNR2
Signal-to-Noise Ratio
OUTL/R
LevMute
Mute Level
OUTL/R
VAO
Analog Output Voltage AC
OUTL/R
1.0
1.05
GAUX
Gain from Auxiliary Inputs to
Outputs
AUXL/R,
OUTL/R
−0.5
0
PHP
Output Power (Headphone)
OUTL/R
24
Min.
Typ.
Max.
Unit
Test Conditions
0.01
dB
0...22 kHz
(no external filters
used)
60
dB
31 kHz...164 kHz
(no external filters
used)
760
kHz
0.05
%
BW = 20 Hz...0.5 fs,
unweighted, RL ≥ 32 Ω
(47 Ω series resistor
required),
Analog Gain = 0 dB,
Input 1 kHz at −3 dBFS
96
dB
input −40 dB below
1.05 Vrms
89
91
dB
RL ≥ 32 Ω
(external 47 Ω series
resistor required)
BW =20 Hz...0.5 fs
unweighted,
Analog Gain = 0 dB,
Input = −20 dBFS
58
62
dB
RL ≥ 32 Ω (external
47 Ω series resistor
required)
BW = 20 Hz..0.5 fs
unweighted
Analog Gain= −40.5 dB,
Input = −3 dBFS
−110
dBV
BW = 20 Hz...22 kHz
unweighted, no digital
input signal,
Analog Gain = Mute
1.1
Vrms
RL > 5 kΩ,
Analog Gain = 0 dB
Input = 0 dBFS digital
0.5
dB
f = 1 kHz, sine wave,
RL > 5 kΩ
0.5 Vrms to AUXL/R
mW
RL = 32 Ω,
Analog Gain = +2 dB,
distortion < 1%,
external 47 Ω series
resistor required
12
Micronas
UAC 3552A
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
GAO
Analog Output Gain
Setting Range
OUTL/R
−75
dGAO1
Analog Output Gain
Step Size
OUTL/R
3.0
dB
dGAO2
Analog Output Gain
Step Size
OUTL/R
1.5
dB
EGA1
Analog Output Gain Error
OUTL/R
−2
2
dB
Analog Gain = −54 dB
EGA2
Analog Output Gain Error
OUTL/R
−1
1
dB
Analog Gain = −45 dB
EGA3
Analog Output Gain Error
OUTL/R
−0.5
0.5
dB
Analog Gain = −39 dB
EdGA
Analog Output Gain
Step Size Error
OUTL/R
−0.5
0.5
dB
Analog Gain = −48 dB
XTALKHP
Crosstalk
Left/Right Channel
(Headphone)
OUTL/R
−70
−80
dB
f = 1 kHz, sine wave,
OUTL/R: RL ≥ 32 Ω
(47 Ω series resistor
required)
Analog Gain = 0 dB,
Input = −3 dBFS or
0.7 Vrms to AUXL/R
XTALK2
Crosstalk between
Input Signal Pairs
AUXnL/R
−70
−80
dB
f = 1 kHz, sine wave,
FOUTL/R: RL > 7.5 kΩ
OUTL/R: RL ≥ 32 Ω
(47-Ω series resistor
required)
Analog Gain = 0 dB,
Input = −3 dBFS and
0.7 Vrms to AUXL/R
Micronas
Typ.
Max.
Unit
18
dB
Test Conditions
Analog Gain:
−75 dB...-54 dB
Analog Gain:
−54 dB...+18 dB
25
UAC 3552A
PRELIMINARY DATA SHEET
4. Applications
3rd-order
4.1. Recommended Low-Pass Filters
for Analog Outputs 1)
1st-order
7.5 kΩ
330 pF
15 kΩ
15 kΩ
7.5 kΩ
1.8 nF
15 kΩ
7.5 kΩ
120 pF
1.8 nF
AVSS
FOUTL(R)
FOPL(R)
FINL(R)
−
FOUTL(R)
FOPL(R)
FINL(R)
−
Fig. 4–3: 3rd-order low-pass filter
Fig. 4–1: 1st-order low-pass filter
Table 4–3: Attenuation of 3rd-order low-pass filter
Table 4–1: Attenuation of 1st-order low-pass filter
Frequency
Gain
24 kHz
−2.2 dB
30 kHz
−3.0 dB
Gain
18 kHz
0.17 dB
24 kHz
−0.23 dB
30 kHz
−3.00 dB
11 kΩ
2nd-order
11 kΩ
Frequency
11 kΩ
220 pF
1.0 nF
AVSS
FOUTL(R)
FOPL(R)
FINL(R)
−
Fig. 4–2: 2nd-order low-pass filter
Table 4–2: Attenuation of 2nd-order low-pass filter
1)
Frequency
Gain
24 kHz
−1.5 dB
30 kHz
−3.0 dB
without deemphasis circuit
26
Micronas
1
2
3
4
J15
USB ser ies B
8VDC
P1
1
5
4
3
2
D5
1n4001
DD+
22p
100n
C22
22p
R18
11k
resq
+
VIN
470n
2
L1
Ferrite bead
C20
100n
100n
5Vana
C19
5Vdig
11k
C4
220p
R5
R9
11k
C1
12MHz
C17
22p
Y1
47u/16V
C16
C18
22p
470n
5
4
32
31
23
C10
10n
100n
C16
3.3u/16V
C14
5Vdig
UAC 3 5 5 2 A
OUTR
OUTL
SOF
Suspend
T R DY
GPIO7
GPIO6
GPIO5
GPIO4
22
21
20
19
C3
R14
11k
C5
220p
11k R 1 0 11k
R7
1n
UAC 3552A
+ C21
d m i nu s
dplus
AU X L
AU X R
TEST
RES#
AU X E N
GPIO0
GPIO1
GPIO2
GPIO3
U1
5Vdig
5Vana
100n
24
25
36
37
29
30
33
14
15
16
17
Bass Boost
S4
C11
R 2 9 single connection point
VO U T
J14
D-
C7
470n
S3
Mute
GPIO0
GPIO1
GPIO2
GPIO3
test
resq
S2
Volume down
J16
D+
auxen
R 1 7 1k
R 1 1 11k
R 6 11k
R21
11k
C6
5Vdig
R16
150k
24 0.5%
R25
1.5k
U2
LM7805
47u/16V
C23
1
R27
R 2 6 24 0.5%
P H O N E J AC K S T E R E O S W
J11
470n
C2
220k
R2
5Vdig
R 3 11k
S1
35
34
18
13
12
11
10
NC6
NC5
NC4
NC3
NC2
NC1
NC0
VREG
Volume up
1
VREG
GND
43
42
41
40
39
38
FinR
Fo p R
FoutR
FinL
FopL
FoutL
AV S S 1
AV S S 0
AV D D 0
AV D D 1
XTI
XTO
VREG
VDD
VSS
VREF
AGNDC
2
3
6
7
8
9
26
27
28
44
1
1n
+
C8
11k
R12
C9
160u/16V
160u/16V
+
R 1 11k
1
R23
1k
GPIO7
GPIO6
GPIO5
GPIO4
R 2 8 680
R 2 4 680
D4
D3
D2
D1
2
3
4
5
1
J7
LED
LED
LED
LED
J12
left
J17
right
J18
RCA right
J13
RCA left
P H O N E J AC K S T E R E O S W
R 1 5 1k
R 2 2 47
R 2 0 47
R19
1k
1k
1k
R 1 3 1k
R8
R4
1
1
Micronas
+
3
PRELIMINARY DATA SHEET
UAC 3552A
4.2. Typical Application
Fig. 4–4: Application circuit
27
UAC 3552A
PRELIMINARY DATA SHEET
5. Data Sheet History
1. Preliminary data sheet: “UAC 3552A Universal
Serial Bus DAC, Nov. 9, 1999, 6251-487-1PD. First
release of the preliminary data sheet.
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: [email protected]
Internet: www.micronas.com
Printed in Germany
Order No. 6251-487-1PD
28
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.
Micronas