ADVANCE‡ 64Mb: x16, x32 SYNCFLASH MEMORY SYNCFLASH® MEMORY MT28S4M16B1LL – 1 Meg x 16 x 4 banks MT28S2M32B1LL – 512K x 32 x 4 banks FEATURES PIN ASSIGNMENT (Top View) 90-Ball FBGA – 2 Meg x 32 • 125 MHz SDRAM-compatible read timing • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access • Programmable burst lengths: 1, 2 , 4, 8, or full page (read) 1, 2, 4, or 8 (write) • LVTTL-compatible inputs and outputs • 3.0V–3.6V VCC, 1.65V–1.95V VCCQ Additional VHH hardware protect mode (RP#) • Supports CAS latency of 1, 2, and 3 • Four-bank architecture supports true concurrent operation with zero latency Read any bank while programming or erasing any other bank • Deep power-down mode: 50µA (MAX) • Cross-compatible Flash memory command set • Operating temperature range of -40oC to +85oC OPTIONS 2 3 DQ26 DQ24 VSS B DQ28 VccQ VSSQ C VSSQ DQ27 DQ25 D VSSQ DQ29 DQ30 E VccQ DQ31 NC 7 8 9 DQ23 DQ21 VccQ VSSQ DQ19 DQ22 DQ20 VccQ DQ17 DQ18 VccQ NC DQ16 VssQ Vcc Vcc F VSS DQM3 A3 A2 DQM2 G A4 A5 A6 A10 A0 A1 H A7 A8 VccP NC BA1 NC J CLK CKE A9 BA0 CS# RAS# K DQM1 RP# DNU CAS# WE# DQM0 L VccQ DQ8 Vss Vcc DQ7 VSSQ M VSS DQ10 DQ9 DQ6 DQ5 VccQ N VSSQ DQ12 DQ14 DQ1 DQ3 VccQ P DQ11 VccQ VSSQ VccQ VSSQ DQ4 R DQ13 DQ15 Vss Vcc DQ0 DQ2 MARKING • Configuration 4 Meg x 16 (1 Meg x 16 x 4 banks) 2 Meg x 32 (512K x 32 x 4 banks) 90-Ball FBGA – 4 Meg x 16 4M16 2M32 • Read Timing (Cycle Time) 10ns (100 MHz) @ CL2 8ns (125 MHz) @ CL3 10ns (100 MHz) @ CL3 1 2 3 8 9 DNU DNU VSS Vcc DNU DNU B DNU VccQ VSSQ VccQ VSSQ DNU C VSSQ DNU DNU DNU DNU VccQ D VSSQ DNU DNU DNU DNU VccQ E VccQ DNU NC NC DNU VssQ Vcc A -8 -8 -10 • Package 90-ball FBGA FG 7 F VSS MCL A3 A2 MCL Part Number Example: G A4 A5 A6 A10 A0 A1 MT28S4M16B1LLFG-8 H A7 A8 VccP NC BA1 NC KEY TIMING PARAMETERS ACCESS SPEED CLOCK TIME SETUP HOLD GRADE FREQUENCY CL = 1* CL = 2* CL = 3* TIME TIME -8 125 MHz - - 7ns 2ns 1ns -10 100 MHz - - 7ns 2ns 1ns -8 1 A 100 MHz - 8ns - 2ns CLK CKE A11 BA0 CS# RAS# DQM1 RP# A9 CAS# WE# DQM0 L VccQ DQ8 Vss Vcc DQ7 VSSQ M VSS DQ10 DQ9 DQ6 DQ5 VccQ N VSSQ DQ12 DQ14 DQ1 DQ3 VccQ P DQ11 VccQ VSSQ VccQ VSSQ DQ4 R DQ13 DQ15 Vss Vcc DQ0 DQ2 1ns NOTE: 1. The # symbol indicates signal is active LOW. * CL = CAS (READ) Latency 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 J K 1 ©2002, Micron Technology, Inc. ‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY GENERAL DESCRIPTION This 64Mb SyncFlash® data sheet is divided into two major sections. The SDRAM Interface Functional Description details compatibility with the SDRAM memory, and the Flash Memory Functional Description specifies the symmetrical-sectored Flash architecture and functional commands. The 64Mb SyncFlash devices are nonvolatile, electrically sector-erasable (Flash), programmable readonly memory containing 67,108,864 bits. Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Each of the x32’s 16,777,216bit banks is organized as 2,048 rows by 256 columns by 32 bits. The 64Mb devices are organized into 16 independently erasable blocks. To ensure that critical firmware is protected from accidental erasure or overwrite, this device features sixteen (x32: 128K-Dword; x16: 256Kword) hardware and software-lockable blocks. A four-bank architecture supports true concurrent operations. A read access to any bank can occur simultaneously with a background PROGRAM or ERASE operation to any other bank. SyncFlash memory has a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read accesses to the memory are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ command. The address bits registered coincident with the ACTIVE command are used to select the bank and row 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 to be accessed. The address bits registered coincident with the READ command are used to select the starting column location for the burst access. The 64Mb devices provide for programmable read burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. The x16 device features an 8-word internal write buffer and the x32 features an 8-Dword internal write buffer that support mode register programmed burst write compatibility of 1, 2, 4, or 8 locations. SyncFlash memory uses an internal pipelined architecture to achieve high-speed operation. The 64Mb devices are designed to operate in 3.3V VCC and 1.8V VCCQ, low-power memory systems. A deep power-down mode is provided, along with a powersaving standby mode. All inputs and outputs are LVTTL-compatible. SyncFlash memory offers substantial advances in Flash operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation and the capability to randomly change column addresses on each clock cycle during a burst access. All Flash operations are performed using either a hardware command sequence (HCS) or a software command sequence (SCS). The HCS operations are used by memory controllers with native SyncFlash support. Standard SDRAM controllers can use SCS operation to perform Flash operations. Please refer to Micron’s Web site (www.micron.com/ syncflash) for the latest data sheet. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY TABLE OF CONTENTS Functional Block Diagram – 4 Meg x 16 ............... – 2 Meg x 32 ............... Pin and Ball Descriptions ....................................... Command Execution Logic (CEL) ............... Internal State Machine (ISM) ...................... ISM Status Register ...................................... Output (READ) Operations .............................. Memory Array ............................................. Status Register .............................................. Device Configuration Registers ................... Input Operations .............................................. Memory Array ............................................. Command Execution ........................................ Status Register .............................................. Device Configuration .................................. Program Sequence ....................................... Erase Sequence ............................................. Program and Erase NVMode Register ......... Block Protect/Unprotect Sequence ................... Device Protect Sequence .............................. Chip Initialize Sequence .............................. Disable LCR Sequence .................................. Reset/Deep Power-Down Mode ....................... Error Handling .................................................. Program/Erase Cycle Endurance ....................... Absolute Maximum Ratings ............................. DC Electrical Characteristics and Operating Conditions .......................... ICC Specifications and Conditions .................... Capacitance ....................................................... Electrical Characteristics and Recommended AC Operating Conditions (Timing Table) .. AC Functional Characteristics .......................... 4 5 6 SDRAM Interface Functional Description ....... Initialization ...................................................... Register Definition ............................................. Mode Register .............................................. Burst Length ............................................ Burst Type ............................................... CAS Latency ............................................ Operating Mode ..................................... Write Burst Mode ................................... Commands ........................................................ 9 9 9 9 9 11 11 11 11 12 Truth Table 1 (Commands and DQM Operation) ........ 12 Truth Table 2a (Harware Command Sequences [HCS]) ................................................. Truth Table 2b (Software Command Sequences [SCS]) .................................................. 13 14 17 17 17 17 17 17 17 17 17 18 18 19 24 24 24 24 25 Truth Table 3 (CKE) .................................................. 26 Truth Table 4 (Current State, Same Bank) .................. 27 Truth Table 5 (Current State, Different Bank) ............. 28 Command Inhibit ........................................ No Operation (NOP) ................................... Load Mode Register ..................................... Active ............................................................ Read ............................................................. Write ............................................................ Active Terminate .......................................... Burst Terminate ............................................ Load Command Register ............................. Operation .......................................................... Bank/Row Activation .................................. Reads ............................................................ Write Bursts .................................................. Active Terminate .......................................... Power-Down ................................................ Clock Suspend ............................................. Burst Read/Single Write ............................... Flash Memory Functional Description ............ Flash Command Sequence ............................... Hardware Command Sequence (HCS) ....... Software Command Sequence (SCS) .......... Memory Architecture ........................................ Protected Blocks ........................................... 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 Timing Waveforms Initialize and Load Mode Register RP# .............................................................. FCS .............................................................. Clock Suspend Mode ........................................ Reads Read ............................................................. Alternating Bank Read Accesses .................. Full-Page Burst ............................................. DQM Operation .......................................... Program/Erase Bank a followed by READ to bank a .......... Bank a followed by READ to bank b .......... 29 29 29 29 30 30 3 30 30 30 31 32 32 32 32 32 32 32 33 33 33 34 34 34 34 35 35 35 35 44 44 45 45 46 47 48 49 50 51 52 53 54 55 56 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 A0–A11, BA0, BA1 RAS# CAS# WE# CS# CLK CKE RP# VCCP 14 COMMAND DECODE ADDRESS REGISTER 12 MODE REGISTER NVMODE REGISTER COMMAND EXECUTION LOGIC 2 8 12 STATE MACHINE 4 COLUMNADDRESS COUNTER/ LATCH BANK CONTROL LOGIC 8 BANK 0 ROWADDRESS 4,096 LATCH & DECODER High Voltage Switch/Pump COLUMN DECODER 256 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 4,096 SENSE AMPLIFIERS BANK 0 MEMORY ARRAY (4,096 x 256 x 16) BANK 2 BANK 1 FUNCTIONAL BLOCK DIAGRAM 4 Meg x 16 BANK 3 16 16 2 ID REG. STATUS REG. DATA INPUT REGISTER DATA OUTPUT REGISTER 16 2 16 DQ0– DQ15 DQM0– DQM1 ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 A0–A10, BA0, BA1 RAS# CAS# WE# CS# CLK CKE RP# VCCP 13 COMMAND DECODE ADDRESS REGISTER 11 MODE REGISTER NVMODE REGISTER COMMAND EXECUTION LOGIC 2 8 11 STATE MACHINE 5 COLUMNADDRESS COUNTER/ LATCH BANK CONTROL LOGIC 8 BANK 0 ROWADDRESS 2,048 LATCH & DECODER High Voltage Switch/Pump COLUMN DECODER 256 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 8,192 SENSE AMPLIFIERS BANK 0 MEMORY ARRAY (2,048 x 256 x 32) BANK 2 BANK 1 FUNCTIONAL BLOCK DIAGRAM 2 Meg x 32 BANK 3 32 32 4 ID REG. STATUS REG. DATA INPUT REGISTER DATA OUTPUT REGISTER 16 4 32 DQ0– DQ31 DQM0– DQM3 ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY PIN AND BALL DESCRIPTIONS TSOP PIN FBGA BALL NUMBERS NUMBERS SYMBOL TYPE DESCRIPTION 68 J1 CLK Input Clock: CLK is driven by the system clock. All SyncFlash memory input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. 67 J2 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides STANDBY operation or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down modes, providing low standby power. CKE may be tied HIGH in systems where power-down modes (other than RP# deep power-down) are not required. 20 J8 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. 19, 18, 17 J9, K7, K8 RAS#, CAS#, WE# Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. 16, 71 K9, K1 x16: DQM0, DQM1 Input Input/Output Mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (after a two-clock latency) when DQM is sampled HIGH during a READ cycle. For x16, DQM0 corresponds to DQ0–DQ7, DQM1 corresponds to DQ8–DQ15. For x32, DQM0 corresponds to DQ0–DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23, DQM3 corresonds to DQ24–DQ31. DQM0–DQM3 are in the same state when referenced as DQM. A0–A11 Input Address Inputs: A0–A11 are sampled during the ACTIVE command (row address A0–A11 [x16]; A0–A10 [x32]) and READ/WRITE command (column-address A0–A7) to select one location in the respective bank. The address inputs provide the op-code during a LOAD MODE REGISTER command and the com-code during an LCR command. For x16: A11 is pin 66 (J3), and A9 is pin 70 (K3). BA0, BA1 Input Bank Address Input(s): BA0, BA1 define to which bank the ACTIVE, READ, or WRITE command is being applied. 16, 71, 28, 59 K9, K1, F8, x32: DQM0 F2 –DQM3 25–27, G8, G9, F7, 60–66, 24, F3, G1, G2, 70 G3, H1, H2, J3, K3, G7 22, 23 J7, H8 (continued on next page) 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY PIN AND BALL DESCRIPTIONS (continued) TSOP PIN FBGA BALL NUMBERS NUMBERS SYMBOL 30 K2 RP# 2, 4, 5, 7, R8, N7, R9, x16: DQ0– 8, 10, 11, N8, P9, M8, DQ15 13, 74, 76, M7, L8, L2, 77, 79, 80, M3, M2, P1, 82, 83, 85, N2, R1, N3, R2 TYPE DESCRIPTION Input Initialize/Power-Down: Upon initial device power-up, a 100µs delay after RP# has transitioned from LOW to HIGH is required for internal device initialization, prior to issuing an executable command. RP# clears the status register, sets the internal state machine (ISM) to the array read mode, and places the device in the deep power-down mode when LOW. All inputs, including CS#, are “Don’t Care” and all outputs are High-Z. When RP# = VHH, all protection modes are ignored during PROGRAM and ERASE. This input also allows the device protect bit to be set to “1” (protected) and allows the block protect bits at locations 0 and 15 to be set to “0” (unprotected). RP# must be held HIGH during all other modes of operation. I/O Data I/O: Data bus. 2, 4, 5, 7, 8, 10, 11, 13, 74, 76, 77, 79, 80, 82, 83, 85, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56 R8, N7, R9, x32: DQ0– N8, P9, M8, DQ31 M7, L8, L2, M3, M2, P1, N2, R1, N3, R2, E8, D7, D8, B9, C8, A9, C7, A8, A2, C3, A1, C2, B1, D2, D3, E2 3, 9, 35, 41, 49, 55, 75, 81 B2, B7, C9, D9, E1, L1, M9, P2, P7, N9 VCCQ Supply DQ Power: 1.65V–1.95V; provide isolated power to DQs for improved noise immunity. 6, 12, 32, B3, B8, C1, 38, 46, 52, D1, E9, L9, 78, 84 M1, N1, P3, P8 V SS Q Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. 1, 15, 29, 43 A7, F9, L7, R7 VCC Supply Power Supply: 3.0V–3.6V. 44, 58, 72, 86 A3, F1, L3, R3 VSS Supply Ground. (continued on next page) 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY PIN AND BALL DESCRIPTIONS (continued) TSOP PIN FBGA BALL NUMBERS NUMBERS SYMBOL TYPE DESCRIPTION 57 H3 VCCP 14, 21, 69, 73 E3, E7, H7, H9 NC – No Connect: These pins may be driven or left unconnected. x16: DNU – Do Not Use. – Must connect to Vss. 31, 36, 40, 47, 51, 33, 37, 42, 48, 53, 56 34, E8, D7, D8, 39, B9, C8, A9, 45, C7, A8, A2, 50, C3, A1, C2, 54, B1, D2, D3, E2 70 K3 x32: DNU 28, 59 F8, F2 x16: MCL 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 Supply Program/Erase Supply Voltage: VCCP must be tied externally to VCC. The VCCP pin sources current during device initialization, PROGRAM, and ERASE operations. 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE SDRAM INTERFACE FUNCTIONAL DESCRIPTION After initialization, the SyncFlash device is in standby mode and ready for mode register programming or an executable command. After initial programming of the nvmode register, the contents are automatically loaded into the mode register during initialization and the device will power-up in the programmed state. Note that when VCC is greater than 2.7V, either of the initialization procedures can be issued. In general, the 64Mb SyncFlash memory devices (1 Meg x 16 x 4 banks, 512K x 32 x 4 banks) are configured as a quad-bank, nonvolatile SDRAM that operate at 3.0V–3.6V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Each of the x32’s 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32 bits. Read accesses to the SyncFlash memory are identical to SDR SDRAM operation. Burst accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank; x32: A0–A10, x16: A0–A11 select the row). The address bits (A0–A7) registered coincident with the READ command are used to select the starting column location for the burst access. All non-READ operations are controlled with either a Hardware Command Sequence (HCS) or a Software Command Sequence (SCS). Both the HCS and SCS interface can be used to initiate any of the internal program, erase, initialization, or status operations. The term Flash command sequence (FCS) refers to either HCS or SCS operation. Prior to normal operation, the SyncFlash memory must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. Register Definition MODE REGISTER The mode register is used to define the specific mode of operation of the SyncFlash memory. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure 1. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is reprogrammed. The nvmode register settings are transferred into the mode register during initialization. The contents of the mode register may be copied into the nvmode register with a PROGRAM NVMODE REGISTER command. Details on erase nvmode register and program nvmode register command sequences are found in the Command Execution section of the Flash Memory Functional Description. Mode register bits M0–M2 specify the burst length, M3 specifies the burst type (sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the WRITE burst mode, and M10 and M11 are reserved for future use. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Initialization The device power-up procedure can be defined two ways. The first is a hardware initiated power-up, where power is applied to VCC , VCCQ, and VCC P (simultaneously). Then, with the clock stable, RP# must be brought from LOW to HIGH. After RP# transitions HIGH, the power-up initialization process will complete within 100µs. The second procedure is defined as a software initiated power-up. In this case the initialization is performed using the INITIALIZE DEVICE FCS operation. When the INITIALIZE DEVICE command is used, the RP# pin does not require the LOW-to-HIGH transition typically required for initialization. After the INITIALIZE DEVICE command has been issued, the power-up initialization process will complete within 100µs. Early completion of either initialization procedure can be detected by polling SR7 in the status register. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 BURST LENGTH Read and write accesses to the SyncFlash memory are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types (read or write), and a full-page burst is available for the sequential type (read only). The full-page burst can be used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. SDRAM 64Mb: x16, x32 SYNCFLASH MEMORY ADVANCE SDRAM 64Mb: x16, x32 SYNCFLASH MEMORY When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1–A7 when the burst length is set to two, by A2–A7 when the burst length is set to four, and by A3– A7 when the burst length is set to eight. The remaining (least significant) address bit(s) are used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Table 1 Burst Definition Burst Length 2 4 Figure 1 Mode Register Definition A11 A10 A9 111 10 9 A8 8 A6 A7 6 7 A5 5 A3 A4 4 Reserved* WB Op Mode CAS Latency 3 1 2 BT A1 A2 A0 0 Address Bus 8 Mode Register (Mx) Burst Length *Program M11, M10 = “0, 0” to ensure compatibility with future devices. Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved Full Page 256 0 Sequential 1 Interleaved M6 M5 M4 CAS Latency 0 0 0 Reserved 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation - - - M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 n = A0–A7 Cn, Cn+1, Cn+2 Cn+3, Cn+4... (location 0-255) …Cn-1, Cn... 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not supported NOTE: 1. For a burst length of two, A1–A7 select the blockof-two burst; A0 selects the starting column within the block. 2. For a burst length of four, A2–A7 select the blockof-four burst; A0–A1 select the starting column within the block. 3. For a burst length of eight, A3–A7 select the block-of-eight burst; A0–A2 select the starting column within the block. 4. For a full-page burst, the full row is selected and A0–A7 select the starting column. 5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. For a burst length of one, A0–A7 select the unique column to be accessed, and mode register bit M3 is ignored. 7. Burst write (x32: 1, 2, 4, or 8 Dwords, x16: 1, 2, 4, or 8 words) is supported (not full page). 8. The contents of the mode register can be read using the READ DEVICE CONFIGURATION command (004h). Burst Type M3 Starting Column Address All other states reserved NOTE: 1. A11 and M11 are supported only by 4 Meg x 16 configuration. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE BURST TYPE Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 1. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Table 2 indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. CAS LATENCY The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two, or three clocks. Figure 2 CAS Latency T0 T1 READ NOP OPERATING MODE The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to READ and WRITE bursts (full-page burst WRITE not supported). Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. T2 CLK COMMAND tLZ tOH DOUT DQ tAC WRITE BURST MODE When M9 = 0, the burst length programmed via M0–M2 applies to both read and write bursts; however, if full-page burst length is selected in conjunction with M9 = 0, the burst write length is 8 words for the x16 and 8-Dwords for the x32 (not full page). When M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. CAS Latency = 1 T0 T1 T2 T3 READ NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC Table 2 CAS Latency CAS Latency = 2 T0 T1 T2 T3 READ NOP NOP NOP ALLOWABLE OPERATING FREQUENCY (MHz) T4 CLK COMMAND tLZ SPEED tOH DOUT DQ tAC CAS CAS CAS LATENCY = 1 LATENCY = 2 LATENCY = 3 -8 £50 MHz £100 MHz £125MHz -10 £40 MHz £83 MHz £100 MHz CAS Latency = 3 DON’T CARE UNDEFINED 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. SDRAM 64Mb: x16, x32 SYNCFLASH MEMORY ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY SDRAM COMMANDS Truth Table 1 provides a quick reference of available commands for SDRAM-compatible operation. This is followed by a written description of each command. Additional truth tables appear later. TRUTH TABLE 1 SDRAM-COMPATIBLE INTERFACE COMMANDS AND DQM OPERATION (Notes: 1) NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR DQs NOTES COMMAND INHIBIT (NOP) H X X X X X X NO OPERATION (NOP) L H H H X X X ACTIVE (Select bank and activate row) L L H H X Bank/Row X 2 READ (Select bank, column and start READ burst) L H L H X Bank/Col X 3 WRITE (Select bank, column and start WRITE) L H L L X Bank/Col Valid 3, 4 BURST TERMINATE L H H L X X Active ACTIVE TERMINATE L L H L X X X 5 LOAD COMMAND REGISTER L L L H X Com-Code X 6, 7 LOAD MODE REGISTER L L L L X Op-Code X 8 Write Enable/Output Enable – – – – L – Active 9 Write Inhibit/Output High-Z – – – – H – High-Z 9 NOTE: 1. 2. 3. 4. 5. 6. 7. 8. 9. CKE is HIGH for all commands shown. x32: A0–A10, x16: A0–A11 provide row address, and BA0 and BA1 determine which bank is made active. A0–A7 provide column address, and BA0 and BA1 determine which bank is being read from or written to. A PROGRAM SETUP command sequence (see Truth Table 2a) must be completed prior to executing a WRITE. ACTIVE TERMINATE is functionally equivalent to the SDRAM PRECHARGE command; however, PRECHARGE (deactivate row in bank or banks) is not required for SyncFlash memory. A10 LOW: BA0 and BA1 determine the bank to be active terminated. A10 HIGH: All banks are active terminated and BA0 and BA1 are “Don’t Care.” A0–A7 define the com-code, and A8–A11 are “Don’t Care” for this operation. See Truth Table 2a. LOAD COMMAND REGISTER (LCR) replaces the SDRAM auto refresh or self refresh mode, which is not required for SyncFlash memory. LCR is the first cycle for Flash memory hardware command sequences (HCS). See Truth Table 2a. After the hardware LCR function is disabled, SyncFlash will treat SDRAM REFRESH or AUTO REFRESH commands as NOPs. A software command sequence (SCS) is available to perform all operations described in Truth Table 2b. A0–A10 define the op-code written to the mode register. The mode register can be dynamically loaded each cycle, provided tMRD is satisfied. The default mode register value is stored in the nvmode register. The contents of the nvmode register are automatically loaded into the mode register during device initialization. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 COMMANDS The following Truth Tables provide a quick reference of available commands for Flash memory interface operation. A written description of each command is found in the Flash Memory Functional Description section. TRUTH TABLE 2a – Hardware Command Sequences (Notes: 1–5; see notes on page 14.) FIRST CYCLE SECOND CYCLE CMD ADDR6 READ DEVICE CONFIGURATION LCR 90h Bank X H ACTIVE CAROW READ STATUS REGISTER LCR 70h X X H ACTIVE CLEAR STATUS REGISTER LCR 50h X X H ERASE SETUP/CONFIRM LCR 20h Bank X H ACTIVE Row Bank X H WRITE PROGRAM SETUP/PROGRAM LCR 40h Bank X H ACTIVE Row Bank X H WRITE PROTECT BLOCK/CONFIRM LCR 60h Bank X H ACTIVE Row10 Bank X H WRITE PROTECT DEVICE/CONFIRM LCR 60h Bank X H ACTIVE X Bank X H UNPROTECT BLOCKS/CONFIRM LCR 60h Bank X H ACTIVE X Bank X H OPERATION DQ RP# CMD7 BANK ADDR ADDR THIRD CYCLE BANK ADDR X DQ RP# CMD BANK ADDR ADDR Bank X H READ CACOL X X H READ X 13 DQ8 RP#9 NOTES Bank X H 11, 12 X X H X Bank D0h H/VHH 12, 13, 14 Col Bank DIN H/VHH 12, 13, 14, 15 X Bank LBDa(IN) H/VHH 12, 13, 15, 16 WRITE X Bank LBDa(IN) WRITE X Bank LBDb(IN) H/VHH 12, 13, 14, 15, 16 12, 13, 16 VHH VHH 12, 13, 16 LCR 60h Bank X H ACTIVE X Bank X H WRITE X Bank LBDb(IN) ERASE NVMODE REGISTER LCR 30h Bank X H ACTIVE X Bank X H WRITE X Bank C0h H 12, 13 PROGRAM NVMODE REGISTER LCR A0h Bank L X H ACTIVE X Bank L X H WRITE X Bank L X H 12, 13, 17, 18 DISABLE HARDWARE LCR LCR A0h Bank U X H ACTIVE X Bank U X H WRITE X Bank U X H CHIP INITIALIZE LCR 68h Bank X H ACTIVE X Bank X H WRITE X Bank C0h H 12, 13, 17, 18, 19 12, 13 SDRAM ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. UNPROTECT DEVICE/CONFIRM ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY SDRAM TRUTH TABLE 2b – SOFTWARE COMMAND SEQUENCES (SCS) (Notes: 1, 2, 4, 5; see notes on page 16) OPERATION FIRST CYCLE READ DEVICE CONFIGURATION 10 Command Active ADDR = 88h Bank Address = X DQ = X RP# = H READ STATUS REGISTER Command Active ADDR = 88h Bank Address = X DQ = X RP# = H CLEAR STATUS REGISTER Command Active ADDR = 88h Bank Address = X DQ = X RP# = H ERASE SETUP/CONFIRM Command Active ADDR = X Bank Address = X DQ = X RP# = H PROGRAM SETUP/CONFIRM Command Active ADDR = X Bank Address = X DQ = X RP#9 = H PROTECT BLOCK/CONFIRM Command Active ADDR = X Bank Address = X DQ = X RP#9 = H PROTECT DEVICE CONFIRM Command Active ADDR = X Bank Address = X DQ = X RP#9 = H SECOND CYCLE THIRD CYCLE FOURTH CYCLE FIFTH CYCLE SIXTH CYCLE SEVENTH CYCLE EIGHTH CYCLE Write 90h X X H Active CAROW Bank12 X H Read CACOL Bank12 X H Write 70h X X H Active X X X H Read X X X H Write 55h Bank12 X H Active 55h Bank12 X H Write 2Ah Bank12 55h H Active 80h Bank12 X H Write 20h Bank12 A0h H Active Row Bank12 X H Write X Bank12 D0h H/V H H Write 55h Bank12 X H Active 55h Bank12 X H Write 2Ah Bank12 55h H Active 80h Bank12 X H Write 40h Bank12 A0h H Active Row Bank12 X H Write Col Bank12 DIN H/V HH 15 Write 55h Bank12 X H Active 55h Bank12 X H Write 2Ah Bank12 55 H Active 80h Bank12 X H Write 60h Bank12 A0h H Active Row11 Bank12 X H Write X Bank12 LBDa(IN)16 H/V HH 15 Write 55h Bank12 X H Active 55h Bank12 X H Write 2Ah Bank12 55h H Active 80h Bank12 X H Write 60h Bank12 A0h H Active X10 Bank12 X H Write X Bank12 LBDa(IN)16 VHH Write 50h X X H (continued on next page) 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY (Notes: 1, 2, 4, 5; see notes on page 16) OPERATION FIRST CYCLE UNPROTECT BLOCK/CONFIRM10, 16 Command Active ADDR = X Bank Address = X DQ = X RP#5 = H UNPROTECT DEVICE/CONFIRM Command Active ADDR = X Bank Address = X DQ = X RP#5 = H ERASE NVMODE REGISTER Command Active ADDR = X Bank Address = X DQ = X RP# = H PROGRAM NVMODE REGISTER18 Command Active ADDR = X Bank Address = X DQ = X RP# = H DISABLE HARDWARE LCR19 Command Active ADDR = X Bank Address = X DQ = X RP# = H CHIP INITIALIZE Command Active ADDR = X Bank Address = X DQ = X RP# = H 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 SECOND CYCLE THIRD CYCLE FOURTH CYCLE FIFTH CYCLE SIXTH CYCLE SEVENTH CYCLE EIGHTH CYCLE Write 55h Bank12 X H Active 55h Bank12 X H Write 2Ah Bank12 55h H Active 80h Bank12 X H Write 60h Bank12 A0h H Active X11 Bank12 X H Write X Bank12 LBDb(IN)16 VHH Write 55h Bank12 X H Active 55h Bank12 X H Write 2Ah Bank12 55h H Active 80h Bank12 X H Write 60h Bank12 A0h H Active X Bank12 X H Write X Bank12 LBDb(IN)16 H/VHH Write 55h Bank12 X H Active 55h Bank12 X H Write 2Ah Bank12 55h H Active 80h Bank12 X H Write 30h Bank12 A0h H Active X Bank12 X H Write X Bank12 C0h H Write 55h Bank L12 X H Active 55h Bank L12 X H Write 2Ah Bank L12 55h H Active 80h Bank L12 X H Write A0h Bank L12 A0h H Active X Bank L12 X H Write X Bank L12 X H Write 55 Bank U12 X H Active 55h Bank U12 X H Write 2Ah Bank U12 55h H Active 80h Bank U12 X H Write 55h Bank12 X H Active 55h Bank12 X H Write 2Ah Bank12 55h H Active 80h Bank12 X H 15 Write Active Write A0h X X Bank U12,18 Bank U12,18 Bank U12,18 A0h X X H H H Write 68h Bank12 A0h H Active X Bank12 X H Write X Bank12 C0h H Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. SDRAM TRUTH TABLE 2b – SOFTWARE COMMAND SEQUENCES (SCS) (continued) ADVANCE SDRAM 64Mb: x16, x32 SYNCFLASH MEMORY NOTE: 1. CMD = Command: decoded from CS#, RAS#, CAS#, and WE# inputs. 2. NOP/COMMAND INHIBIT/BURST TERMINATE/ACTIVE TERMINATE commands may be issued throughout the HCS or SCS. Addtitionally, LOAD COMMAND REGISTER may be issued throughout the SCS. 3. After a PROGRAM or ERASE operation is registered to the ISM and prior to completion of the ISM operation, a READ to any location in the bank under ISM control will output the contents of the row activated prior to the LCR/active/write sequence (see Note 14). 4. To meet the tRCD specification, the appropriate number of NOP/COMMAND INHIBIT commands must be issued between ACTIVE and READ/WRITE commands. 5. The ERASE, PROGRAM, PROTECT, and UNPROTECT operations are self-timed. The status register may be polled to monitor these operations. 6. x32: A8–A10, x16: A8–A11 are “Don’t Care.” 7. A row will not be opened when ACTIVE is preceded by LCR. ACTIVE is considered a NOP. 8. x32 Data Inputs, DQ8–DQ31 are “Don’t Care” except for DIN, where all DQ31–DQ0 are driven. x16 Data Inputs, DQ8–DQ15 are "Don’t Care" except for DIN, where all DQ15–DQ0 are driven. Data Outputs: All unused bits are driven LOW. 9. VHH = 7.0V–8.5V 10. Address must be any row address in the Block desired to be protected. 11. CAROW, CACOL = Configuration address This value changes depending on the bit location being accessed CAROW = X02h for block protect bit, which corresponds to the block row address: x32: X = 0, 2, 4, or 6h x16: X = 0, 4, 8, or Ch For all other bits CAROW = XXXh (“Don’t Care”) 12. 13. 14. 15. 16. 17. 18. 19. CACOL = Values shown below 00h = Manufacturer compatibility ID = 2Ch 01h = Device ID MT28S4M16B1 = D5h Device ID MT28S2M32B1 = D4h 02h = Block protect bit (BPB) 03h = Device protect bit (DPB) 04h = Mode register 05h = Hardware load command register (LCR) bit 06h/07h = Reserved for future use BA = Bank address must match for all the cycles, except for manufacturer ID/device ID/device protect where it is xxh. The proper command sequence (LCR/active/write) is needed to initiate an ERASE, PROGRAM, PROTECT, or UNPROTECT operation. If the device protect bit is not set, RP# = VIH unprotects all sixteen ( x32: 128K-Dword, x16: 256K-word ) erasable blocks, except for blocks 0 and 15. When RP# = VHH, all sixteen ( x32: 128K-Dword, x16: 256K-word) erasable blocks (including blocks 0 and 15) will be unprotected, and the device protect bit will be ignored. If the device protect bit is set and RP# = VIH, the block protect bits cannot be modified. If the device protect bit is set, then an ERASE, PROGRAM, PROTECT, or UNPROTECT operation can still be initiated by bringing RP# to VHH prior to the WRITE command cycle and holding it at VHH until the operation is completed. LBDa = Lock bit data 01h = Set block protect bit F1h = Set device protect bit If the DPB is not set, RP# = VIH; all blocks can be set If the DPB is set, RP# = VIH; BPBs cannot be modified RP# = VHH; all BPBs can be modified To set DPB, RP# = VHH is a must RP# = VHH; all blocks including 0 and 15 are unprotected (reset); DPB does not matter LBDb = Lock bit data D0h = Clear block and device protect bit If the DPB is not set, RP# = VIH; all blocks except 0 and 15 are unprotected (reset) If the DPB is set, RP# = VIH; block protect bits cannot be modified RP# = VHH; all blocks including 0, 15, and DPB are unprotected (reset) Bank L: [BA1,BA0] = [0,0] or [0,1] Bank U: [BA1 BA0] = [1,0] or [1,1] If [BA1, BA0] = [0,0] or [0,1], then WRITE NVMODE REGISTER operation is performed. If [BA1, BA0] = [1,0] or [1,1], then DISABLE HARDWARE LCR operation is performed. Hardware LCR is preset to “1.” Hardware LCR bit is a one time programmable bit and cannot be reset to “1” after programmed to “0.” 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE WRITE The WRITE command is used to initiate a burst write access. A WRITE command must be preceded by LCR/ ACTIVE. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A7 selects the column location. Input data appearing on the DQs is written to the memory array, subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that word/column location. A WRITE command with DQM HIGH is considered a NOP. COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SyncFlash memory, regardless of whether the CLK signal is enabled. The SyncFlash memory is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to a SyncFlash memory that is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The mode register is loaded via inputs A0–A10. See the mode register heading in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. The data in the nvmode register is automatically loaded into the mode register upon powerup initialization and is the default mode setting unless dynamically changed with the LOAD MODE REGISTER command. ACTIVE TERMINATE ACTIVE TERMINATE, which replaces the SDRAM PRECHARGE command, is not required for SyncFlash memory, but is functionally equivalent to the SDRAM PRECHARGE command. ACTIVE TERMINATE can be issued to terminate a BURST READ in progress and may or may not be bank specific. BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated as shown in the Operation section of this data sheet. BURST TERMINATE is not bank specific. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs (x32: A0–A10, x16: A0–A11) selects the row. This row remains active for accesses until the next ACTIVE command, power-down or reset. LOAD COMMAND REGISTER (HCS ONLY) The LOAD COMMAND REGISTER command in the HCS is used to initiate Flash memory control commands to the command execution logic (CEL). The CEL receives and interprets commands to the device. These commands control the operation of the internal state machine and the read path (i.e., memory array, ID register or status register). However, there are restrictions on what commands are allowed in this condition. See the Command Execution section of Flash Memory Functional Description for more details. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A7 selects the starting column location. Read data appears on the DQs subject to the logic level on the DQM input two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. SDRAM 64Mb: x16, x32 SYNCFLASH MEMORY ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY Figure 3 Activating a Specific Row in a Specific Bank SDRAM Operation BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SyncFlash memory, a row in that bank must be “opened.” (Note: A row will not be activated for LCR/active/read or LCR/active/write command sequences. See Flash Memory Architecture section for additional information). This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks rounded to 3. This is reflected in Figure 4, which covers any case where 2 < tRCD (MIN)/tCK £ 3. (The same procedure is used to convert other specification limits from time units to clock cycles). A subsequent ACTIVE command to a different row in the same bank can be issued without having t o close a previous active row, provided the minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. Example: Meeting T0 tRCD CLK CKE HIGH CS# RAS# CAS# WE# x32: A0–A10 x16: A0–A11 ROW ADDRESS BANK ADDRESS BA0,BA1 Figure 4 (MIN) When 2 < tRCD (MIN)/tCK £ 3 T1 T2 NOP NOP T3 T4 CLK COMMAND ACTIVE READ or WRITE tRCD DON’T CARE 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 7 for CAS latencies of one, two and three; data element n + 3 is either the last of a burst of four, or the last desired of a longer burst. The SyncFlash memory uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed, random read accesses within a page can be performed as shown in Figure 8, or each subsequent READ may be performed to a different bank. READs Read bursts are initiated with a READ command, as shown in Figure 5. The starting column and bank addresses are provided with the READ command. During read bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 6 shows general timing for one, two and three CAS latency settings. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from any read burst may be truncated with a subsequent READ command, and data from a fixedlength read burst may be immediately followed by data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst, or the last desired data element of a longer burst that is being truncated. Figure 6 CAS Latency T0 T1 T2 READ NOP CLK COMMAND tLZ tOH DOUT DQ tAC Figure 5 READ Command CAS Latency = 1 CLK T0 T1 T2 T3 READ NOP NOP CLK CKE HIGH COMMAND tLZ CS# tOH DOUT DQ tAC CAS Latency = 2 RAS# CAS# T0 T1 T2 T3 T4 READ NOP NOP NOP CLK WE# COMMAND tLZ DOUT DQ A0–A7 COLUMN ADDRESS tOH tAC CAS Latency = 3 BA0, BA1 DON’T CARE BANK ADDRESS UNDEFINED 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. SDRAM 64Mb: x16, x32 SYNCFLASH MEMORY ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY SDRAM Figure 7 Consecutive Read Bursts T0 T1 T2 T3 T4 T5 CLK COMMAND READ NOP NOP NOP READ NOP X = 0 cycles ADDRESS BANK, COL n BANK, COL b DOUT n DQ DOUT n+2 DOUT n+1 DOUT n+3 DOUT b CAS Latency = 1 T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP READ NOP NOP X = 1 cycle BANK, COL b DOUT n DQ DOUT n+2 DOUT n+1 DOUT n+3 DOUT b CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND READ NOP NOP NOP READ NOP NOP NOP X = 2 cycles ADDRESS BANK, COL n BANK, COL b DOUT n DQ DOUT n+1 DOUT n+2 DOUT n+3 DOUT b CAS Latency = 3 NOTE: Each READ command may be to either bank. DQM is LOW. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 20 DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY T0 T1 T2 T3 SDRAM Figure 8 Random Read Accesses Within a Page T4 CLK COMMAND READ READ READ READ ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DOUT n DQ NOP DOUT x DOUT a DOUT m CAS Latency = 1 T0 T1 T2 T3 T4 T5 CLK COMMAND READ READ READ READ ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DOUT n DQ NOP NOP DOUT x DOUT a DOUT m CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ READ READ READ ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m NOP DOUT a DOUT n DQ NOP DOUT x NOP DOUT m CAS Latency = 3 NOTE: Each READ command may be to either bank. DQM is LOW. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 21 DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE SDRAM 64Mb: x16, x32 SYNCFLASH MEMORY Data from any read burst may be truncated with a subsequent WRITE command and data from a fixedlength read burst may be immediately followed by data from a subsequent WRITE command (subject to bus turnaround limitations). The WRITE may be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, provided that I/O contention can be avoided. In a given system design, there may be the possibility that the device driving the input data would go Low-Z before the SyncFlash memory DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. The DQM input is used to avoid I/O contention as shown in Figure 9. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z) regardless of the state of the DQM signal. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle. A fixed-length or full-page read burst can be truncated with ACTIVE TERMINATE (which may or may not be bank specific) or BURST TERMINATE (which is not bank specific). The ACTIVE TERMINATE or BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 11 for each possible CAS latency; data element n + 3 is the last desired data element of a burst of four or the last desired of a longer burst. Figure 9 HCS READ to WRITE Figure 10 HCS READ to WRITE with Extra Clock Cycle T0 T1 T2 T3 T4 CLK T0 T1 T2 T3 T4 T5 CLK DQM, H DQM COMMAND READ LCR ACTIVE ADDRESS BANK, COL n 40h BANK ROW NOP WRITE BANK, COL b tCK COMMAND READ LCR ADDRESS BANK, COL n 40H DQ DOUT n NOP BANK, ROW NOP WRITE BANK, COL b tHZ tHZ DQ ACTIVE DOUT n DIN b tDS DIN b tDS NOTE: NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. If a CAS latency of one is used, then DQM is not required. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. DON’T CARE 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY T0 T1 T2 T3 T4 T5 SDRAM Figure 11 Terminating a Read Burst T6 CLK COMMAND READ NOP NOP NOP BURST TERMINATE NOP NOP X = 0 cycles ADDRESS BANK, COL n DOUT n+2 DOUT n+1 DOUT n DQ DOUT n+3 CAS Latency = 1 T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP BURST TERMINATE NOP NOP X = 1 cycle DOUT n+2 DOUT n+1 DOUT n DQ DOUT n+3 CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP BURST TERMINATE NOP NOP NOP X = 2 cycles DOUT n DQ DOUT n+1 DOUT n+2 DOUT n+3 CAS Latency = 3 NOTE: DQM is LOW. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 DON’T CARE 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE SDRAM 64Mb: x16, x32 SYNCFLASH MEMORY WRITE BURSTS Write bursts are initiated with a WRITE command as shown in Figure 12. WRITE commands are preceded by an FCS program command. The 2 Meg x 32 features a 32-byte internal buffer, while the 4 Meg x 16 features a 16-byte internal write buffer which supports mode register programmed burst writes of 1, 2, 4, or 8 locations. The starting column and bank addresses are provided with the WRITE command. Once a WRITE command is registered, a READ command can be executed as defined by Truth Tables 4 and 5. An example is shown in Figure 14. During write bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 13). terminate operation. ACTIVE TERMINATE is considered a NOP for banks not addresssed by A10, BA0, BA1 (see Figure 15). POWER-DOWN Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. Entering power-down deactivates the input and output buffers (excluding CKE) after internal state machine operations (including WRITE operations) are completed for power savings while in standby (see Figure 16). The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). See the Reset/Deep Power-Down description in the Flash Memory Functional Description for maximum power savings mode. CLOCK SUSPEND The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored, any data present on the DQ pins remains driven, and burst counters are not incremented, as long as the clock is suspended (see examples in Figures 17 and 18). ACTIVE TERMINATE The ACTIVE TERMINATE command is functionally equivalent to the SDRAM PRECHARGE command. Unlike SDRAM, SyncFlash memory does not require a PRECHARGE command to deactivate the open row in a particular bank or the open rows in all banks. Asserting input A10 HIGH during an ACTIVE TERMINATE command will terminate a BURST READ in any bank. When A10 is low during an ACTIVE TERMINATE command, BA0 and BA1 will determine which bank will undergo a Figure 12 WRITE Command Figure 13 Write Burst CLK CKE T0 T1 T2 T3 COMMAND WRITE NOP NOP NOP ADDRESS BANK, COL n HIGH CK CS# RAS# CAS# DQ WE# DIN n DIN n+1 NOTE: Burst length = 2. DQM is LOW. A0–A7 COLUMN ADDRESS DON’T CARE BA0, BA1 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 BANK ADDRESS 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. SDRAM Figure 16 Power-Down Coming out of a power-down sequence (active), tCKS (CKE setup time) must be greater than or equal to 3ns. BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. All WRITE commands result in the access of a single column location (burst of one). READ commands access columns according to the programmed burst length and sequence. (( )) (( )) CLK tCKS CKE t CKS (( )) COMMAND (( )) (( )) NOP NOP ACTIVE tRCD tRAS All banks idle Input buffers gated off Figure 14 HCS WRITE to READ T0 T1 Enter power-down mode. T2 tRC Exit power-down mode. Figure 17 Clock Suspend During Write Burst T3 CLK T0 T1 NOP WRITE T2 T3 T4 T5 NOP NOP DIN n+1 DIN n+2 CK COMMAND READ WRITE NOP NOP CKE ADDRESS BANK, COL n BANK, COL b INTERNAL CLOCK COMMAND DIN n DQ DbOUT BANK, COL n ADDRESS NOTE: A CAS latency of two is used for illustration. The WRITE command may be to any bank and the READ command may be to any bank. DQM is LOW. For more details, refer to Truth Tables 4 and 5. NOTE: T1 For this example, burst length = 4 or greater, and DQM is LOW. Figure 18 Clock Suspend During Read Burst Figure 15 Terminating a Write Burst T0 DIN n DQ T0 T2 T1 T2 T3 T4 T5 T6 CLK CK CKE BURST TERMINATE NEXT COMMAND COMMAND WRITE ADDRESS BANK, COL n (ADDRESS) DIN n (DATA) DQ NOTE: INTERNAL CLOCK COMMAND READ ADDRESS BANK, COL n DQ DQMs are LOW, and burst length >1. BURST TERMINATE command causes data on DQ to become invalid. NOP NOP DOUT n NOP DOUT n+1 NOP DOUT n+2 NOP DOUT n+3 NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and DQM is LOW. DON’T CARE 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY SDRAM TRUTH TABLE 3 – CKE (Notes: 1–4) CKEn-1 CKEn L L CURRENT STATE COMMAND n ACTION n Clock Standby X Maintain Clock Standby Clock Suspend X Maintain Clock Suspend COMMAND INHIBIT or NOP Exit Clock Standby 5 6 L H Clock Standby Clock Suspend X Exit Clock Suspend H L No Burst in Progress COMMAND INHIBIT or NOP Clock Standby Reading VALID Clock Suspend H H NOTES See Truth Table 4 NOTE: 1. 2. 3. 4. 5. “CKEn” is the logic state of CKE at clock edge n; “CKEn-1” was the state of CKE at the previous clock edge. “CURRENT STATE” is the state of the SyncFlash memory immediately prior to clock edge n. “COMMANDn” is the command registered at clock edge n and “ACTIONn” is a result of COMMANDn. All states and sequences not shown are illegal or reserved. Exiting power-down at clock edge n will put the device in the idle state in time for clock edge n + 1 (provided that tCKS is met). 6. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY (Notes: 1–6) CURRENT STATE C S # R A S #C A S # W E # Any Idle Row Active Read Write COMMAND/ACTION NOTES H X X X COMMAND INHIBIT (NOP/continue previous operation) L H H H NO OPERATION (NOP/continue previous operation) L L H H ACTIVE (Select and activate row) L L L H LOAD COMMAND REGISTER L L L L LOAD MODE REGISTER 7 L L H L ACTIVE TERMINATE 8 L H L H READ (Select column and start Read burst) L H L L WRITE (Select column and start WRITE) L L H L ACTIVE TERMINATE L L L H LOAD COMMAND REGISTER L H L H READ (Select column and start new Read burst) L L H L ACTIVE TERMINATE 8 L H H L BURST TERMINATE 9 L L L H LOAD COMMAND REGISTER L H L H READ (Select column and start new Read burst) L L L H LOAD COMMAND REGISTER 8 10 NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 3). 2. This table is bank specific, except where noted; i.e., the Current State is for a specific bank and the commands shown are those allowed to be issued to that bank, when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank is not in read or write mode. Row Active: A row in the bank has been activated and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A read burst has been initiated and has not yet terminated or been terminated. Write: A WRITE operation has been initiated to the SyncFlash internal state machine (ISM) and has not yet completed. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank, should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 4, and according to Truth Table 5. Active Terminate: Starts with registration of an ACTIVE TERMINATE command and ends on the next clock cycle. The bank will then be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the SyncFlash memory will be in the all banks idle state. Initialize Mode: Starts with RP# transitioning from LOW to HIGH and ends after 100µs delay. 6. All states and sequences not shown are illegal or reserved. 7. Not bank specific; requires that all banks are idle. 8. May or may not be bank specific. 9. Not bank specific; BURST TERMINATE affects the most recent read burst, regardless of bank. 10. A READ operation to the bank under ISM control will output the contents of the row activated prior to the LCR/active/ write sequence (see Truth Table 2a). 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. SDRAM TRUTH TABLE 4 – CURRENT STATE BANK n; COMMAND TO BANK n ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY SDRAM TRUTH TABLE 5 – CURRENT STATE BANK n; COMMAND TO BANK m (Notes: 1–6) CURRENT STATE C S # R A S #C A S # W E # Any COMMAND/ACTION H X X X COMMAND INHIBIT (NOP/continue previous operation) L H H H NO OPERATION (NOP/continue previous operation) Idle X X X X Any command otherwise allowed to Bank m Row L L H H ACTIVE (Select and activate row) Activating, L H L H READ (Select column and start read burst) Active, or L H L L WRITE (Select column and start WRITE) Active L L H L ACTIVE TERMINATE Terminate L L L H LOAD COMMAND REGISTER L L H H ACTIVE (Select and activate row) L H L H READ (Select column and start new read burst) L L H L ACTIVE TERMINATE L L L H LOAD COMMAND REGISTER L L H H ACTIVE (Select and activate row) L H L H READ (Select column and start read burst) L L H L ACTIVE TERMINATE L H H L BURST TERMINATE L L L H LOAD COMMAND REGISTER (HCS) Read Write NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 3). 2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank is not in initialize, read, write mode. Row Active: A row in the bank has been activated and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A read burst has been initiated and has not yet terminated or been terminated. Write: A WRITE operation has been initiated to the SyncFlash ISM and has not yet completed. 4. LOAD MODE REGISTER command may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY FLASH COMMAND SEQUENCE All Flash operations are performed using either a hardware command sequence (HCS) or a software command sequence (SCS). The HCS operations are used in systems that support the LOAD COMMAND REGISTER (LCR) command. In systems that do not have the ability to generate an LCR command, SCS operations can be used for Flash operations. A Flash command sequence (FCS) is used to describe Flash operations where the actual implementation (HCS or SCS) is not relevant. The SyncFlash memory incorporates a number of features that make it ideally suited for code storage and execute-in-place applications on an SDRAM bus. The memory array is segmented into individual erase blocks. Each block may be erased without affecting data stored in other blocks. These memory blocks are read, programmed, and erased by issuing commands to the command execution logic (CEL). The CEL controls the operation of the internal state machine (ISM), which completely controls all READ DEVICE CONFIGURATION, READ STATUS REGISTER, CLEAR STATUS REGISTER, RESET DEVICE/CONFIRM, PROGRAM SETUP/CONFIRM, PROTECT BLOCKS/CONFIRM, PROTECT DEVICE/CONFIRM, UNPROTECT DEVICE /CONFIRM, UNPROTECT BLOCKS/CONFIRM, ERASE NVMODE REGISTER, PROGRAM NVMODE REGISTER, DISABLE HARDWARE LCR, ERASE SETUP CONFIRM and CHIP INITIALIZATION operations. The ISM protects each memory location from overerasure and optimizes each memory location for maximum data retention. In addition, the ISM greatly simplifies the control necessary for programming the device in-system or in an external programmer. The Flash Memory Functional Description provides detailed information on the operation of the SyncFlash memory and is organized into these sections: • • • • • • • • HARDWARE COMMAND SEQUENCE (HCS) All HCS operations are executed with LCR, LCR/ ACTIVE/READ, or LCR/ACTIVE/WRITE commands and command sequences as defined in Truth Tables 1 and 2a. See PROGRAM/ERASE diagram for timing information. See the SDRAM Interface Functional Description for information on reading the memory array. Address pins A0–A7 are used to input 8-bit commands during the LCR command cycle. This command will identify which Flash operation is initiated. Certain LCR/active/write command sequences require an 8-bit confirmation code on the WRITE cycle. The confirmation code is input on DQ0–DQ7. SOFTWARE COMMAND SEQUENCE (SCS) Flash operations can also be performed using an SCS. The SCS uses a series of standard CPU READ and WRITE op-codes to perform Flash operations. This command interface is similar to the multistep sequence common in standard Flash components. Table 3 is an example of programming data into a particular address using SCS. See Truth Table 2b for a description of SCS operations. Command Interface Memory Architecture Output (READ) Operations Input Operations Command Execution Reset/Power-Down Mode Error Handling PROGRAM/ERASE Cycle Endurance Table 31 Software Code to Program Data Value 1234h to Address 0000h Using SCS ASSEMBLY CODE EXECUTED SDRAM COMMANDS ISSUED OP-CODE ADDRESS, DATA COMMAND BANK ADDRESS DATA WRITE 00000055h, 00000000h ACTIVE WRITE 0h 0h 000h 55h XXXX 0000h WRITE 0000552Ah, 00000055h ACTIVE WRITE 0h 0h 055h 2Ah XXXX 0055h WRITE 00008040h, 000000A0h ACTIVE WRITE 0h 0h 080h 40h XXXX 00A0h WRITE 00000000h, 00001234h ACTIVE WRITE 0h 0h 000h 00h XXXX 1234h NOTE: 1. This is a programming example for the 4 Meg x 16. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. FLASH FLASH MEMORY FUNCTIONAL DESCRIPTION ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY FLASH When a CPU executes a WRITE op-code to a memory address configured for SDRAM, the memory controller issues an ACTIVE command followed by a WRITE command. A similar ACTIVE/READ pair is also issued during a READ operation. By issuing ACTIVE/WRITE and ACTIVE/READ pairs with predefined address and data values, any of the Flash commands can be performed. a PROTECT BLOCK operation has been executed to these blocks, an UNPROTECT ALL BLOCKS operation will unlock all blocks except the blocks at locations 0 and 15 unless RP# = VHH. This provides additional security for critical code during in-system firmware updates should an unintentional power disruption or system reset occur. A second level of block protection is possible by completing a hardware DEVICE PROTECT operation. DEVICE PROTECT prevents block protect bit modification. The protection status of any block may be checked by reading the protect bits with a read device configuration command sequence. MEMORY ARCHITECTURE The 64Mb SyncFlash memory is a four-bank architecture with four erasable blocks per bank. By erasing blocks rather than the entire array, the total device endurance is enhanced, as is system flexibility. Only the ERASE and BLOCK PROTECT functions are block ori-ented. The four banks have simultaneous readwhile-write functionality. An ISM PROGRAM or ERASE operation to any bank can occur simultaneously to a READ to any other bank. The SyncFlash memory has a single background operation ISM to control power-up initialization, ERASE, PROGRAM, and PROTECT operations. ISM operations are initiated with an HCS or SCS. Only one ISM operation can occur at any time; however, certain other commands, including READ operations, can be performed while an ISM operation is taking place. A new HCS or SCS will not be permitted until the current ISM operation is complete. An operational command controlled by the ISM is defined as either a bank-level operation or a devicelevel operation. PROGRAM and ERASE are bank-level ISM operations. After an ISM bank-level operation has been initiated, a READ may be issued to any bank; however, a READ to the bank under ISM control will output the contents of the row activated prior to the HCS or SCS. CHIP INITIALIZE, HARDWARE LCR DISABLE, ERASE NVMODE REGISTER, PROGRAM NVMODE REGISTER, BLOCK PROTECT, DEVICE PROTECT, and UNPROTECT ALL BLOCKS are device-level ISM operations. Once an ISM device-level operation has been initiated, a READ to any bank will output the contents of the array. A READ STATUS REGISTER command sequence may be issued to determine completion of the ISM operation. When SR7 = 1, the ISM operation is complete and a new ISM operation may be initiated. COMMAND EXECUTION LOGIC (CEL) SyncFlash operations are executed by issuing the appropriate commands to the CEL. The CEL receives and interprets commands to the device. These commands control the operation of the ISM and the read path (i.e., memory array, device configuration, or status register). Commands may be issued to the CEL while the ISM is active. However, there are restrictions on what commands are allowed in this condition. See the Command Execution section for more details. INTERNAL STATE MACHINE (ISM) Power-up initialization, erase, program, and protect timings are simplified by using an ISM to control all programming algorithms in the memory array. The ISM ensures protection against overerasure and optimizes programming margin to each cell. During PROGRAM operations, the ISM automatically increments and monitors PROGRAM attempts, verifies programming margin on each memory cell and updates the ISM status register. When BLOCK ERASE is performed, the ISM automatically overwrites the entire addressed block (eliminates overerasure), increments and monitors ERASE attempts, and sets bits in the ISM status register. ISM STATUS REGISTER The 16-bit ISM status register allows an external processor to monitor the status of the ISM during device initialization, ERASE NVMODE REGISTER, PROGRAM NVMODE REGISTER, PROGRAM, ERASE, BLOCK PROTECT, DEVICE PROTECT or UNPROTECT ALL BLOCKS, and any related errors. ISM operations and related errors can be monitored by reading status register bits on DQ0–DQ8. All of the defined bits are set by the ISM, but only the ISM status bits (SR0, SR1, SR2, SR7) are cleared by the ISM. The erase/unprotect block, program/protect block, and device protection bits must be cleared by PROTECTED BLOCKS The 64Mb SyncFlash devices are organized into 16 erasable memory blocks. Each block may be software protected by issuing the appropriate FCS for a BLOCK PROTECT operation. The blocks at locations 0 and 15 have additional protection to prevent inadvertent PROGRAM or ERASE operations in platforms where Vih is not available. Once 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE the host system using the CLEAR STATUS REGISTER command. This allows the user to choose when to poll and clear the status register. For example, the host system may perform multiple PROGRAM operations before checking the status register instead of checking after each individual PROGRAM. A V CC power sequence error is cleared by reinitializing the device. Asserting the RP# signal or powering down the device will also clear the status register. SyncFlash memory features three different types of READs. Depending on the mode, a READ operation will produce data from the memory array, status regis- ter, or one of the device configuration registers. SyncFlash memory is in the array read mode unless a status register or device register read is initiated or in progress. A READ to the device configuration register or the status register must be issued as defined by the FCS. The burst length of data-out is defined by the mode register settings. Reading the device configuration register or status register will not disrupt data in a previously open (or “activated”) page. When the burst is complete, a subsequent READ will read the array. However, several differences exist and are described in the following section. Moving between modes to perform a specific READ will be covered in the Command Execution section. Figure 19 2 Meg x 32 Memory Address Map Figure 20 4 Meg x 16 Memory Address Map OUTPUT (READ) OPERATIONS ADDRESS RANGE 128K-Dword Block 14 128K-Dword Block 13 128K-Dword Block 12 128K-Dword Block 11 128K-Dword Block 10 128K-Dword Block 9 128K-Dword Block 8 128K-Dword Block 7 128K-Dword Block 6 128K-Dword Block 5 128K-Dword Block 4 128K-Dword Block 3 128K-Dword Block 2 128K-Dword Block 1 128K-Dword Block 0 Co lu m FFF C00 BFF 800 7FF 400 3FF 000 FFF C00 BFF 800 7FF 400 3FF 000 FFF C00 BFF 800 7FF 400 3FF 000 FFF C00 BFF 800 7FF 400 3FF 000 FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h 256K-word Block 15 256K-word Block 14 256K-word Block 13 256K-word Block 12 256K-word Block 11 256K-word Block 10 256K-word Block 9 256K-word Block 8 256K-word Block 7 256K-word Block 6 256K-word Block 5 256K-word Block 4 256K-word Block 3 256K-word Block 2 256K-word Block 1 256K-word Block 0 Word-wide (x16) Dword-wide (x32) Unlock Blocks (RP# = VHH) Unlock Blocks (RP# = VHH) Unlock Blocks (RP# = VIH) Unlock Blocks (RP# = VIH) 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 w Ba Bank 3 128K-Dword Block 15 Bank 2 FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h Ro nk m lu Co w Ro 7FF 600 5FF 400 3FF 200 1FF 000 7FF 600 5FF 400 3FF 200 1FF 000 7FF 600 5FF 400 3FF 200 1FF 000 7FF 600 5FF 400 3FF 200 1FF 000 Bank 1 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Bank 0 Bank 0 Bank 1 Bank 2 Bank 3 Ba nk n n ADDRESS RANGE NOTE: See block lock and unlock flowchart sequences for additional information. 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. FLASH 64Mb: x16, x32 SYNCFLASH MEMORY ADVANCE FLASH 64Mb: x16, x32 SYNCFLASH MEMORY MEMORY ARRAY A READ command to any bank will output the contents of the memory array. While a PROGRAM or ERASE ISM operation is in progress, a READ to any location in the bank under ISM control will output the contents of the row activated prior to an FCS; a READ to any other bank will output the contents of the array. All commands and their operations are covered in the SDRAM Interface Functional Description section. the array is input on the DQ pins. The data and addresses are latched on the rising edge of the clock. Details on how to input data to the array is covered in the Command Execution section. COMMAND EXECUTION Commands are issued to bring the device into different operational modes. Each mode has specific operations that can be performed while in that mode. All HCS modes require that an LCR/active/read or LCR/ active/write sequence be issued, except CLEAR STATUS REGISTER, which is a single LCR command. Inputs A0–A7 during the FCS determine the operation being performed. The following section describes the properties of each mode, and Truth Tables 1, 2a, and 2b list all commands and command sequences required to perform the desired operation. Read-whilewrite functionality allows a background operation program or erase to any bank while simultanously reading any other bank. The HCS operations in Truth Table 2a must be completed on consecutive clock cycles. However, in order to reduce bus contention issues, an unlimited number of NOPs or COMMAND INHIBITs can be issued throughout the LCR/active/write command sequence. For additional protection, these command sequences must have the same bank address for the three command cycles. The SCS operations described in Truth Table 2b must also be completed on adjacent clock cycles. The SCS operation will allow NOP, COMMAND INHIBIT, REFRESH, and BURST TERMINATE commands to be issued during the sequence without aborting the sequence. All steps in the SCS must access the same bank or the operation will be aborted and the device will return to the read array mode. If the bank address changes during the FCS or if the command sequences are not consecutive (other than NOPs and COMMAND INHIBITs), the program and erase status bits (SR4 and SR5) will be set and the desired operation will be aborted. For additional protection, these command sequences must have the same bank address during all command cycles. STATUS REGISTER Reading the status register requires an FCS. The status register contents are latched on the next positive clock edge subject to CAS latencies. The burst length of the status register data-out is defined by the mode register. All commands and their operations are covered in the Command Execution section. DEVICE CONFIGURATION REGISTERS To read the device ID, manufacturer compatibility ID, device protection status, block protect status, and the hardware LCR disable bit, the appropriate command sequence for READ DEVICE CONFIGURATION must be issued. This is the same input sequencing used when reading the status register, except that specific addresses must be issued. INPUT OPERATIONS An FCS is required to program the array, or to perform an ERASE, PROTECT, UNPROTECT, or HARDWARE LCR DISABLE operation. The first cycle of an input operation is an FCS operation where inputs A0– A7 determine the input command being executed to the CEL. An input operation will not disrupt data in a previously opened page. The DQ pins are used either to input data to the array or to input a command to the CEL during the WRITE cycle. More information describing how to program, erase, protect, or unprotect the device is provided in the Command Execution section. MEMORY ARRAY Programming or erasing the memory array sets the desired bits to logic 0s but cannot change a given bit to a logic 1 from a logic 0. Setting any bit to a logic 1 requires that the entire block be erased. Programming a protected block requires that the RP# pin be brought to VHH. A0–A10 (x32), A0–A11 (x16) provide the address to be programmed, while the data to be programmed in 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 STATUS REGISTER Reading and clearing the status register requires an FCS. During status reads, the status register contents are latched on the next positive clock edge, subject to CAS latencies, for a burst length defined by the mode register. 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY DEVICE CONFIGURATION To read the device ID, manufacturer compatibility ID, device protect bit, and each of the block protect bits, the appropriate FCS operation for READ DEVICE CONFIGURATION must be issued. Specific configuration addresses must be issued to read the desired information. The manufacturer compatibility ID is read at 000h; the device ID is read at 001h. The manufacturer compatibility ID and device ID are output on DQ0–DQ7. The device protect bit is read at 003h; and each of the block protect bits is read on the third address location within each block (x02h). The device and block protect bits are output on DQ0. The mode register is read from address 004h. The hardware load command register bit is available on bit 0 of address 005h. A LOW on bit zero means that HCS operations are disabled and a HIGH means that HCS operations are allowed. The device configuration register contents are output subject to CAS latencies for a burst length defined by the mode register. ERASE SEQUENCE Executing an erase sequence will set all bits within a block to logic 1. The HCS necessary to execute an ERASE is similar to that of a PROGRAM. To provide added security against accidental block erasure, three consecutive command sequences on consecutive clock edges are required to initiate an ERASE of a block. See Table 2a. In the first cycle, LOAD COMMAND REGISTER is issued with ERASE SETUP (20h) on A0–A7, and the bank address of the block to be erased is issued on BA0, BA1. The next command is ACTIVE, where A10, A11, BA0, and BA1 provide the address of the block to be erased. The third cycle is WRITE, during which ERASE CONFRIM (D0h) is issued on DQ0–DQ7 and the bank address is reissued. The ISM status bit will be set on the following clock edge (subject to CAS latencies). After ERASE CONFIRM (D0h) is issued, the ISM will start erasing the addressed block. When the ERASE operation is complete, the bank will be in the array read mode and ready for an executable command. Erasing hardware-protected blocks also requires that the RP# pin be set to VHH prior to the third cycle (WRITE), and RP# must be held at VHH until the ERASE operation is complete (SR7 = 1). If the HCS is not completed on consecutive cycles (NOP, COMMAND INHIBIT, PRECHARGE, and REFRESH are permitted between cycles) or the bank address changes for one or more of the command cycles, the program and erase status bits (SR4 and SR5) will be set. During the SCS operation, eight commands on consecutive clock edges are required to input data to the array (NOP and COMMAND INHIBIT are permitted between cycles). See Table 2b. After the first five setup cycles, the next three cycles are identical to the normal LCR command sequence except the command for the first of last three cycles is a WRITE instead of an LCR. The ISM status bit is set on the following clock edge (subject to CAS latencies), indicating the ERASE operation is in progress. PROGRAM SEQUENCE Using an HCS operation, three commands on consecutive clock edges are required to input data to the array (NOPs and COMMAND INHIBITS are permitted between cycles). See Table 2a. In the first cycle, LOAD COMMAND REGISTER is issued with PROGRAM SETUP (40h) on A0–A7, and the bank address is issued on BA0, BA1. The next command is ACTIVE, which identifies the row address and confirms the bank address. The third cycle is WRITE, during which the column address, the bank address, and data are issued. To perform a program operation using an SCS operation, the system executes a series of WRITE op-codes using a predetermined set of address/data values (see Truth Table 2b). The SCS operation will result in the command register being loaded with the PROGRAM command (40h), and the CEL being loaded with the address and data value to be programmed. The ISM status bit will be set on the following clock edge (subject to CAS latencies). While the ISM is programming the array, the ISM status bit (SR7) will be at “0.” When the ISM status bit (SR7) is set to a logic 1, programming is complete, and the bank will be in the array read mode and ready for a new ISM operation. Programming hardware-protected blocks requires that the RP# pin be set to VHH during the FCS, and RP# must be held at VHH until the ISM PROGRAM operation is complete. The program and erase status bits (SR4 and SR5) will be set and the operation aborted if the FCS command sequence is not completed on consecutive cycles or the bank address changes for any of the 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 PROGRAM AND ERASE NVMODE REGISTER The contents of the mode register may be copied into the nvmode register with a PROGRAM NVMODE REGISTER command. Prior to programming the nvmode register, an erase nvmode register command sequence must be completed to set all bits in the nvmode register to logic 1. The command sequence necessary to execute an ERASE NVMODE REGISTER and PROGRAM NVMODE REGISTER is similar to that 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. FLASH three cycles. After the ISM has initiated programming, it cannot be aborted except by a reset or by powering down the device. Doing either while programming the array will corrupt the data being written. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY FLASH of a program sequence. See Truth Tables 2a and 2b for more information on the FCS operations necessary to complete ERASE NVMODE REGISTER and PROGRAM NVMODE REGISTER. If the device protect bit is set, RP# must be brought to VHH prior to the last FCS cycle and held at VHH until the BLOCK PROTECT or UNPROTECT ALL BLOCKS operation is complete. To check a block’s protect status, a read device configuration command sequence may be issued. BLOCK PROTECT/UNPROTECT SEQUENCE Executing a block protect sequence enables the first level of software/hardware protection for a given block. The command sequence necessary to execute a BLOCK PROTECT is similar to that of a program sequence. To provide added security against accidental block protection, three consecutive command cycles are required to initiate a BLOCK PROTECT during a normal HCS. In the first cycle, LOAD COMMAND REGISTER is issued with PROTECT SETUP (60h) on A0–A7, and the bank address of the block to be protected is issued on BA0, BA1. The next cycle is ACTIVE, which identifies a row in the block to be protected and confirms the bank address. The third cycle is WRITE, during which BLOCK PROTECT CONFIRM (01h) is issued on DQ0–DQ7, and the bank address is reissued. The ISM status bit is set on the following clock edge (subject to CAS latencies), indicating the PROTECT operation is in progress. If the LCR/ACTIVE/WRITE is not completed on consecutive cycles (NOP and COMMAND INHIBIT, REFRESH, and PRECHARGE are permitted between cycles), or the bank address changes, the write and erase status bits (SR4 and SR5) will be set and the operation will be aborted. When the ISM status bit (SR7) is set to a logic 1, the PROTECT is complete. During the SCS operation, eight commands on consecutive clock edges are required to input data to the array (NOP, COMMAND INHIBIT, REFRESH, and PRECHARGE are permitted between cycles). After the first six setup cycles, the last 2 cycles are identical to the normal HCS. The ISM status bit is set on the following clock edge (subject to CAS latencies) indicating the PROTECT operation is in progress. Once a block protect bit has been set to a “1” (protected), it can only be reset to a “0” if the UNPROTECT ALL BLOCKS command is executed. The unprotect all blocks command sequence is similar to the block protect sequence; however, in the last FCS cycle, a WRITE is issued with UNPROTECT ALL BLOCKS CONFIRM (D0h) and addresses are “Don’t Care.” For additional information, refer to Truth Tables 2a and 2b. The blocks at locations 0 and 15 have additional security. Once the block-protect bits at locations 0 and 15 have been set to a “1” (protected), each bit can only be reset to a “0” if RP# is brought to VHH prior to the third cycle (WRITE) of the UNPROTECT operation and held at VHH until the operation is complete (SR7 = 1). 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 DEVICE PROTECT SEQUENCE Executing a device protect command sequence sets the device protect bit to a “1” and prevents block protect bit modification. The command sequence necessary to execute a DEVICE PROTECT is similar to that of a PROGRAM sequence. During normal HCS operation, LOAD COMMAND REGISTER is issued in the first cycle with protect setup (60h) on A0–A7, and a bank address is issued on BA0, BA1. The bank address is “Don’t Care,” but the same bank address must be used for all three cycles. The next cycle is ACTIVE. The third cycle is WRITE, during which DEVICE PROTECT (F1h) is issued on DQ0–DQ7. RP# must be brought to VHH prior to registration of the WRITE command. During the SCS, eight commands on consecutive clock edges are required to input data to the array (NOP, COMMAND INHIBIT, REFRESH, PRECHARGE, and BURST TERMINATE are permitted between cycles). After the first five setup cycles, the last three cycles are indentical to the normal HCS, except the command for the first of the last three cycles is a WRITE instead of an LCR. The ISM status bit is set on the following clock edge (subject to CAS latencies). RP# must be held at VHH until the PROTECT operation is complete (SR7 = 1). Once the device protect bit is set, it can be reset by issuing an UNPROTECT BLOCK command with RP# = VHH. With the device protect bit set to a “1,” BLOCK PROTECT or BLOCK UNPROTECT is prevented unless RP# is at VHH during either operation. The device protect bit does not affect PROGRAM or ERASE operations. CHIP INITIALIZE SEQUENCE Executing a chip initialize sequence can be accomplished one of two ways. The first option is a hardware initiated power-up using the RP# transition to initiate a reset. A successful entry into the reset mode requires that RP# be held LOW for a minimum of 5µs before transitioning HIGH. The second option is called a software initiated power-up, which requires an INITIALIZE DEVICE FCS operation for a successful entry into reset mode. During an HCS INITIALIZE DEVICE operation, the LOAD COMMAND REGISTER command is issued in the first cycle with CHIP INITIALIZE (68h) issued on A0–A7, and a bank address issued on BA0, BA1. The 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE bank address is “Don’t Care,” but the same bank address must be used for all three cycles. The second cycle is ACTIVE, and the third cycle is WRITE, during which C0h is issued on DQ0-DQ7. Once the last command is issued, the initialization sequence will commence. During an SCS INITIALIZE DEVICE operation, eight commands on consecutive clock edges are required to input data to the array (NOP, COMMAND INHIBIT, REFRESH, PRECHARGE, and BURST TERMINATE are permitted between cycles). After the first five setup cycles, the last three cycles are identical to a typical HCS, except the command for the first of the last three cycles is a WRITE instead of an LCR. Once the last command is issued, the initialization sequence will commence. The initialization sequence is completed either by allowing a time period of 100µs to elapse or by checking for SR7 = 1. To enter this mode, RP# (reset/power-down) is taken to VSS ±0.2V. To prevent an inadvertent reset, RP# must be held at VSS for at least 5µs prior to the device entering the reset/deep power-down mode. After the device enters the reset/deep power-down mode, a transition from LOW to HIGH on RP# results in a device power-up initialization sequence as outlined in the Chip Initialization section. When the device enters the deep powerdown mode, all buffers excluding the RP# buffer are disabled and the current draw is a maximum of 50µA at 3.3V VCC. The input to RP# must remain at VSS during deep power-down. Entering the reset mode clears the status register. ERROR HANDLING After the ISM status bit (SR7) has been set, the device protect (SR3), write/protect block (SR4) and erase/ unprotect (SR5) status bits may be checked. If one or a combination of SR3, SR4, SR5 status bits has been set, an error has occurred. SR8 is set when an inadvertent power failure occurs during device initialization. The device should be reinitialized to ensure proper device operation. The ISM cannot reset SR3, SR4, SR5, or SR8. To clear these bits, CLEAR STATUS REGISTER command must be given. Table 6 lists the combination of errors. DISABLE LCR SEQUENCE In some systems the SDRAM controller does not support the generation of the LCR command. These systems will likely find that the SCS is more practical for performing Flash operations. The DISABLE LCR command can be issued with either an HCS or SCS operation. Once issued, the DISABLE LCR bit will no longer allow HCS operations. Note that unless DISABLE LCR is issued, the device can function in either HCS or SCS mode. PROGRAM/ERASE CYCLE ENDURANCE SyncFlash memory is designed and fabricated to meet advanced code and data storage requirements. Operation outside specification limits may reduce the number of PROGRAM and ERASE cycles that can be performed on the device. Each block is designed and processed for a minimum of 100,000-PROGRAM/ ERASE-cycle endurance. RESET/DEEP POWER-DOWN MODE To allow for maximum power conservation, the device features a very low current, deep power-down mode. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. FLASH 64Mb: x16, x32 SYNCFLASH MEMORY ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY Table 4 Status Register Bit Definition1 R VPS ISMS R ES WS DPS BISMS DBS 15–9 8 7 6 5 4 3 2–1 0 FLASH STATUS BIT # STATUS REGISTER BIT SR15– SR9 DESCRIPTION RESERVED Reserved for future use. SR8 VCC POWER SEQUENCE STATUS (VPS) 1 = Power-up incomplete error 0 = Power-up complete VPS is set if there has been a power disruption that may result in undefined device operation. A VPS error is only cleared by re-initializing the device. SR7 ISM STATUS (ISMS) 1 = Ready 0 = Busy The ISMS bit displays the active status of the state machine when performing PROGRAM, BLOCK ERASE or CHIP INITIALIZE. The controlling logic polls this bit to determine when the erase and program status bits are valid. This bit can be monitored to determine the completion of power-up initialization after CHIP INITIALIZATION sequence is issued. SR6 RESERVED Reserved for future use. SR5 ERASE/UNPROTECT BLOCK STATUS (ES) 1 = BLOCK ERASE or BLOCK UNPROTECT error 0 = Successful BLOCK ERASE or UNPROTECT ES is set to “1” after the maximum number of ERASE cycles is executed by the ISM without a successful verify. This bit is also set to “1” if a BLOCK UNPROTECT operation is unsuccessful. ES is only cleared by a CLEAR STATUS REGISTER command or by a RESET. SR4 PROGRAM/PROTECT BLOCK STATUS (WS) WS is set to “1” after the maximum number of PROGRAM cycles 1 = PROGRAM or BLOCK PROTECT error is executed by the ISM without a successful verify. This bit is also 0 = Successful BLOCK ERASE or set to “1” if a BLOCK or DEVICE PROTECT operation is UNPROTECT unsuccessful. WS is only cleared by a CLEAR STATUS REGISTER command or by a RESET. SR3 DEVICE PROTECT STATUS (DPS) 1 = Device protected, invalid operation attempted 0 = Device unprotected or RP# condition met DPS is set to “1” if an invalid PROGRAM, ERASE, PROTECT BLOCK, PROTECT DEVICE or UNPROTECT ALL BLOCKS is met. After one of these commands is issued, the condition of RP#, the block protect bit and the device protect bit are compared to determine if the desired operation is allowed. Must be cleared by CLEAR STATUS REGISTER or by a RESET. SR2 SR1 BANKA1 ISM STATUS (BISMS) BANKA0 ISM STATUS When SR0 = 0, the bank under ISM control can be decoded from SR1, SR2: [0,0] Bank 0; [0,1] Bank 1; [1,0] Bank 2; [1,1] Bank 3. SR1, SR2 is valid when SR7 = 0. When SR7 = 1, SR1, SR2 is reset to “0.” SR0 DEVICE/BANK ISM STATUS (DBS) 1 = Device-level ISM operation 0 = Bank-level ISM operation DBS is set to “1” if the ISM operation is a device-level operation. A valid READ to any bank can immediately follow the registration of an ISM PROGRAM operation. When DBS is set to “0,” the ISM operation is a bank-level operation. A READ to the bank under ISM control will output the contents of the row activated prior to the FCS. SR1 and SR2 can be decoded to determine which bank is under ISM control. SR0 is used in conjuction with SR7, and is valid when SR7 = 0. When SR7 = 1, SR0 is reset to “0.” NOTE: 1. SR3–SR5 must be cleared with CLEAR STATUS REGISTER prior to initiating an ISM WRITE operation for the status bits to be valid. 2. x32: SR32-SR16 is a copy of SR15-SR0. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY Table 5 Device Configuration Manufacturer Compatibility ID Device ID CONFIGURATION ADDRESS DATA CONDITION 000h xx2Ch Manufacturer compatibility ID read 1 x32: 001h xxD4h Device ID read 1 x16: 001h xxD5h Device ID read 1 NOTES Block Protect Bit x02h x02h DQ0 = 1 DQ0 = 0 Block protected Block unprotected Device Protect Bit 003h 003h DQ0 = 1 DQ0 = 0 Block protect modification prevented Block protect modification enabled 3 Mode Register 004h Mode register definition data 4 Hardware LCR Disable 005h 005h DQ0 = 1 DQ0 = 0 Hardware LCR is disabled Hardware LCR is enabled 2, 3 3, 5 NOTE: 1. DQ8–DQ15 are “Don’t Care.” For x32, DQ31–DQ16 are a copy of DQ15–DQ0. 2. Address to read block protect bit is always the third location within each block. x32: X = 0, 2, 4, 6h; BA0, BA1 required. x16: X = 0, 4, 8, Ch; BA0, BA1 required. 3. DQ1–DQ7 are reserved, DQ8–DQ15 are “Don’t Care.” For x32, DQ31–DQ16 are a copy of DQ15–DQ0. 4. See Figure 1 for more information. 5. Factory preset is “0.” 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. FLASH DEVICE CONFIGURATION ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY FLASH Table 6 Status Register Codes1 STATUS REGISTER CODE SR8 000h 0 001h 0 SR7 0 0 SR6 0 0 SR5 0 0 SR4 0 0 SR3 0 0 SR2 0 0 SR1 0 0 002h 003h 004h 005h 006h 007h 010h 011h 012h 013h 014h 015h 016h 020h 021h 022h 023h 024h 025h 026h 080h 090h 098h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 0 0A0h 0A8h 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 0 0B0h 0B8h 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 0 1xxh 1 X X X X X X X SR0 STATE MACHINE DESCRIPTION 0 Busy – ERASE or PROGRAM cycle for Bank 0 1 Busy – BLOCK PROTECT or UNPROTECT cycle 0 Busy – ERASE or PROGRAM cycle for Bank 1 1 Busy – DEVICE PROTECT cycle 0 Busy – ERASE or PROGRAM cycle for Bank 2 1 Busy – NVMODE ERASE or PROGRAM cycle 0 Busy – ERASE or PROGRAM cycle for Bank 3 1 Busy – INITIALIZATION cycle 0 Busy – PROGRAM cycle error for Bank 0 1 Busy – BLOCK PROTECT cycle error 0 Busy – PROGRAM cycle error for Bank 1 1 Busy – DEVICE PROTECT cycle error 0 Busy – PROGRAM cycle error for Bank 2 1 Busy – NVMODE PROGRAM cycle error 0 Busy – PROGRAM cycle error for Bank 3 0 Busy – ERASE cycle error for Bank 0 1 Busy – BLOCK UNPROTECT cycle error 0 Busy – ERASE cycle error for Bank 1 1 Busy – DEVICE UNPROTECT cycle error 0 Busy – ERASE cycle error for Bank 2 1 Busy – NVMODE ERASE cycle error 0 Busy – ERASE cycle error for Bank 3 0 Ready – No errors 0 Ready – PROGRAM or PROTECT cycle error 0 Ready – Program/protect error and device/ block protection error 0 Ready – ERASE or UNPROTECT cycle error 0 Ready – Erase/unprotect error and device/ block protection error 0 Ready – Command sequence error 0 Ready – Command sequence error and device/block protection error X VCC error (power-up without initialization error) NOTE: 1. SR3–SR5 must be cleared using CLEAR STATUS REGISTER. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY SELF-TIMED PROGRAM SEQUENCE1 COMPLETE PROGRAM STATUS-CHECK SEQUENCE Start (PROGRAM completed) FCS Command Sequence 2 SR4, SR5 = 1? YES Command Sequence Error 5 NO Read Status Register Polling SR3 = 1? YES Invalid PROGRAM Error 5 NO SR7 = 1? NO SR4 = 1? YES PROGRAM Error 5 NO YES PROGRAM Successful Complete Status Check 3 PROGRAM Complete4 NOTE: 1. 2. 3. 4. 5. Sequence may be repeated for multiple PROGRAMs. FCS includes HCS and SCS. Complete status check is not required. The bank will be in array read mode. SR3–SR5 must be cleared using CLEAR STATUS REGISTER. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. FLASH Start ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY FLASH SELF-TIMED BLOCK ERASE SEQUENCE1 COMPLETE BLOCK ERASE STATUS-CHECK SEQUENCE Start Start (BLOCK ERASE completed) FCS Command Sequence 2, 3 SR4, SR5 = 1? YES Command Sequence Error 6 YES Invalid ERASE or UNPROTECT Error 6 YES BLOCK ERASE or UNPROTECT Error 6 NO Read Status Register SR3 = 1? NO SR7 = 1 NO SR5 = 1? NO YES Complete Status Check 4 ERASE or BLOCK UNPROTECT Successful ERASE Complete 5 NOTE: 1. 2. 3. 4. 5. 6. Sequence may be repeated to erase multiple blocks. FCS includes HCS and SCS. RP# can be brought to VHH before the last command in the erase sequence is issued. Complete status check is not required. The bank will be in the array read mode. SR3–SR5 must be cleared using CLEAR STATUS REGISTER. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY BLOCK PROTECT SEQUENCE1 Start Start (BLOCK PROTECT completed) FCS Command Sequence2, 3 SR4 = 1? YES BLOCK or DEVICE PROTECT Error 6 YES Command Sequence Error 6 YES Invalid BLOCK/DEVICE PROTECT Error 6 NO SR4, SR5 = 1? Read Status Register NO SR7 = 1 SR3 = 1? NO NO YES BLOCK PROTECT Successful Complete Status Check DEVICE PROTECT Complete4, 5 NOTE: 1. 2. 3. 4. 5. 6. Sequence may be repeated for multiple BLOCK PROTECTs. FCS includes HCS and SCS. RP# can be brought to VHH before the last command in the block protect sequence is issued. Complete status check is not required. The bank will be in array read mode. SR3–SR5 must be cleared using CLEAR STATUS REGISTER. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. FLASH COMPLETE BLOCK PROTECT STATUS-CHECK SEQUENCE ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY DEVICE PROTECT SEQUENCE1 COMPLETE BLOCK STATUS-CHECK SEQUENCE Start Start YES FLASH FCS Command Sequence2, 3 Device Protected? NO Unprotect Blocks 1-14? Read Status Register YES NO SR7 = 1 NO RP# = VHH YES FCS Command Sequence 2 Complete Status Check Read Status Register DEVICE PROTECT Complete4, 5 SR7 = 1 NO YES Complete Status Check 4, 5 ALL BLOCKS UNPROTECT Complete NOTE: 1. 2. 3. 4. 5. Once the device protect bit is set, it can be reset. FCS includes HCS and SCS. RP# can be brought to VHH before the last command in the device protect sequence is issued. Complete status check is not required. A subsequent WRITE command may be issued. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY COMPLETE DEVICE PROTECT STATUS-CHECK SEQUENCE SR4 = 1? YES BLOCK or DEVICE PROTECT Error 1 YES Command Sequence Error 1 YES Invalid BLOCK/DEVICE PROTECT Error 1 NO SR4, SR5 = 1? NO SR3 = 1? NO DEVICE PROTECT Successful NOTE: 1. SR3–SR5 must be cleared using CLEAR STATUS REGISTER. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. FLASH Start (DEVICE PROTECT completed) ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FLASH ABSOLUTE MAXIMUM RATINGS* Voltage on RP# Relative to VSS ...................... -1V to +9V Voltage on VCC, VCCP, or VCCQ Supply, Inputs, or I/Os Relative to VSS ........................ -1V to +2.45V Operating Temperature, TA (ambient) ..................................... -40ºC to +85ºC Storage Temperature (plastic) ........... -55ºC to +150ºC Power Dissipation ........................................................ 1W Short Circuit Output Current ................................ 50mA DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS1, 2 Commercial Temperature (-40ºC £ TA £ +85ºC); VCC = 3.0V–3.6V; VCCQ = 1.65V–1.95V PARAMETER/CONDITION SYMBOL MIN MAX UNIT VCC 3.0 3.6 V VCCQ 1.65 1.95 V HARDWARE PROTECTION VOLTAGE (RP# only) VHH 7.0 8.5 V INPUT HIGH VOLTAGE: Logic 1; All Inputs VIH 0.8 × VCCQ VCCQ + 0.4 V INPUT LOW VOLTAGE: Logic 0; All Inputs VIL -0.3 0.3 V IL -2 2 µA OUPUT LEAKAGE CURRENT: DQs are disabled; 0V £ VOUT £ VCCQ IOZ -5 5 µA OUTPUT HIGH VOLTAGE: IOUT = -100µA VOH VCCQ - 0.2 – V OUTPUT LOW VOLTAGE: IOUT = 100µA VOL – 0.2 V VCC SUPPLY VOLTAGE VCCQ SUPPLY VOLTAGE INPUT LEAKAGE CURRENT: Any input 0V £ VIN £ VCC (All other pins not under test = 0V) NOTE: 1. All voltages referenced to VSS. 2. An initial pause of 100µs is required after power-up. (VCC, VCCP, and VCCQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY ICC SPECIFICATIONS AND CONDITIONS (Notes: 1, 2, 3); Extended Temperature (-40ºC £ TA £ +85ºC); VCC = 3.0V–3.6V; VCCQ = 1.65V–1.95V PARAMETER/CONDITION SYMBOL MAX -10 TYP MAX TYP UNITS NOTES VCC OPERATING CURRENT: READ Operation; Burst Mode All banks active; READ; CAS latency = 3 ICCR 125 120 mA 4, 5, 6 VCC OPERATING CURRENT: ACTIVE Operation All banks active VCC STANDBY CURRENT: Active Mode; CKE = HIGH; Burst in progress ICCA 100 95 mA 4 ICCS1 10 10 mA VCC STANDBY CURRENT: Power-Down Mode; CKE = LOW; No burst in progress ICCS2 2 2 mA VCC STANDBY CURRENT: Clock-Quiet Mode; CLK = CKE = LOW ICCS3 200 200 µA VCC DEEP POWER-DOWN CURRENT: RP# = VSS ±0.2V or DEEP POWER-DOWN Command ICCDP 200 50 µA PROGRAM CURRENT ICCW + IPPW 55 55 mA VCCP ERASE CURRENT IPPE 80 80 mA VCCP CURRENT: Standby; Power-Down; Deep Power-Down IPPS 1 1 µA MAX UNITS NOTES CAPACITANCE PARAMETER SYMBOL TYP Input Capacitance: CLK CI1 2.5 4.0 pF 7 Input Capacitance: All other input-only pins CI2 2.5 5.0 pF 7 Input/Output Capacitance: DQs CIO 4.0 6.5 pF 7 NOTE: 1. All voltages referenced to VSS. 2. An initial pause of 100µs is required after power-up. (VCC, VCCP, and VCCQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) 3. ICC specifications are tested after the device is properly initialized. 4. ICC is dependent on output loading and cycle rates. Specified values are obtained with the outputs open. 5. The ICC current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS latency is reduced. 6. Address transitions average one transition every 30ns. 7. This parameter is sampled. VCC = VCCQ; f = 1 MHz, TA = +25ºC. 8. Typical conditions: +25oC, burst length = 8, tRC = 140ns. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. FLASH -8 ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 1, 2, 3, 4, 5); Extended Temperature (-40ºC £ TA £ +85ºC); VCC = 3.0V–3.6V; VCCQ = 1.65V–1.95V FLASH AC CARACTERISTICS PARAMETER Access time from CLK (pos. edge) -8 CL = 3 CL = 2 CL = 1 Address hold time Address setup time CLK high level width CLK low level width Clock cycle time CL = 3 CL = 2 CL = 1 CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time CL = 3 CL = 2 CL = 1 Data-out low-impedance time Data-out hold time ACTIVE command period ACTIVE to READ or WRITE delay ACTIVE bank A to ACTIVE bank B command Transition time SYM tAC tAC tAC tAH tAS tCH tCL tCK tCK tCK tCKH tCKS tCMH tCMS tDH tDS tHZ tHZ tHZ tLZ tOH tRC tRCD tRRD tT MIN -10 MAX 7 8 19 1 2 3 3 8 10 20 1 2 1 2 1 2 MIN 1 2 3 3 10 12 25 1 2 1 2 1 2 7 8 19 1 3 60 24 24 0.3 MAX 7 8 22 1.2 7 8 22 1 3 60 30 30 0.3 1.2 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 6 6 6 7 NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 2. An initial pause of 100µs is required after power-up. (VCC, VCCP, and VCCQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) 3. In addition to meeting the transition rate specification, the clock and CKE must transit between V IH and VIL (or between VIL and VIH) in a monotonic manner. 4. Outputs measured at 0.8V with equivalent load: x32 x16 Q Q 50pF 30pF 5. AC timing and ICC tests have VIL = 0V and VIH = 1.6V, with timing referenced to 0.8V crossover point. 6. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 7. AC characteristics assume tT = 1ns. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY AC FUNCTIONAL CHARACTERISTICS PARAMETER READ/WRITE to READ/LOAD COMMAND REGISTER command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command Data-in to ACTIVE TERMINATE command LOAD MODE REGISTER command to ACTIVE command Data-out to High-Z from ACTIVE TERMINATE command CL = 3 CL = 2 CL = 1 SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tMRD tROH tROH tROH -8 1 1 1 0 0 2 0 5 2 2 3 2 1 -10 1 1 1 0 0 2 0 5 2 2 3 2 1 UNITS tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK NOTES 7 8 8 7 7 7 7 7 7 7 NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 2. An initial pause of 100µs is required after power-up. (VCC, VCCP, and VCCQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) 3. AC characteristics assume tT = 1ns. 4. In addition to meeting the transition rate specification, the clock and CKE must transit between V IH and VIL (or between VIL and VIH) in a monotonic manner. 5. Outputs measured at 0.8V with equivalent load: x32 x16 Q Q 30pF 50pF 6. AC timing and ICC tests have VIL = 0V and VIH = 1.6V, with timing referenced to 0.8V crossover point. 7. Required clocks specified by JEDEC functionality and not dependent on any timing parameter. 8. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. FLASH (Notes: 1-6); Extended Temperature (-40ºC £ TA £ +85ºC); VCC = 3.0V–3.6V; VCCQ = 1.65V–1.95V ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY INITIALIZE AND LOAD MODE REGISTER (RP# CONTROL) Ta CLK tCKS tCKH (( )) (( )) COMMAND (( )) (( )) (( )) (( )) DQM (( )) (( )) (( )) (( )) (( )) (( )) VCC, VCCP, VCCQ Tn (( )) (( )) (( )) (( )) CKE FLASH Tm (( )) (( )) Tn + 1 tCK Tn + 2 tCL Tn + 3 tCH tCMH tCMS LOAD MODE REGISTER ACTIVE NOP (( )) RP#1 (( )) tAS ADDRESS (( )) (( )) DQ (( )) (( )) (( )) High-Z tAH OPCODE ROW (( )) tMRD T = 100µs 3, 4, 5 2 Power-up: VCC, VCCP, VCCQ, CLK stable Load Mode Register DON’T CARE UNDEFINED TIMING PARAMETERS -8 SYMBOL* tAH tAS tCH tCL tCK(3) tCK(2) MIN 1 2 -10 MAX MIN 1 2 MAX -8 UNITS ns ns SYMBOL* tCK(1) tCKH 3 3 3 3 ns ns tCKS 8 10 10 12 ns ns tCMS tCMH tMRD MIN – 1 -10 MAX MIN – 1 MAX UNITS ns ns 2 1 2 1 ns ns 2 2 2 2 tCK ns *CAS latency indicated in parentheses. NOTE: 1. RP# = VCC or VHH 2. VCC = 3.3V, VCCP = 3.3V, VCCQ = 1.8V 3. The nvmode register contents are automatically loaded into the mode register upon power-up initialization, LOAD MODE REGISTER cycle is required to enter new mode register values. 4. JEDEC and PC100 specify three clocks. 5. If CS is HIGH at clock time, all commands applied are NOP, with CKE a “Don’t Care.” 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY INITIALIZE AND LOAD MODE REGISTER (FCS CONTROL) Ta CLK tCKS tCKH (( )) (( )) Tm (( )) (( )) (( )) (( )) CKE (( )) (( )) DQM (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) RP#1 WRITE tCMH High-Z DQ (( )) tCMS LOAD MODE REGISTER tAS ADDRESS Tn + 3 tCL tCH (( )) (( )) 6 Tn + 2 Tn + 1 tCK (( )) (( )) COMMAND VCC, VCCP, VCCQ Tn NOP ACTIVE tAH OPCODE ROW (( )) C0h tMRD T = 100µs Load Mode Register 3, 4, 5 Power-up:2 VCC, VCCP, VCCQ, CLK stable DON’T CARE UNDEFINED TIMING PARAMETERS -8 SYMBOL* tAH MIN MAX MIN -10 MAX -8 UNITS SYMBOL* tCK(1) tCKH tCKS MIN – 1 2 MAX MIN – 1 2 -10 MAX UNITS ns ns ns 1 2 3 1 2 3 ns ns ns 3 8 3 10 ns ns tCMH tCK(3) tCMS 1 2 1 2 ns ns tCK(2) 10 12 ns tMRD 2 2 tCK tAS tCH tCL *CAS latency indicated in parentheses. NOTE: 1. RP# = VCC or VHH 2. VCC = 3.3V, VCCP = 3.3V, VCCQ = 1.8V 3. The nvmode register contents are automatically loaded into the mode register upon power-up initialization, LOAD MODE REGISTER cycle is required to enter new mode register values. 4. JEDEC and PC100 specify three clocks. 5. If CS is HIGH at clock time, all commands applied are NOP, with CKE a “Don’t Care.” 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY CLOCK SUSPEND MODE1 T0 T1 T2 tCK CLK T3 T4 T5 tCL tCH tCKS tCKH CKE tCKS tCKH tCMS tCMH COMMAND READ NOP tCMS NOP NOP NOP NOP tCMH DQM tAS x32: A0–A10 x16: A0–A11 tAH COLUMN m2 tAS BA tAH BANK tAC tOH tAC DQ tHZ DOUT m tLZ DOUT m+1 DON’T CARE UNDEFINED TIMING PARAMETERS -8 SYMBOL* tAC(3) MIN tAC(2) tAS tCH tCL tCK(3) tCK(2) tCK(1) tCKH MIN 8 – tAC(1) tAH MAX 7 -10 MAX 7 8 – -8 SYMBOL* tCKS tCMH tCMS UNITS ns ns ns 1 2 3 1 2 3 ns ns ns tDH 3 8 3 10 ns ns tHZ(2) 10 – 1 12 – 1 ns ns ns tLZ tDS MIN 2 1 2 1 2 tHZ(3) MIN 2 1 2 1 3 -10 MAX 1 2 7 8 – tHZ(1) tOH MAX ns ns 7 8 – 1 3 UNITS ns ns ns ns ns ns ns ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 2, CAS latency = 3. 2. A0–A7 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY READ1 T0 T1 T2 tCK CLK tCKS T3 T4 T5 T6 T7 T8 NOP ACTIVE tCL tCH tCKH CKE tCMS tCMH COMMAND ACTIVE NOP READ NOP NOP NOP NOP tCMS tCMH DQM tAS x32: A0–A10 x16: A0–A11 ROW tAS BA tAH COLUMN m2 ROW BANK BANK tAH BANK tAC tAC DQ DOUT m tLZ tRCD tAC tOH tAC tOH tOH tOH DOUT m+1 DOUT m+2 DOUT m+3 tHZ CAS Latency tRC DON’T CARE UNDEFINED TIMING PARAMETERS -8 SYMBOL* tAC(3) tAC(2) tAC(1) tAH tAS tCH tCL tCK(3) tCK(2) tCK(1) MIN MAX 7 8 – MIN -10 MAX 7 8 – -8 SYMBOL* tCKH tCKS tCMH UNITS ns ns ns 1 2 3 1 2 3 ns ns ns tCMS 3 8 3 10 ns ns tRC 10 – 12 – ns ns MIN 1 2 1 MAX MIN 1 2 1 -10 MAX UNITS ns ns ns 2 1 2 1 ns ns tRCD 3 60 24 3 60 30 ns ns ns tRRD 24 30 ns tLZ tOH *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4, CAS latency = 2. 2. A0–A7. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY READ – ALTERNATING BANK READ ACCESSES1 T0 T1 T2 tCK CLK T3 T4 T5 NOP ACTIVE T6 T7 T8 READ NOP ACTIVE tCL tCH tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE NOP READ NOP tCMS tCMH DQM tAS x32: A0–A10 x16: A0–A11 ROW tAS BA tAH COLUMN m2 ROW COLUMN b2 ROW BANK 0 BANK 1 BANK 1 BANK 0 tAH BANK 0 tAC tOH tAC DQ DOUT m tLZ tRCD - BANK 0 tAC tOH DOUT m+1 tAC tOH tAC tOH DOUT m+2 tAC tOH DOUT m+3 DOUT b tRCD - BANK 0 CAS Latency - BANK 0 tRC - BANK 0 tRCD - BANK 1 tRRD CAS Latency - BANK 1 DON’T CARE UNDEFINED TIMING PARAMETERS -8 SYMBOL* tAC(3) MIN tAC(2) -8 -10 MAX 7 MIN 8 – SYMBOL* tCKH MAX 7 UNITS ns 8 – tCKS UNITS ns 2 1 3 2 1 3 ns ns ns tRCD 60 24 60 30 ns ns tRRD 24 30 ns 1 1 2 3 2 3 ns ns tLZ 3 10 12 ns ns ns tRC tCK(2) 3 8 10 tCK(1) – – ns tCK(3) MAX ns ns tAS tCL MIN 1 2 1 tAH tCH -10 MAX 2 1 ns ns ns tAC(1) MIN 1 tCMH tCMS tOH *CAS latency indicated in parentheses. NOTE: 1. For this example, CAS latency = 2. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY READ – FULL-PAGE BURST1 T0 T1 T2 tCL CLK T3 T4 T5 T6 (( )) (( )) tCK tCH tCKS ACTIVE NOP READ NOP NOP NOP NOP tCMS tCMH Tn + 4 tAS tAH ROW tAS (( )) (( )) COLUMN m2 (( )) (( )) BANK (( )) (( )) tAH BANK NOP BURST TERM NOP NOP (( )) (( )) DQM BA Tn + 3 (( )) (( )) tCMS tCMH x32: A0–A10 x16: A0–A11 Tn + 2 tCKH CKE COMMAND Tn + 1 tAC tAC tAC tOH OH DOUT m DQ DOUT m+1 tLZ tAC ( ( tOH ) ) (( )) DOUT m+2 (( )) tAC tAC tOH tOH DOUT m-1 tOH DOUT m DOUT m+1 tHZ 256 (x16), 128 (x32) locations within the same row. tRCD Full page completed. Full-page burst does not self-terminate. Can use BURST TERMINATE command. CAS Latency DON’T CARE UNDEFINED TIMING PARAMETERS -8 SYMBOL* tAC(3) tAC(2) MIN tAC(1) MAX 7 8 MIN -10 MAX 7 8 2 1 tCMS 2 1 1 tAS 2 3 3 2 3 3 ns ns ns tHZ(3) 10 12 ns ns tLZ tCK(2) 8 10 tCK(1) – – ns tRCD tCK(3) MIN 1 tCMH tAH tCL – tCKS ns ns tCH – -8 SYMBOL* tCKH UNITS ns ns MIN 1 tHZ(1) -10 MAX 2 1 7 8 – UNITS ns ns ns 2 7 8 tHZ(2) tOH MAX – ns ns ns 1 1 ns ns 3 24 3 30 ns ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the CAS latency = 2. 2. A0–A7. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY READ – DQM OPERATION1 T0 T1 T2 tCK CLK tCKS T3 T4 T5 NOP NOP T6 T7 T8 NOP NOP NOP tCL tCH tCKH CKE tCMS tCMH COMMAND ACTIVE NOP READ NOP tCMS tCMH DQM tAS x32: A0–A10 x16: A0–A11 COLUMN m2 ROW tAS BA tAH tAH BANK BANK tAC DQ tOH DOUT m tLZ tRCD tAC tHZ tAC tOH tOH DOUT m+2 DOUT m+3 tLZ tHZ CAS Latency DON’T CARE UNDEFINED TIMING PARAMETERS -8 SYMBOL* MIN tAC(3) tAC(1) tAS tCH tCL tCK(3) tCK(2) tCK(1) MIN 7 8 – tAC(2) tAH MAX -10 MAX 7 8 – -8 SYMBOL* tCKH UNITS ns ns ns 1 2 1 2 ns ns 3 3 8 3 3 10 ns ns ns 10 – 12 – ns ns tCKS tCMH tCMS MIN 1 2 1 2 tHZ(3) tHZ(1) tOH tRCD MIN 1 -10 MAX 2 1 2 7 8 tHZ(2) tLZ MAX – UNITS ns ns ns ns 7 8 ns ns – 1 3 1 3 ns ns ns 24 30 ns *CAS latency indicated in parentheses. NOTE: 1. For this example, the burst length = 4, CAS latency = 2. 2. A0–A7. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 54 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 PROGRAM/ERASE1 (Bank a followed by READ to Bank a) T0 T1 T2 T3 tCK CLK tCKS tCKH tCMS tCMH T4 tCL T5 T6 T7 T8 NOP NOP NOP T9 tCH CKE COMMAND LCR ACTIVE NOP WRITE READ NOP NOP tCMS tCMH DQM tAS x32: A0–A10 x16: A0–A11 BA COMCODE2 BANK a tAH 3 ROW COLUMN m COLUMN n BANK a BANK a BANK a 55 tDS tDH tDS High-Z DIN4 m DQ tDH Dout n+1 Dout n tRCD DON’T CARE UNDEFINED -8 SYMBOL* tAH tAS tCH tCL tCK(3) tCK(2) MIN 1 2 3 3 8 10 MAX MIN 1 2 3 3 10 12 -10 MAX -8 UNITS ns ns ns ns ns ns SYMBOL* tCK(1) tCKH tCKS tCMH tCMS tMRD MIN – 1 2 1 2 2 MAX MIN – 1 2 1 2 2 -10 MAX UNITS ns ns ns ns ns tCK *CAS latency indicated in parentheses. ADVANCE NOTE: 1. ACTIVE/READ or READ will output the contents of the row activated prior to the LCR/active/write command sequence. This example illustrates the timing for activating a new row in bank a. For this example, READ burst length = 2, CAS latency = 2. 2. ComCode = 40h for PROGRAM, 20h for ERASE (see Truth Table 2). 3. LCR/ACTIVE cycles must be initiated prior to READ according to Truth Table 2 for a status register read command sequence. 4. Column address is “Don’t Care” for ERASE operation. 5. DIN = D0h (erase confirm) for ERASE operation. 64Mb: x16, x32 SYNCFLASH MEMORY Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. TIMING PARAMETERS ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY PROGRAM/ERASE1 (Bank a followed by READ to Bank b) T0 T1 T2 T3 t CK CLK T4 t CL T5 T6 T7 T8 NOP NOP NOP T9 t CH t CKS t CKH CKE tCMS tCMH COMMAND LCR ACTIVE NOP WRITE READ NOP NOP t CMS t CMH DQM t AS x32: A0-A10 x16: A0-A11 BA COMCODE2 BANK a t AH ROW COLUMN3 m COLUMN n BANK a BANK a BANK b t DS t DH t DS DOUT n DIN4 m DQ t DH High-Z DOUT n + 1 t RCD DON’T CARE UNDEFINED TIMING PARAMETERS -8 SYMBOL* tAH tAS tCH MIN 1 2 3 tCL tCK(3) tCK(2) MAX MIN 1 2 3 -10 MAX -8 UNITS ns ns ns SYMBOL* tCK(1) tCKH tCKS MIN – 1 2 MAX MIN – 1 2 -10 MAX UNITS ns ns ns 3 3 ns tCMH 1 1 ns 8 10 10 12 ns ns tCMS 2 2 2 2 tCK tMRD ns *CAS latency indicated in parentheses. NOTE: 1. 2. 3. 4. For this example, READ burst length = 2, CAS = 3. ComCode = 40h for WRITE, 20h for ERASE (see Truth Table 2). Column address is “Don’t Care” for ERASE operation. DIN = D0h (erase confirm) for ERASE operation. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 56 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY 90-BALL FBGA .850 ±.075 .10 C SEATING PLANE C SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb. Or 62% Sn, 36% Pb, 2% Ag SOLDER BALL PAD: Ø .33mm 11.00 ±.10 90X Ø 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0.40mm PIN A1 ID 6.40 .80 TYP SUBSTRATE: PLASTIC LAMINATE ENCAPSULATION MATERIAL: EPOXY NOVOLAC PIN A1 ID BALL A9 BALL A1 6.50 ±.05 13.00 ± .10 CL 11.20 .80 TYP 5.60 ±.05 CL 3.20 ±.05 1.20 MAX 5.50 ±.05 NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. DATA SHEET DESIGNATION Advance: This data sheet contains initial descriptions of products still under development. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and SyncFlash are registered trademarks, and the Micron logo is a trademark of Micron Technology, Inc. 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 57 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. ADVANCE 64Mb: x16, x32 SYNCFLASH MEMORY REVISION HISTORY Original document, Rev. 1, Advance .................................................................................................................. 4/02 64Mb: x16, x32 SyncFlash MT28S4M16B1LL.p65 – Rev. 1, Pub. 5/02 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc.