TI TPS65193

TPS65193
www.ti.com ....................................................................................................................................................................................................... SLVS964 – JULY 2009
Dual High-Voltage Scan Driver for TFT-LCD
FEATURES
1
•
•
•
•
•
•
APPLICATIONS
Dual High-Voltage Scan Driver
Scan Driver Output Charge Share
High Output-Voltage Level: Up to 35 V
Low Output-Voltage Level: Down to –28 V
Logic-Level Inputs
24-Pin 4-mm × 4-mm QFN package
•
TFT LCD Using Amorphous Silicon Gate (ASG)
Technology
DESCRIPTION
CKV1 to ASG
The TPS65193 is dual high-voltage scan driver to drive an amorphous-silicon-gate (ASG) circuit on TFT glass.
Each single high-voltage scan driver receives logic-level inputs of CPVx and generates two high-voltage outputs
of CKVx and CKVBx. The device receives a logic-level input of STV and generates a high-voltage output of
STVP. These outputs are swings from Voff (–28 V) to Von (35 V) and are used to drive the ASG circuit and
charge/discharge the capacitive loads of the TFT LCD. In order to reduce the power dissipation of the device, a
charge-share function is implemented. The device features a discharge function, which shorts Voff to GND in
order to shut down the panel faster when the LCD is turned off.
RBCS1
19
VON
20
NC
21
AGND
22
CKV1
23
DISH
CKVCS2
AGND
17
CVOFF
Vlogic
16
15
CDISH
14
13
12
STV from T-CON 7
18
DLY
NC
EN
CKV2
11
6
CKVBCS2
STV
CKV2 to ASG
NC
EN
5
RCS2
CKVB2
NC
4
NC
10
RBCS2
STVP
CPV2
3
VOFF
CPV2 from T-CON 9
CKVB2 to ASG
VOFF
CKVB1
CPV1
2
CKVCS1
24
STVP to ASG
CKVBCS1
1
CVON
RCS1
CPV1 from T-CON 8
CKVB1 to ASG
VON
CDLY
S0418-01
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPS65193
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
(1)
TA
ORDERING P/N
PACKAGE
PACKAGE MARKING
–40°C to 85°C
TPS65193RGE
24-Pin 4-mm x 4-mm QFN
TPS65193
The RGE package is available taped and reeled and shipped in quantities of 2500 devices per reel.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
Voltage on pins CPVx, STV
–0.3 to 5.5
V
Voltage on pins EN
–0.3 to 5.5
V
Input voltage on VON (2)
37
V
Input voltage on VOFF (2)
–30
V
–30 to 37
V
Voltage on CKVx, CKVBx, CKVCSx, CKVBCSx
VON–VOFF
62
V
Voltage on STVP
–30 to 37
V
Voltage on DISH
–3.6 to 5.5
V
ESD rating HBM
2
kV
ESD rating MM
200
V
ESD rating CDM
700
V
Continuous power dissipation
See Dissipation Ratings table
Operating junction temperature range
–40 to 150
°C
Storage temperature range
–65 to 150
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS
PACKAGE
RθJA
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
24-pin 4-mm x 4-mm QFN
88°C/ W (Low-K board)
1.13 W
0.62 W
0.45 W
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
VON
Positive high-voltage range
15
35
V
VOFF
Negative low-voltage range
–28
–3
V
VON-VOFF
VON to VOFF voltage range
fCPV
CPV input frequency
TA
Operating ambient temperature
TJ
Operating junction temperature
2
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60
V
150
kHz
–40
85
°C
–0
125
°C
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ELECTRICAL CHARACTERISTICS
VOFF = –10 V, VON = 30 V, EN = 3.3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
600
800
120
200
520
800
260
400
UNIT
SUPPLY CURRENT
IQIN
ISD
Quiescent current into VON
CPVx = GND, STV = 3.3 V
Quiescent current out of VOFF
CPVx = GND, STV = 3.3 V
EN = GND
Shutdown current into VON
Shutdown current out of VOFF
µA
µA
UNDERVOLTAGE LOCKOUT
VUVLO
VON rising
Undervoltage lockout threshold on VON
10
Hysteresis
13
250
V
mV
LOGIC SIGNALS EN, CPVx, STV
VIH
High-level input voltage of CPVx, STV, EN
VIL
Low-level input voltage of CPVx, STV, EN
2
V
0.5
V
OUTPUT CKVx, CKVBx, STVP, CKVCSx
VOH
VOL
RCHSH
Output high voltage of CKVx, CKVBx
Output high voltage of STVP
Output low voltage of CKVx, CKVBx
Output low voltage of STVP
Charge-sharing on-resistance
IOH = 10 mA
VON – 0.3
V
VON – 0.8
VOFF + 0.2
IOL = –10 mA
VOFF + 0.4
ICHSH = 10 mA
V
120
Ω
1.5
kΩ
100
kΩ
DISCHARGING CIRCUIT
RDSCHG
Discharging resistance
RBIAS
Resistance DISH to GND
DISH = –2 V
CONTROL DELAY
VDLYREF
Reference voltage for comparator
2.9
V
IDLYREF
Delay charge current
15
µA
RDLY
Delay resistor
140
200
260
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kΩ
3
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ELECTRICAL CHARACTERISTICS (continued)
VOFF = –10 V, VON = 30 V, EN = 3.3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
30
55
20
35
MAX
UNIT
AC CHARACTERISTICS
Slew–
Slew rate, Slew– STVP
Slew+
Slew rate, Slew+ STVP
tpf
Propagation delay, tpf-STVP
tpr
Propagation delay, tpr-STVP
Load = 4.7 nF (See Figure 1)
V/µs
Vµs
40
100
ns
30
100
ns
3.3 V
3.3 V / 2
STV
tpr-STVP
tpf-STVP
VON
97.5%
80%
(VON+VOFF) / 2
STVP
20%
2.5%
VOFF
Slew+ STVP
Slew– STVP
T0441-01
Figure 1. Switching Characteristics of STVP
4
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CKVx, CKVBx SWITCHING CHARACTERISTICS
VOFF = –10 V, VON = 30 V, EN = 3.3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tcsf
tcsf-CPVx_CKVx, tcsf-CPVx_CKVBx
tcsr
tcsr-CPVx_CKVx, tcsr-CPVx_CKVBx
tf
tf-CPVx_CKVx, tf-CPVx_CKVBx
tr
tr-CPVx_CKVx, tr-CPVx_CKVBx
MIN
fCPVx = 85 kHz, STV = GND,
See Figure 2, load = 4.7 nF,
RCS1 = RBCS1 = RCS2 = RBCS2 = 50 Ω
TYP
MAX
UNIT
80
150
ns
80
150
ns
40
100
ns
30
100
ns
3.3 V
3.3 V / 2
CPVx
GND
VON
97.5%
tf-CPVx_CKVx
tcsf-CPVx_CKVx
CKVx
(VON+VOFF) / 2
tcsr-CPVx_CKVx
tr-CPVx_CKVx
2.5%
VOFF
VON
97.5%
tf-CPVx_CKVBx
tcsf-CPVx_CKVBx
CKVBx
tcsr-CPVx_CKVBx
(VON+VOFF) / 2
tr-CPVx_CKVBx
VOFF
2.5%
T0442-01
Figure 2. Switching Characteristics of CKVx, CKVBx (STV = GND)
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CKVx, CKVBx SWITCHING CHARACTERISTICS (Continued)
VOFF = –10 V, VON = 30 V, EN = 3.3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Slew+
Slew+ CKVx, Slew+ CKVBx
fCPVx = 85 kHz, STV = 3.3 V, See Figure 3,
load = 4.7 nF, RCSx = RBCSx = 50 Ω
Slew–
Slew– CKVx, Slew– CKVBx
fCPVx = 85 kHz, STV = 3.3 V, See Figure 3,
load = 4.7 nF, RCSx = RBCSx = 50 Ω
MIN
TYP
MAX
UNIT
50
100
V/µs
70
130
V/µs
VON
80%
CKVx
Slew+ CKVx
Slew– CKVx
20%
VOFF
80%
CKVBx
Slew– CKVBx
Slew+ CKVBx
20%
T0443-01
Figure 3. CKVx, CKVBx Output Rise and Fall Times (STV = 3.3 V)
6
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DEVICE INFORMATION
AGND
NC
VON
19
CKV1
22
20
CKVCS1
23
21
CKVBCS1
24
RGE Package
(Top View)
CKVB1
1
18
17
NC
16
NC
15
DISH
VOFF
STVP
2
CKVB2
3
CKVBCS2
4
CKVCS2
5
14
AGND
CKV2
6
13
NC
9
10
11
12
NC
EN
DLY
8
CPV1
CPV2
7
STV
Exposed
Thermal
Pad
P0024-08
Exposed thermal pad and NC pins are recommended to be connected with ground on the PCB for better thermal
dissipation.
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
CKV1
22
O
Output vertical-scan clock 1 for ASG
CKV2
6
O
Output vertical-scan clock 2 for ASG
CKVB1
1
O
Inverted-output vertical-scan clock 1 for ASG
CKVB2
3
O
Inverted-output vertical-scan clock 2 for ASG
CKVBCS1
24
I
Charge-share input for CKVB1
CKVBCS2
4
I
Charge-share input for CKVB2
CKVCS1
23
I
Charge-share input for CKV1
CKVCS2
5
I
Charge-share input for CKV2
CPV1
8
I
Input vertical-scan clock 1
CPV2
9
I
Input vertical-scan clock 2
DISH
15
I
VOFF discharge control
DLY
12
O
Connecting a capacitor from this pin to GND allows the setting of the start-up delay.
EN
11
I
Enable pin of device. When this pin is pulled high, the device starts up after a delay time set by DLY has
passed.
GND
14, 21
–
Ground
NC
10,
13,
16,
17, 20
–
Not connected
STV
7
I
Input vertical-scan start signal
STVP
2
O
Output vertical-scan start signal
VOFF
18
I
Negative low-supply voltage
VON
19
I
Positive high-supply voltage
–
Not connected
Thermal pad
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TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
SYSTEM PERFORMANCE
Start-up sequence CKVx
Start-up sequence STVP
EN = HIGH after UVLO, CDLY = 10 nF, STV = LOW
Figure 4
EN = HIGH before UVLO, CDLY = 10 nF, STV = LOW
Figure 5
EN = HIGH after UVLO, CDLY = 10 nF, CPVx = LOW
Figure 6
EN = HIGH before UVLO, CDLY = 10 nF, CPVx = LOW
Figure 7
STV = HIGH, load = 4.7 nF
Figure 8
OUTPUT CKVx, CKVBx, and STVP
Rise time / propagation delay of CKVx
STV = LOW, load = 4.7 nF
Figure 9
STV = HIGH, load = 4.7 nF
Figure 10
STV = LOW, load = 4.7 nF
Figure 11
Rise time / propagation delay of STVP
CPV1 = LOW, load = 4.7 nF
Figure 12
Fall time / propagation delay of STVP
CPV1 = LOW, load = 4.7 nF
Figure 13
CPV1 = HIGH
Figure 14
CPV1 = LOW
Figure 15
STV = HIGH
Figure 16
STV = LOW
Figure 17
Fall time / propagation delay of CKVx
STVP output
CKVx, CKVBx outputs
Figure 4. Start-Up Sequence CKVx,
EN = HIGH After UVLO
8
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Figure 5. Start-Up Sequence CKVx,
EN = HIGH Before UVLO
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Figure 6. Start-Up Sequence STVP,
EN = HIGH After UVLO
Figure 7. Start-Up Sequence STVP,
EN = HIGH After UVLO
Figure 8. Rise Time / Propagation Delay of CKVx,
STV = HIGH
Figure 9. Rise Time / Propagation Delay of CKVx,
STV = LOW
Figure 10. Fall Time / Propagation Delay of CKVx,
STV = HIGH
Figure 11. Fall Time / Propagation Delay of CKVx,
STV = LOW
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10
Figure 12. Rise Time / Propagation Delay of STVP,
CPV1 = LOW
Figure 13. Fall Time / Propagation Delay of STVP,
CPV1 = LOW
Figure 14. STVP Output, CPV1 = HIGH
Figure 15. STVP Output, CPV1 = LOW
Figure 16. CKVx, CKVBx Outputs, STV = HIGH
Figure 17. CKVx, CKVBx Outputs, STV = LOW
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BLOCK DIAGRAM
VON
UVLO
DLY
CKV1
EN
CKVBCS1
Q1
Q
D
Gate
Driver
VOFF
VON
CKVCS1
CPV1
QB1
CLK Q
CKVB1
VON
VOFF
Gate
Driver
STV
STVP
VON
VOFF
DLY
CKV2
CKVBCS2
D
Q2
Q
Gate
Driver
VOFF
VON
CKVCS2
CPV2
QB2
CLK Q
CKVB2
EN
IDLY
VOFF
GND
Vref
DLY
DLY
GND
VOFF
DISH
B0366-01
DETAILED DESCRIPTION
UNDERVOLTAGE LOCKOUT
The device has an undervoltage lockout feature to avoid improper operation of the device when input voltage
VON is low. When VON is lower than 10 V, the device shuts down, and outputs CKVx, CKVBx, and STVP enter
the high-impedance state.
INPUT SIGNALS
The timing controller in the system provides input signals to the TPS65193. STV is the synchronous signal for
picture frames, and its frequency depends on the frame rate. CPVx are the synchronous signals for horizontal
lines, and their frequency depends on the frame rate and vertical resolution.
OUTPUT SIGNALS
The STVP, CKVx, and CKVBx scan-driver outputs are generated with internal switches. Table 1 and Table 2
show the logic diagrams of the scan-driver outputs.
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Table 1. STVP Logic Diagram
INPUT
OUTPUT
STV
CPV1
STVP
LOW
Don’t care
VOFF
HIGH
LOW
VON
HIGH
HIGH
High impedance
Table 2. CKVx, CKVBx, and Output Charge-Share Logic
INPUT
OUTPUT
STV
CPVx
CKVx
CKVBx
CHARGE SHARE
LOW
LOW
High impedance
High impedance
Enable
LOW
Rising edge
Toggle state
Toggle state
Disable
LOW
HIGH
Previous state
Previous state
Disable
HIGH
LOW
VOFF
VON
Disable
HIGH
HIGH
VON
VOFF
Disable
OUTPUT CHARGE SHARE
Power dissipation can be reduced by the output charge share. Figure 18 shows the current flows when the
charge share is enabled. CKVCSx and CKVBCSx are charge-share inputs. When the charge share is enabled,
the charge that is in the capacitor of the positive voltage line is transferred to the capacitor of the negative
voltage line. Charge-sharing resistors RCSx and RBCSx reduce the peak current into the charge-share inputs,
CKVCSx and CKVBCSx, during the output charge share. These resistors also control the slope of the output
charge-share waveform. The smaller RCSx and RBCSx, the bigger the peak current into the charge-share inputs
and the steeper the slope of output charge-share waveform. The power dissipation in charge-sharing resistors
should be taken into consideration. With 0603 size resistors, the power rating of two in parallel is good for most
applications.
VON
LCD Panel
CKVx
UVLO
RASG
CASG
DLY
D
CPVx
Q
CKVBCSx
Gate
Driver
RCS
VOFF
VON
CKVCSx
RBCS
CLK Q
CKVBx
RASG
CASG
VOFF
B0367-01
Figure 18. Single-Scan Driver Block Diagram
START-UP SEQUENCE (EN, DLY)
The TPS65193 has adjustable start-up sequencing that is set by EN and DLY. When VON is below the UVLO
threshold, all outputs are at high impedance. When EN is pulled LOW after the UVLO threshold is reached, all
12
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outputs follow VOFF. Pulling EN high enables the device after a delay time set by the capacitor connected to
DLY, and the delay time starts with EN = HIGH. If EN is pulled high before the UVLO threshold is reached, the
delay starts when VON reaches the UVLO threshold. Pulling EN low disables the device and outputs CKVx,
CKVBx, and STVP follow VOFF as long as VON is higher than the UVLO threshold. For the typical start-up
sequence, see Figure 19 and Figure 20.
SETTING THE DELAY TIME (DLY)
Connecting an external capacitor to the DLY pin sets the delay time. If no delay time is required, the DLY pin can
be left floating. The external capacitor is charged with a constant-current source of typically 15 µA. The delay
time is terminated when the capacitor voltage reaches the internal reference voltage of 2.9 V, and the final DLY
voltage on an external capacitor is maximum 8 V.The voltage rating of the external capacitor must be higher than
8 V.
The external delay capacitor is calculated using the following formula:
Delay time Delay time
CDLY =
=
RDLY
200 kW
(1)
Example for setting a delay time of 10 ms:
10 ms
CDLY =
= 50 nF » 47 nF
200 kW
(2)
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STV
CPVx
VOFF
VON
UVLO
Delay Time
EN
VREF
DLY
Charge
Share
CKVx
High
Impedance
Charge
Share
CKVBx
High
Impedance
Charge
Share
High Impedance
STVP
High
Impedance
T0444-01
Figure 19. Start-Up Sequence With EN = High After UVLO Threshold
14
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STV
CPVx
VOFF
VON
UVLO
Delay Time
EN
VREF
DLY
Charge
Share
CKVx
High
Impedance
CKVBx
Charge
Share
Charge
Share
High
Impedance
High Impedance
STVP
High
Impedance
T0445-01
Figure 20. Start-Up Sequence With EN = High Before UVLO Threshold
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TIMING DIAGRAM OF SCAN DRIVER
Figure 21 shows the typical timing diagram of the TPS65193.
STV
CPVx
Charge Share
CKVx
CKVBx
High Impedance
STVP
T0446-01
Figure 21. Scan Driver Timing Diagram
SUPPLY VOLTAGE, VON and VOFF
The TPS65193 drives the capacitive load. The high peak currents should be supplied from VON on the rising
edges of the outputs and VOFF on the falling edges of the outputs, respectively. Bypass capacitors of 1 µF must
be placed as close as possible on both VON and VOFF supplies. Depending on the peak current that the
TPS65193 must deliver, the bypass capacitor can be bigger than 1 µF.
VOFF DISCHARGE
DISH controls the VOFF discharging time during the system power off. Figure 22 shows a typical application for
VOFF discharge. DISH is connected to the system logic voltage through a capacitor. During power off, the
system logic voltage falls, and the voltage on DISH falls below ground level. An internal switch turns on when
DISH is below –0.6 V and VOFF is connected to ground through 1 kΩ, which helps VOFF discharge. A 1-µF
DISH capacitor is good for most applications. Figure 23 shows the typical power-off sequence of VOFF
discharging. VOFF discharge can be disabled by connecting DISH to GND directly.
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GND
1 kW
90 kW
10 kW
VOFF
VOFF
DISH
1 mF
Vlogic
S0419-01
Figure 22. Typical Application for VOFF Discharge
VIN
Time
Vlogic
DISH
Discharge is disabled.
VOFF
Discharge time depends on
capacitor on VOFF.
T0447-01
Figure 23. Power-Off Sequence of VOFF Discharge
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CKV1 to ASG
TYPICAL APPLICATION
250 W
19
VON
20
NC
21
AGND
22
CKV1
23
DISH
CKVCS2
AGND
17
Vlogic
16
15
1 mF
14
13
12
STV from T-CON 7
1 mF
18
DLY
NC
EN
CKV2
11
6
CKVBCS2
STV
CKV2 to ASG
NC
EN
5
250 W
CKVB2
NC
4
NC
10
250 W
STVP
CPV2
3
VOFF
CPV2 from T-CON 9
CKVB2 to ASG
VOFF
CKVB1
CPV1
2
CKVCS1
24
STVP to ASG
CKVBCS1
1
1 mF
250 W
CPV1 from T-CON 8
CKVB1 to ASG
VON
47 nF
S0420-01
Figure 24. Typical Application With VOFF Discharge Enabled
18
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Product Folder Link(s) :TPS65193
TPS65193
CKV1 to ASG
www.ti.com ....................................................................................................................................................................................................... SLVS964 – JULY 2009
250 W
19
VON
20
NC
21
AGND
22
CKV1
23
CKVCS2
AGND
NC
1 mF
17
16
15
14
13
12
STV from T-CON 7
18
DLY
CKV2
EN
6
DISH
11
250 W
CKVBCS2
STV
CKV2 to ASG
NC
EN
5
CKVB2
NC
4
NC
10
250 W
STVP
CPV2
3
VOFF
CPV2 from T-CON 9
CKVB2 to ASG
VOFF
CKVB1
CPV1
2
CKVCS1
24
STVP to ASG
CKVBCS1
1
1 mF
250 W
CPV1 from T-CON 8
CKVB1 to ASG
VON
47 nF
S0421-01
Figure 25. Typical Application With VOFF Discharge Disabled
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS65193
19
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TPS65193RGER
PREVIEW
VQFN
RGE
Pins Package Eco Plan (2)
Qty
24
3000
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Aug-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS65193RGER
Package Package Pins
Type Drawing
VQFN
RGE
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
4.3
B0
(mm)
K0
(mm)
P1
(mm)
4.3
1.5
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Aug-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65193RGER
VQFN
RGE
24
3000
346.0
346.0
29.0
Pack Materials-Page 2
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