TI SN74ALVC16834

SN74ALVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES140B – JULY 1998 – REVISED FEBRUARY 1999
D
D
D
D
D
Member of the Texas Instruments
Widebus  Family
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
NC
NC
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
description
This 18-bit universal bus driver is designed for
1.65-V to 3.6-V VCC operation.
Data flow from A to Y is controlled by the
output-enable (OE) input. The device operates in
the transparent mode when the latch-enable (LE)
input is low. The A data is latched if the clock (CLK)
input is held at a high or low logic level. If LE is
high, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLK. When OE is
high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power
up or power down, OE should be tied to VCC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
The SN74ALVC16834 is characterized
operation from –40°C to 85°C.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
GND
NC
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CLK
GND
NC – No internal connection
for
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ALVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES140B – JULY 1998 – REVISED FEBRUARY 1999
FUNCTION TABLE
INPUTS
CLK
A
OUTPUT
Y
X
X
X
Z
L
X
L
L
L
L
X
H
H
L
H
↑
L
L
L
H
↑
H
L
H
H
X
H
Y0†
OE
LE
H
L
Y0‡
† Output level before the indicated steady-state
input conditions were established, provided
that CLK is high before LE goes high
‡ Output level before the indicated steady-state
input conditions were established
L
H
L
X
logic symbol§
OE
CLK
27
EN1
30
2C3
28
LE
C3
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
3
1
1
3D
5
52
6
51
8
49
9
48
10
47
12
45
13
44
14
43
15
42
16
41
17
40
19
38
20
37
21
36
23
34
24
33
26
31
§ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
54
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A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
SN74ALVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES140B – JULY 1998 – REVISED FEBRUARY 1999
logic diagram (positive logic)
OE
CLK
LE
A1
27
30
28
54
1D
C1
3
Y1
CLK
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
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3
SN74ALVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES140B – JULY 1998 – REVISED FEBRUARY 1999
recommended operating conditions (see Note 4)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
MIN
MAX
1.65
3.6
2
0.35 × VCC
Low-level input voltage
VI
VO
Input voltage
0
Output voltage
0
0.7
VCC = 2.7 V to 3.6 V
IOL
∆t/∆v
High level output current
High-level
VCC = 2.7 V
VCC = 3 V
VCC = 1.65 V
VCC = 2.3 V
Low level output current
Low-level
VCC = 2.7 V
VCC = 3 V
Input transition rise or fall rate
V
1.7
VIL
IOH
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 1.65 V
VCC = 2.3 V
UNIT
V
0.8
VCC
VCC
V
V
–4
–12
–12
mA
–24
4
12
12
mA
24
10
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES140B – JULY 1998 – REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
IOH = –100 µA
IOH = –4 mA
1.65 V
IOH = –6 mA
VOH
IOH = –12 mA
IOH = –24 mA
IOL = 100 µA
VO = VCC or GND
VI = VCC or GND,
Ci
One input at VCC – 0.6 V,
Control inputs
Data inputs
IO = 0
Other inputs at VCC or GND
2.3 V
2
2.3 V
1.7
2.7 V
2.2
3V
2.4
3V
2
0.2
2.3 V
0.4
2.3 V
0.7
2.7 V
0.4
3V
0.55
±5
µA
3.6 V
±10
µA
3.6 V
40
µA
750
µA
4
33V
3.3
Co
Outputs
VO = VCC or GND
† All typical values are at VCC = 3.3 V, TA = 25°C.
V
3.6 V
3 V to 3.6 V
VI = VCC or GND
UNIT
V
0.45
IOL = 24 mA
VI = VCC or GND
ICC
∆ICC
MAX
VCC–0.2
1.2
1.65 V
IOL = 12 mA
II
IOZ
TYP†
1.65 V to 3.6 V
IOL = 4 mA
IOL = 6 mA
VOL
MIN
pF
5.5
3.3 V
7
pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
VCC = 1.8 V
MIN
fclock
tw
tsu
Clock frequency
Pulse duration
MAX
MIN
150
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
3.3
3.3
3.3
CLK high or low
‡
3.3
3.3
3.3
Data before CLK↑
‡
2.1
2.1
1.7
CLK high
‡
2.2
2.3
1.9
CLK low
‡
1.5
1.9
1.5
‡
0.6
0.6
0.7
‡
0.8
0.8
0.9
Data before LE↑
Data after LE↑
CLK
high or low
UNIT
MAX
150
LE low
Setup time
Hold time
MIN
VCC = 2.7 V
‡
Data after CLK↑
th
MAX
‡
VCC = 2.5 V
± 0.2 V
MHz
ns
ns
ns
‡ This information was not available at the time of publication.
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5
SN74ALVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES140B – JULY 1998 – REVISED FEBRUARY 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
fmax
VCC = 1.8 V
MIN
†
A
tpd
LE
Y
CLK
ten
tdis
TYP
VCC = 2.5 V
± 0.2 V
MIN
VCC = 2.7 V
MAX
150
MIN
MAX
150
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
150
MHz
†
1
4.4
4.2
1
3.6
†
1.3
6
5.9
1.5
4.9
†
1.2
6
5.3
1.5
4.6
ns
OE
Y
†
1.4
5.6
5.6
1.5
5
ns
OE
Y
†
1
4
4.7
1.8
4.5
ns
† This information was not available at the time of publication.
switching characteristics from 0°C to 65°C, CL = 50 pF
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CLK
Y
tpd
VCC = 3.3 V
± 0.15 V
MIN
MAX
1.7
4.3
UNIT
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
d
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0
0,
VCC = 1.8 V
TYP
†
f = 10 MHz
† This information was not available at the time of publication.
6
POST OFFICE BOX 655303
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†
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
38
41
13
15
UNIT
pF
SN74ALVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES140B – JULY 1998 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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7
SN74ALVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES140B – JULY 1998 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ALVC16834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES140B – JULY 1998 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
1.5 V
1.5 V
Input
0V
1.5 V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
2.7 V
1.5 V
0V
tPZL
2.7 V
Input
1.5 V
1.5 V
0V
tPLH
VOH
Output
1.5 V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLZ
3V
1.5 V
tPZH
tPHL
1.5 V
VOL
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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9
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Copyright  1999, Texas Instruments Incorporated