DATA SHEET MOS INTEGRATED CIRCUIT µ PD16640C 300/309-OUTPUT TFT-LCD SOURCE DRIVER (64 GRAY SCALE) DESCRIPTION The µ PD16640C is a source driver for TFT-LCD 64-gray scale displays. Its logic circuit operates at 3.3 V and the driver circuit operates at 3.3 or 5.0 V (selectable). The input data is digital data at 6 bits x 3 dots, and 260,000 colors can be displayed in 64-value outputs γ-corrected by the internal D/A converter and 11 external power supplies. The clock frequency is 55 MHz MIN. By switching over the number of outputs between 300 and 309, the µ PD16640C can be used in TFT-LCD panels conforming to the SVGA/XGA standards. FEATURES • CMOS level input • Number of outputs selectable (Osel = H : 300 outputs, Osel = L : 309 outputs) • 6 bits (gray scale data) x 3 dots input • 64-value output by 11 external power supplies and internal D/A converter • Output dynamic range : VSS2 + 0.1 V to VDD2 − 0.1 V • High-speed data transfer: fMAX.=55 MHz MIN.(internal data transfer speed when VDD1 = 3.0 V) • Precharge-less output buffer • Level of γ-corrected power supply can be inverted. • Input data inversion function (INV) • Logic power supply (VDD1) : 3.3 V ± 0.3 V • Driver power supply (VDD2) : 3.3 V ± 0.3 V (Vsel = H) 5.0 V ± 0.5 V (Vsel = L) ORDERING INFORMATION Part Number Package µ PD16640CN-xxx TCP (TAB package) Remark The TCP’s external shape is customized. To order your TCP’s external shape, please contact a NEC salesperson. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S11269EJ1V1DS00 (1st edition) Date Published June 1999 NS CP (K) Printed in Japan © 1999 µ PD16640C 1. BLOCK DIAGRAM STHR R,/L CLK Osel STHL VDD1 (3.3 V) VSS1 103-bit bidirectional shift register C1 C2 C102 C103 D00 - D05 D10 - D15 D20 - D25 INV Data register STB Latch Vsel VDD2 (3.3/5.0 V) D/A converter V0 - V10 VSS2 Output buffer S1 Remark 2 S2 S3 S309 /xxx indicates active low signal. Data Sheet S11269EJ1V1DS00 µ PD16640C 2. PIN CONFIGURATION (µ PD16640CN-xxx) S309 S308 S307 Vsel VSS2 VDD2 V10 V8 V6 V4 V2 V0 R,/L D20 D21 D22 D23 D24 D25 STB STHL VDD1 CLK VSS1 INV STHR D10 D11 D12 D13 D14 D15 D00 D01 D02 D03 D04 D05 V1 V3 V5 V7 V9 VDD2 VSS2 Osel Remark Copper Foil Surface S3 S2 S1 Osel and Vsel pins are internally pulled up. Therefore, the number of input pins can be reduced by opening or short-circuiting these pins to VSS2 by means of TCP writing. Data Sheet S11269EJ1V1DS00 3 µ PD16640C 3. PIN FUNCTIONS Pin Symbol Pin Name S1 to S309 Driver output D00 to D05 Display data input D10 to D15 Description Output 64 gray scale analog voltages converted from digital signals. Osel = H : 300 outputs (S1 - S150, S160 - S309) Osel = L : 309 outputs (S1 - S309) Output pins S151 to S159 are invalid in 300-output mode. Inputs 18-bit-wide display gray scale data (6 bits) x 3 dots (RGB). DX0 : LSB, DX5 : MSB D20 to D25 R,/L Shift direction select input STHR Right shift start pulse I/O STHL Left shift start pulse I/O Osel Number of output selection Vsel Driver voltage selection CLK Shift clock input STB Latch input V0 to V10 γ-corrected power supply INV Data inversion input VDD1 Logic circuit power supply VDD2 Driver circuit power supply VSS1 Logic ground Vsel = H : VDD2 = 3.3 V ± 0.3 V Vsel = L : VDD2 = 5.0 V ± 0.5 V Ground VSS2 Driver ground Ground Caution This pin inputs/outputs start pulses in cascade mode. Shift direction of shift register is as follows: R,/L = H : STHR input, S1 → S309, STHL output R,/L = L : STHL input, S309 → S1, STHR output R,/L = H : Inputs start pulse R,/L = L : Outputs start pulse R,/L = H : Outputs start pulse R,/L = L : Inputs start pulse Selects number of outputs. This pin is internally pulled up by VDD1 power supply. Osel = H : 300 outputs Osel = L : 309 outputs Selects driver voltage. This pin is internally pulled up by VDD2 power supply. Vsel = H : 300 outputs Vsel = L : 309 outputs Inputs shift clock to shift register. Display data is loaded to data register at rising edge of this pin. When Osel = H, start pulse output goes high at rising edge of 100th clock after start pulse has been input, and serves as start pulse to driver in next stage. When Osel = L, start pulse output goes high at rising edge of 103rd clock after start pulse has been input, and serves as start pulse to driver in next stage. 103rd clock of driver in first stage serves as start pulse of driver in next stage. Contents of data register are latched at rising edge, transferred to D/A converter, and output as analog voltage corresponding to display data. Contents of internal shift register are cleared after STB has been input. One pulse of this signal is input when µPD16640C is started, and then device operates normally. For STB input timing, refer to 8. SWITCHING CHARACTERISTIC WAVEFORM. Inputs γ-corrected power from external source. VSS2+0.1 V ≤ V10 ≤ V9 ≤ V8 ≤ V7 ≤ V6 ≤ V5 ≤ V4 ≤ V3 ≤ V2 ≤ V1 ≤ V0 ≤VDD2−0.1 V or VSS2+0.1 V ≤ V0 ≤ V1 ≤ V2 ≤ V3 ≤ V4 ≤ V5 ≤ V6 ≤ V7 ≤ V8 ≤ V9 ≤ V10 ≤VDD2−0.1 V Maintain gray scale power supply during gray scale voltage output. Input data can be inverted when display data is loaded. INV = H : Inverts and loads input data. INV = L : Does not invert input data. 3.3 V ± 0.3 V Be sure to turn on power in the order VDD1, logic input, VDD2, and gray scale power (V0 to V10), and turn off power in the reverse order, to prevent the µ PD16640C from being damaged by latchup. Be sure to observe this power sequence even during a transition period. 4 Data Sheet S11269EJ1V1DS00 µ PD16640C 4. RELATION BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE The 11 major points on the γ-characteristic curve of the LCD panel are arbitrarily set by external power supplies V0 through V10. If the display data is 00H or 3FH, gray scale voltage V0 or V10 is output. If the display data is in the range 01H to 3EH, the high-order 3 bits select an external powers pair Vn+1, Vn. The low-order 3 bits evenly divide the range of Vn+1, Vn into eight segments by means of D/A conversion (however, the ranges from V9 to V8 and from V2 to V1 are divided into seven segments) to output a 64-grayscale voltage. DX5 (MSB) DX4 DX3 DX2 High-order 3 bits : γ-corrected power selected (Vn+1-Vn) DX5 0 0 0 0 1 1 1 1 DX4 0 0 1 1 0 0 1 1 DX3 0 1 0 1 0 1 0 1 DX0 (LSB) DX1 Low-order 3 bits : 3-bit D/A (range Vn-Vn+1 is divided into 7 or 8 segments) Vn Vn+1-Vn V1-V2 V2-V3 V3-V4 V4-V5 V5-V6 V6-V7 V7-V8 V8-V9 1 2 3 4 5 6 7 8 Vn+1 000 001 010 011 100 101 110 111 DX2-DX0 Figure 4-1. Relation between Input Data and γ -corrected Voltage VDD2 0.1 V gray scale supply specified by 00H V0 V1 7 segments V2 8 segments V3 8 segments V4 8 segments V5 8 segments V6 8 segments V7 8 segments V8 7 segments V9 gray scale supply specified by 3FH V10 0.1 V VSS2 0 7 F 17 1F 27 2F 37 3F Input data (HEX) Data Sheet S11269EJ1V1DS00 5 µ PD16640C Table 4-1. Relation between Input Data and Output Voltage Input Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 6 DX5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DX3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DX2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DX1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DX0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Data Sheet S11269EJ1V1DS00 Output Voltage V0 V2 + (V1 – V2) × 6/7 V2 + (V1 – V2) × 5/7 V2 + (V1 – V2) × 4/7 V2 + (V1 – V2) × 3/7 V2 + (V1 – V2) × 2/7 V2 + (V1 – V2) × 1/7 V2 V3 + (V2 – V3) × 7/8 V3 + (V2 – V3) × 6/8 V3 + (V2 – V3) × 5/8 V3 + (V2 – V3) × 4/8 V3 + (V2 – V3) × 3/8 V3 + (V2 – V3) × 2/8 V3 + (V2 – V3) × 1/8 V3 V4 + (V3 – V4) × 7/8 V4 + (V3 – V4) × 6/8 V4 + (V3 – V4) × 5/8 V4 + (V3 – V4) × 4/8 V4 + (V3 – V4) × 3/8 V4 + (V3 – V4) × 2/8 V4 + (V3 – V4) × 1/8 V4 V5 + (V4 – V5) × 7/8 V5 + (V4 – V5) × 6/8 V5 + (V4 – V5) × 5/8 V5 + (V4 – V5) × 4/8 V5 + (V4 – V5) × 3/8 V5 + (V4 – V5) × 2/8 V5 + (V4 – V5) × 1/8 V5 V6 + (V5 – V6) × 7/8 V6 + (V5 – V6) × 6/8 V6 + (V5 – V6) × 5/8 V6 + (V5 – V6) × 4/8 V6 + (V5 – V6) × 3/8 V6 + (V5 – V6) × 2/8 V6 + (V5 – V6) × 1/8 V6 V7 + (V6 – V7) × 7/8 V7 + (V6 – V7) × 6/8 V7 + (V6 – V7) × 5/8 V7 + (V6 – V7) × 4/8 V7 + (V6 – V7) × 3/8 V7 + (V6 – V7) × 2/8 V7 + (V6 – V7) × 1/8 V7 V8 + (V7 – V8) × 7/8 V8 + (V7 – V8) × 6/8 V8 + (V7 – V8) × 5/8 V8 + (V7 – V8) × 4/8 V8 + (V7 – V8) × 3/8 V8 + (V7 – V8) × 2/8 V8 + (V7 – V8) × 1/8 V8 V9 + (V8 – V9) × 6/7 V9 + (V8 – V9) × 5/7 V9 + (V8 – V9) × 4/7 V9 + (V8 – V9) × 3/7 V9 + (V8 – V9) × 2/7 V9 + (V8 – V9) × 1/7 V9 V10 µ PD16640C 4.1 γ-corrected Power Circuit The reference power supply of the D/A converter consists of a ladder circuit with a total of 64 resistors, and resistance Σri between γ-corrected power pins differs depending on each pair of γ-corrected power pins. One pair of γ-corrected power pins consists of seven or eight series resistors, and resistance Σri in the figure below is indicated as the sum of the seven or eight resistors. The resistance ratio between the γ-corrected power pins (Σri ratio) is designed to be a value relatively close to the ratio of the γ-corrected voltages V1 to V9 (gray-scale voltages in 8 steps) used in an actual LCD panel. Under ideal conditions where there is no difference between the two, therefore, there is no voltage difference between the voltage of the γ-corrected power supplies and the gray-scale voltages in 8 steps of the resistor ladder circuits of the µPD16640C, and no current flows into the γ-corrected power pins V1 to V9. As a result, a voltage-follower circuit is not necessary. Figure 4-2. γ -corrected Power Circuit γ-corrected power pin γ-corrected resistor − + V0 µ PD16640C i0 R0 = 2.39 kΩ − + V1 − + V2 i1 i2 − + V3 i3 − + V4 − + V5 − + V6 − + V7 − + V8 − + V9 i9 − + V10 i10 i4 i5 i6 i7 i8 7 R1 = Σ ri = 4.45 kΩ i=1 8 R2 = Σ ri = 6.19 kΩ i=1 Sum of eight γ-corrected resistors 8 R3 = Σ ri = 3.58 kΩ i=1 8 R4 = Σ ri = 2.15 kΩ i=1 8 R5 = Σ ri = 2.03 kΩ i=1 8 R6 = Σ ri = 1.61 kΩ i=1 8 R7 = Σ ri = 2.03 kΩ i=1 7 R8 = Σ ri = 3.39 kΩ i=1 R9 = 2.55 kΩ Data Sheet S11269EJ1V1DS00 7 µ PD16640C 5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format : 6 bits x RGB(3 dots) Input width : 18 bits (1) R,/L = H (right shift) Output S1 S2 S3 … S308 S309 Data D00 to D05 D10 to D15 D20 to D25 … D10 to D15 D20 to D25 (2) R,/L = L (left shift) Output S1 S2 S3 … S299 S300 Data D00 to D05 D10 to D15 D20 to D25 … D10 to D15 D20 to D25 6. OPERATION OF OUTPUT BUFFER The output buffer consists of an operational amplifier circuit that does not perform precharge operation. Therefore, driver output current IVOH1/2 is the charging current to the LCD, and IVOL1/2 is the discharging current. Figure 6-1. LCD Panel Driving Waveform VDD2 Sn VSS2 Write (IVOL1/2/IVOH1/2) Write (IVOL1/2/IVOH1/2) 1 horizontal period 8 Data Sheet S11269EJ1V1DS00 µ PD16640C 7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (VSS1 = VSS2 = 0 V) Parameter Symbol Ratings Unit Logic power supply VDD1 –0.3 to +4.5 V Driver power supply VDD2 –0.3 to +6.0 V Input voltage VI –0.3 to VDD1,2 + 0.3 V Output voltage VO –0.3 to VDD1,2 + 0.3 V Operating ambient temperature TA –10 to +75 °C Storage temperature Tstg –55 to +125 °C Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. Recommended Operating Range (TA = –10 to +75 °C, VSS1 = VSS2 = 0 V) Parameter Symbol Logic supply voltage VDD1 Driver supply voltage VDD2 Condition MIN. TYP. MAX. Unit 3.0 3.3 3.6 V Vsel = H 3.0 3.3 3.6 V Vsel = L 4.5 5.0 5.5 V 0.7VDD1 VDD1 V 0 0.3VDD1 V VSS2+0.1 VDD2−0.1 V High-level input voltage VIH R,/L, CLK, STB, Osel, Vsel, Low-level input voltage VIL STHR(STHL), D00-D05,D10-D15, D20-D25 γ-corrected supply voltage V0-V10 Maximum clock frequency fMAX. 55 Data Sheet S11269EJ1V1DS00 MHz 9 µ PD16640C Electrical Characteristics (TA = –10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 3.3 V ± 0.3 V or 5.0 V ± 0.5 V, VSS1 = VSS2 = 0 V) Parameter Input leakage current Symbol IIL Condition MIN. TYP. D00-D05, D10-D15, D20-D25, MAX. Unit ±1.0 µA 250 kΩ R,/L, STB Pull-up resistor RPU VDD1 = 3.3 V, Osel, Vsel High-level output voltage VOH STHR(STHL),IO=−1.0 mA Low-level output voltage VOL STHR(STHL),IO=+1.0 mA Static current consumption of Ivn1 VDD1=3.3 V V0-V1 105 Vn−Vn+1=0.5 V V1-V2 γ -corrected supply current (VDD2 = 3.3 V or 5.0 V) Driver output current IVOH1 (VDD2 = 3.3 V) VOUT=2.7 V, Vx=3.2 V 40 100 VDD1 − 0.5 V 0.5 V 210 420 µA 56 113 226 µA V2-V3 41 82 164 µA V3-V4 70 140 280 µA V4-V5 117 234 468 µA V5-V6 124 248 496 µA V6-V7 156 313 626 µA V7-V8 124 248 496 µA V8-V9 74 149 298 µA V9-V10 99 198 396 µA −0.16 −0.08 mA Note1 VDD1=VDD2=3.3 V IVOL1 VOUT=0.6 V, Vx=0.1 VNote1 0.07 0.14 mA VDD1=VDD2=3.3 V Driver output current IVOH2 (VDD2 = 5.0 V) −0.24 VOUT=4.4 V, Vx=4.9 VNote1 −0.12 mA VDD1=3.3 V, VDD2=5.0 V IVOL2 VOUT=0.6 V, Vx=0.1 VNote1 0.10 0.20 mA VDD1=3.3 V, VDD2=5.0 V Output voltage deviation ∆VO ±10 VDD1=3.3 V, ±20 mV VDD2=3.3 V or 5.0 V, VOUT= 0.5 V,1.5 V, 2.5 VNote1 Output voltage deviation ∆VP-P Input data Output voltage range VO Input data : 00H to 3FH Dynamic logic current Note2 ±5 VSS2 + 0.1 mV VDD2 − 0.1 V IDD1 No load 0.5 2.5 mA IDD21 No load, VDD2=3.3 VNote2 3.0 10 mA IDD22 No load, VDD2=5.0 VNote2 3.0 10 mA consumption Dynamic driver current consumption Notes 1. VX is output voltage of analog output pins S1 to S309. VOUT is the voltage applied to analog output pins S1 to S309. 2. The STB cycle is specified at 31 µ s and fCLK = 16 MHz. 10 Data Sheet S11269EJ1V1DS00 µ PD16640C Switching Characteristics (TA = −10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 3.3 V ± 0.3 V or 5.0 V ± 0.5 V, VSS1 = VSS2 = 0 V) Parameter Start pulse delay time Symbol tPLH1 Condition MIN. CL = 15 pF tPHL1 Driver output delay time Driver output delay time Input capacitance TYP. MAX. Unit 7 12 ns 7 12 ns tPLH21 VDD2=3.3 V VO:0.1 V 2.6 tPLH31 2 kΩ +75 pF x 2 →3.2 V 3.0 tPHL21 VO:3.2 V 2.4 tPHL31 →0.1 V 3.2 µs 10 µs µs 10 µs µs tPLH22 VDD2=5.0 V VO:0.1 V 2.2 tPLH32 2 kΩ +75 pF x 2 →4.9 V 2.9 tPHL22 VO:4.9 V 2.6 tPHL32 →0.1 V 3.6 10 µs 10 µs µs CI1 STHR(STHL), TA=25 °C 10 20 pF CI2 V0-V10, TA = 25 °C 60 100 pF CI3 STHR(STHL), other than V0-V10, 10 15 pF MAX. Unit TA=25 °C Timing Requirements (TA = −10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VSS1 = 0 V, tr = tf = 3.0 ns) Parameter Symbol Condition MIN. TYP. Clock pulse width PW CLK 18 ns Clock pulse high period PW CLK (H) 4 ns Clock pulse low period PW CLK (L) 4 ns Data setup time tSETUP1 4 ns Data hold time tHOLD1 0 ns Start pulse setup time tSETUP2 4 ns Start pulse hold time tHOLD2 0 ns INV setup time tSETUP4 4 ns INV hold time tHOLD4 0 ns Start pulse low period tSPL 2 CLK Start pulse rise time tSPR1 Osel=H 100 CLK tSPR2 Osel=L 103 CLK Final data timing tSETUP3 CLK-STB time tINV STB-CLK time tLDT 1 CLK 1 CLK 1 CLK Time between STB and start pulse tCLK-STB CLK↑→STB↑ 7 ns STB-POL time STB↑ →CLK↑ 7 ns tSTB-CLK Data Sheet S11269EJ1V1DS00 11 PWCLK(H) 1 tr 2 1 CLK tSETUP2 2 3 103 104 105 1023 1024 1025 tf VDD1 90% 10% VSS1 tSPL tHOLD2 VDD1 STHR (1st Dr.) VSS1 tINV tSETUP1 tSETUP3 tHOLD1 VDD1 Dn0 - Dn5 INVALID D1 - D3 D4 - D 6 D304 D306 D307 D309 D310 D312 D3064 D3066 D3067 D3069 D3070 D3072 D1 - D3 INVALID D4 - D6 VSS1 tSETUP4 tHOLD4 VDD1 Data Sheet S11269EJ1V1DS00 INV INVALID INVALID VSS1 tPLH1 tPHL1 tSPR1/2 VDD1 STHL (1st Dr.) VSS1 tCLK-STB tSTB-CLK tLDT VDD1 STB VSS1 tPLH31/32 tPLH21/22 Hi-Z 8. SWITCHING CHARACTERISTIC WAVEFORM(R,/L= H) PWCLK Unless otherwise specified, the input level is defined to VIH = 0.7 VDD1, VIL = 0.3 VDD1. 12 PWCLK(L) Target Voltage ±0.1 VDD2 VOUT 6-bit accuracy tPHL31/32 µ PD16640C tPHL21/22 µ PD16640C 9. RECOMMENDED MOUNTING CONDITIONS The following conditions must be met for mounting conditions of the µPD16640C. For more details, refer to the Semiconductor Device Mounting Technology Manual(C10535E). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. µ PD16640CN-xxx : TCP(TAB Package) Mounting Condition Thermocompression Mounting Method Condition Heating tool 300 to 350 °C, heating for 2 to 3 sec ; pressure 100g(per Soldering solder) ACF Temporary bonding 70 to 100 °C ; pressure 3 to 8 kg/cm ; time 3 to 5 (Adhesive Conductive sec. Real bonding 165 to 180 °C pressure 25 to 45 kg/cm time 30 to Film) 40secs(When using the anisotropy conductive film SUMIZAC1003 of 2 2 Sumitomo Bakelite,Ltd). Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time. Data Sheet S11269EJ1V1DS00 13 µ PD16640C [MEMO] 14 Data Sheet S11269EJ1V1DS00 µ PD16640C NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S11269EJ1V1DS00 15 µ PD16640C Reference Documents NEC Semiconductor Device Reliability/Quality Control System(C10983E) Quality Grades to NEC’s Semiconductor Devices(C11531E) • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8