DATA SHEET MOS INTEGRATED CIRCUIT µ PD16732D 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALES) DESCRIPTION The µPD16732D is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as VSS2 + 0.1 V to VDD2 – 0.1 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 65 MHz when driving at 3.0 V, 45 MHz when driving at 2.3 V, this driver is applicable to XGA-standard TFT-LCD panels and SXGA TFT-LCD panels. FEATURES • CMOS level input (2.3 to 3.6 V) • 384 outputs • Input of 6 bits (gray-scale data) by 6 dots • Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter • Logic power supply voltage (VDD1): 2.3 to 3.6 V • Driver power supply voltage (VDD2): 8.0 to 9.0 V • High-speed data transfer: fCLK = 65 MHz (internal data transfer speed when operating at VDD1 = 3.0 V) • Output dynamic range: VSS2 + 0.1 V to VDD2 – 0.1 V • Apply for dot-line inversion, n-line inversion and column line inversion • Output voltage polarity inversion function (POL) • Display data inversion function (capable of controlling by each input port) (POL21,POL22) • Current consumption control function (LPC, Bcont) • Succession of µPD16732A driver ORDERING INFORMATION Part Number Package µPD16732DN-xxx TCP (TAB package) Remark The TCP’s external shape is customized. To order the required shape, so please contact one of our sales representatives. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15022EJ1V0DS00 (1st edition) Date Published June 2002 NS CP (K) Printed in Japan The mark ★ shows major revised points. © 2001,2002 µPD16732D 1. BLOCK DIAGRAM STHR R,/L CLK STB STHL VDD1 VSS1 64-bit bidirectional shift register C1 C2 C63 D00 - D05 D10 - D15 D20 - D25 D30 - D35 D40 - D45 D50 - D55 POL21,POL22 C64 Data register Latch POL VDD2 Level shifter VSS2 V0 - V9 D/A converter LPC Bcont Voltage follower output S1 S2 S3 S384 Remark /xxx indicates active low signal. 2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER S1 V5 S383 5 V0 V4 S2 Multiplexer 6-bit D/A converter 5 V9 POL 2 Data Sheet S15022EJ1V0DS S384 µPD16732D 3. PIN CONFIGURATION (Top of copper foil surface, face-up) µPD16732DN-xxx: TCP (TAB package) STHL D55 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 D30 VDD1 R,/L V9 V8 V7 V6 V5 VDD2 VSS2 Bcont V4 V3 V2 V1 V0 VSS1 LPC CLK STB POL POL21 POL22 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 STHR S384 S383 S382 S381 Copper foil surface S4 S3 S2 S1 Remark This figure does not specify the TCP package. Data Sheet S15022EJ1V0DS 3 µPD16732D 4. PIN FUNCTIONS (1/2) Pin Symbol Pin Name S1 to S384 Driver D00 to D05 Display data I/O Output Input Description The D/A converted 64-gray-scale analog voltage is output. The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by D10 to D15 6 dots (2 pixels). D20 to D25 DX0: LSB, DX5: MSB D30 to D35 D40 to D45 D50 to D55 R,/L Shift direction control Input The shift direction control pin of the shift register. The shift directions of the shift registers are as follows. R,/L = H (right shift): STHR (input), S1 → S384, STHL (output) R,/L = L (left shift) : STHL (input), S384 → S1, STHR (output) STHR Right shift start pulse I/O These refer to the start pulse I/O pins when the IC is connected in cascade. Loading of display data starts when a high level is read at the rising edge of CLK. A high level should be input as the pulse of one cycle of the clock signal. ★ STHL Left shift start pulse I/O If the start pulse input is more than 2CLKs, the first 1CLK of the high-level input is valid. R,/L = H (right shift): STHR input, STHL output R,/L = L (left shift): STHL input, STHR output CLK Shift clock Input This pin refers to the shift clock input of the shift register. The display data is loaded into the data register at the rising edge. At the rising edge of the 64th after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. When the 66 clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB’s rising edge. STB Latch Input The contents of the data register are transferred to the latch circuit at the rising edge. In addition, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL Polarity input Input POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to V9 as the reference supply. POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to V4 as the reference supply. S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge. POL21, Data inversion Input POL22 Select of inversion or no inversion for input data. POL21: D00-D05, D10-D15, D20-D25 Data inversion or no inversion of Port1 POL22: D30-D35, D40-D45, D50-D55 Data inversion or no inversion of Port2 POL21,POL22 = H: Data are inverted in the IC. POL21,POL22 = L: Data are not inverted in the IC. LPC Low power control Input The current consumption is lowered by controlling the constant current source of the output amplifier. In low power mode (LPC = L), the VDD2 of static current consumption can be reduced to two thirds of the normal current consumption. This pin is pulled up to the VDD1 power supply inside the IC. LPC = H or open: Normal power mode LPC = L: Low power mode Bcont Bias control Input This pin can be used to finely control the bias current inside the output amplifier. In cases when fine-control is necessary, connect this pin to the stabilized ground potential (VSS2) via an external resistor of 10 to 100 kΩ (per IC). When this fine-control function is not required, leave this pin open. Refer to 9. CURRENT CONSUMPTION REDUCTION FUNCTION 4 Data Sheet S15022EJ1V0DS µPD16732D (2/2) Pin Symbol V0 to V9 Pin Name γ -corrected power I/O − supplies Description Input the γ -corrected power supplies from outside by using operational amplifier. Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. VDD2 − 0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 0.5 VDD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V VDD1 Logic power supply − 2.3 to 3.6 V VDD2 Driver power supply − 8.0 to 9.0 V VSS1 Logic ground − Grounding VSS2 Driver ground − Grounding Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down (Simultaneous power application to VDD2 and V0 to V9 is possible.). 2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.01 µF is also recommended between the γ -corrected power supply terminals (V0, V1, V2,....., V9) and VSS2. Data Sheet S15022EJ1V0DS 5 µPD16732D 5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE The µPD16732D incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD’s counter electrode voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel γ -compensated voltages to V0’ to V63’ and V0” to V63” is almost equivalent as shown in Figure 5-2. For the 2 sets of five γ -compensated power supplies, V0 to V4 and V5 to V9, respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine-gray scale voltage precision is not necessary, there is no need to connect voltage follower circuit to the γ –corrected power supplies V1 to V3 and V6 to V8. Figure 5–1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2, and γ -corrected voltages V0 to V9 and the input data. Be sure to maintain the voltage relationships as follows. VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 ★ 0.5 VDD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V Figures 5–2 indicates γ -corrected voltages and ladder resistors ratio. Figures 5–3 indicates the relationship between the input data and output voltage and the resistance values of the resistor string. Figure 5–1. Relationship between Input Data and γ-corrected Power Supplies VDD2 0.1 V V0 16 V1 16 V2 16 V3 15 V4 0.5 VDD2 Split interval V5 15 16 V6 16 V7 V8 16 V9 0.1 V VSS2 00 10 20 30 Input Data (HEX) 6 Data Sheet S15022EJ1V0DS 3F µPD16732D Figure 5–2. γ -corrected Voltages and Ladder Resistor’s Ratio ★ V0 V0' V5 r0 V63'' r62 V1' V62'' r1 r61 V2' V61'' r2 r60 V3' V60'' r3 r59 r14 r49 V15' r15 V1 V16' V48'' V6 r16 r47 V47'' V17' r17 r46 r46 r47 V3 r17 V17'' V47' r16 V48' r48 V16'' V8 r15 V15'' V49' r14 r49 r60 r61 r2 V61' V2'' r1 V1'' V62' r62 V4 V49'' r48 r0 V63' V9 V0'' rn r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r48 r49 r50 r51 r52 r53 r54 r55 r56 r57 r58 r59 r60 r61 r62 Ratio1 8.0 7.5 7.0 6.5 6.0 5.5 5.5 5.0 5.0 4.0 4.0 3.5 3.5 3.5 3.0 3.0 3.0 2.5 2.5 2.5 2.0 2.0 2.0 1.5 1.5 1.5 1.5 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.5 1.5 1.5 2.0 2.0 2.5 2.5 3.0 5.0 8.0 Ratio2 0.050 0.047 0.044 0.041 0.038 0.035 0.035 0.032 0.032 0.025 0.025 0.022 0.022 0.022 0.019 0.019 0.019 0.016 0.016 0.016 0.013 0.013 0.013 0.009 0.009 0.009 0.009 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.006 0.009 0.009 0.009 0.013 0.013 0.016 0.016 0.019 0.032 0.050 Value(Ω) 800 750 700 650 600 550 550 500 500 400 400 350 350 350 300 300 300 250 250 250 200 200 200 150 150 150 150 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 150 150 150 200 200 250 250 300 500 800 Caution There is no connection between V4 and V5 terminal in the chip. Remark The resistance ratio1 is a relative ratio in the case of setting the minimum resistance value to 1. The resistance ratio2 is a relative ratio in the case of setting the total resistance to 1. Data Sheet S15022EJ1V0DS 7 µPD16732D ★ Figure 5–3. Relationship between Input Data and Output Voltage (POL21,POL22 = L) (Output Voltage 1) VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 (Output Voltage 2) 0.5 VDD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V Input Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH V0' V1' V2' V3' V4' V5' V6' V7' V8' V9' V10' V11' V12' V13' V14' V15' V16' V17' V18' V19' V20' V21' V22' V23' V24' V25' V26' V27' V28' V29' V30' V31' V32' V33' V34' V35' V36' V37' V38' V39' V40' V41' V42' V43' V44' V45' V46' V47' V48' V49' V50' V51' V52' V53' V54' V55' V56' V57' V58' V59' V60' V61' V62' Output Voltage1 V0 V1+(V0-V1)× 7250 V1+(V0-V1)× 6500 V1+(V0-V1)× 5800 V1+(V0-V1)× 5150 V1+(V0-V1)× 4550 V1+(V0-V1)× 4000 V1+(V0-V1)× 3450 V1+(V0-V1)× 2950 V1+(V0-V1)× 2450 V1+(V0-V1)× 2050 V1+(V0-V1)× 1650 V1+(V0-V1)× 1300 V1+(V0-V1)× 950 V1+(V0-V1)× 600 V1+(V0-V1)× 300 V1 V2+(V1-V2)× 2450 V2+(V1-V2)× 2200 V2+(V1-V2)× 1950 V2+(V1-V2)× 1700 V2+(V1-V2)× 1500 V2+(V1-V2)× 1300 V2+(V1-V2)× 1100 V2+(V1-V2)× 950 V2+(V1-V2)× 800 V2+(V1-V2)× 650 V2+(V1-V2)× 500 V2+(V1-V2)× 400 V2+(V1-V2)× 300 V2+(V1-V2)× 200 V2+(V1-V2)× 100 V2 V3+(V2-V3)× 1500 V3+(V2-V3)× 1400 V3+(V2-V3)× 1300 V3+(V2-V3)× 1200 V3+(V2-V3)× 1100 V3+(V2-V3)× 1000 V3+(V2-V3)× 900 V3+(V2-V3)× 800 V3+(V2-V3)× 700 V3+(V2-V3)× 600 V3+(V2-V3)× 500 V3+(V2-V3)× 400 V3+(V2-V3)× 300 V3+(V2-V3)× 200 V3+(V2-V3)× 100 V3 V4+(V3-V4)× 3350 V4+(V3-V4)× 3250 V4+(V3-V4)× 3150 V4+(V3-V4)× 3050 V4+(V3-V4)× 2950 V4+(V3-V4)× 2800 V4+(V3-V4)× 2650 V4+(V3-V4)× 2500 V4+(V3-V4)× 2300 V4+(V3-V4)× 2100 V4+(V3-V4)× 1850 V4+(V3-V4)× 1600 V4+(V3-V4)× 1300 V4+(V3-V4)× 800 3FH V63' V4 / / / / / / / / / / / / / / / 8050 8050 8050 8050 8050 8050 8050 8050 8050 8050 8050 8050 8050 8050 8050 / / / / / / / / / / / / / / / 2750 2750 2750 2750 2750 2750 2750 2750 2750 2750 2750 2750 2750 2750 2750 / / / / / / / / / / / / / / / 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 / / / / / / / / / / / / / / 3450 3450 3450 3450 3450 3450 3450 3450 3450 3450 3450 3450 3450 3450 V0'' V1'' V2'' V3'' V4'' V5'' V6'' V7'' V8'' V9'' V10'' V11'' V12'' V13'' V14'' V15'' V16'' V17'' V18'' V19'' V20'' V21'' V22'' V23'' V24'' V25'' V26'' V27'' V28'' V29'' V30'' V31'' V32'' V33'' V34'' V35'' V36'' V37'' V38'' V39'' V40'' V41'' V42'' V43'' V44'' V45'' V46'' V47'' V48'' V49'' V50'' V51'' V52'' V53'' V54'' V55'' V56'' V57'' V58'' V59'' V60'' V61'' V62'' Output Voltage2 V9 V9+(V8-V9)× 800 V9+(V8-V9)× 1550 V9+(V8-V9)× 2250 V9+(V8-V9)× 2900 V9+(V8-V9)× 3500 V9+(V8-V9)× 4050 V9+(V8-V9)× 4600 V9+(V8-V9)× 5100 V9+(V8-V9)× 5600 V9+(V8-V9)× 6000 V9+(V8-V9)× 6400 V9+(V8-V9)× 6750 V9+(V8-V9)× 7100 V9+(V8-V9)× 7450 V9+(V8-V9)× 7750 V8 V8+(V7-V8)× 300 V8+(V7-V8)× 550 V8+(V7-V8)× 800 V8+(V7-V8)× 1050 V8+(V7-V8)× 1250 V8+(V7-V8)× 1450 V8+(V7-V8)× 1650 V8+(V7-V8)× 1800 V8+(V7-V8)× 1950 V8+(V7-V8)× 2100 V8+(V7-V8)× 2250 V8+(V7-V8)× 2350 V8+(V7-V8)× 2450 V8+(V7-V8)× 2550 V8+(V7-V8)× 2650 V7 V7+(V6-V7)× 100 V7+(V6-V7)× 200 V7+(V6-V7)× 300 V7+(V6-V7)× 400 V7+(V6-V7)× 500 V7+(V6-V7)× 600 V7+(V6-V7)× 700 V7+(V6-V7)× 800 V7+(V6-V7)× 900 V7+(V6-V7)× 1000 V7+(V6-V7)× 1100 V7+(V6-V7)× 1200 V7+(V6-V7)× 1300 V7+(V6-V7)× 1400 V7+(V6-V7)× 1500 V6 V6+(V5-V6)× 100 V6+(V5-V6)× 200 V6+(V5-V6)× 300 V6+(V5-V6)× 400 V6+(V5-V6)× 500 V6+(V5-V6)× 650 V6+(V5-V6)× 800 V6+(V5-V6)× 950 V6+(V5-V6)× 1150 V6+(V5-V6)× 1350 V6+(V5-V6)× 1600 V6+(V5-V6)× 1850 V6+(V5-V6)× 2150 V6+(V5-V6)× 2650 / / / / / / / / / / / / / / / 8050 8050 8050 8050 8050 8050 8050 8050 8050 8050 8050 8050 8050 8050 8050 / / / / / / / / / / / / / / / 2750 2750 2750 2750 2750 2750 2750 2750 2750 2750 2750 2750 2750 2750 2750 / / / / / / / / / / / / / / / 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 / / / / / / / / / / / / / / 3450 3450 3450 3450 3450 3450 3450 3450 3450 3450 3450 3450 3450 3450 V63'' V5 Caution There is no connection between V4 and V5 terminal in the chip. 8 Data Sheet S15022EJ1V0DS µPD16732D 6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format : 6 bits x 2 RGBs (6 dots) Input width : 36 bits (2-pixel data) (1) R,/L = H (Right shift) Output S1 S2 S3 S4 ... S383 S384 Data D00 to D05 D10 to D15 D20 to D25 D30 to D35 ... D40 to D45 D50 to D55 (2) R,/L = L (Left shift) Output S1 S2 S3 S4 ... S383 S384 Data D00 to D05 D10 to D15 D20 to D25 D30 to D35 ... D40 to D45 D50 to D55 Note POL Note S2n–1 S2n L V0 to V4 V5 to V9 H V5 to V9 V0 to V4 Note S2n–1 (Odd output), S2n (Even output) 7. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM The output voltage is written to the LCD panel synchronized with the STB falling edge. STB POL S2n-1 Selected voltage V0 to V4 Selected voltage V5 to V9 Selected voltage V0 to V4 S2n Selected voltage V0 to V4 Selected voltage V5 to V9 Hi-Z Hi-Z Data Sheet S15022EJ1V0DS Selected voltage V5 to V9 Hi-Z 9 µPD16732D 8. RELATIONSHIP BETWEEN STB, CLK, AND OUTPUT WAVEFORM The output voltage is written to the LCD panel synchronized with the STB falling edge. Figure 8–1. Output Circuit Block Diagram Output Amp - DAC + SW1 Sn (VX) VAMP(IN) Figure 8–2. Output Circuit Block Diagram [1] [2] CLK (External Input) STB (External Input) SW1 : ON SW1 : OFF SW1 : ON VAMP(IN) Sn (VX) Output Hi-Z Output Remarks 1. STB = L: SW1 = ON STB = H: SW1 = OFF 2. STB = H is acknowledged at timing [1]. 3. The display data latch is completed at timing [2] and the input voltage (VAMP(IN): gray-scale level voltage) of the output amplifier changes. 10 Data Sheet S15022EJ1V0DS µPD16732D 9. CURRENT CONSUMPTION REDUCTION FUNCTION The µPD16732D has a low power control function (LPC) which can switch the bias current of the output amplifier between two levels and a bias control function (Bcont) which can be used to finely control the bias current. <Low power control function (LPC)> The bias current of the output amplifier can be switched between two levels using this pin. (Bcont: open) LPC = H or open: normal power mode LPC = L: low power mode The VDD2 of static current consumption can be reduced to two thirds of that in normal mode, input a stable DC current (VDD1/VSS1) to this pin. <Bias current control function (Bcont)> It is possible to fine-control the current consumption by using the bias current control function (Bcont pin). When using this function, connect this pin to the stabilized ground potential (VSS2) via an external resistor (REXT). When not using this function, leave this pin open. Figure 9–1. Bias Current Control Function (Bcont) µ PD16732D Bcont LPC REXT H/L VSS2 Refer to the table below for the percentage of current regulation when using the bias current control-function. Table 9–1. Current Consumption Regulation Percentage Compared to Normal Mode VDD1 = 3.3 V VDD2 = 8.7 V LPC = 3.3 V/ 0 V REXT (kΩ) Current Consumption Regulation Percentage (%) LPC = H LPC = L ∞ (Open) 100 65 50 110 70 20 115 80 10 120 85 Remark The above current consumption regulation percentages are not product-characteristic guaranteed as they are based on the results of simulation. Caution Because the low-power and bias-current control functions control the bias current in the output amplifier and regulate the over-all current consumption of the driver IC, when this occurs, the characteristics of the output amplifier will simultaneously change. Therefore, when using these functions, be sure to sufficiently evaluate the picture quality. Data Sheet S15022EJ1V0DS 11 µPD16732D Figure9− −2. Output Wave Form (LPC = L) Bcont = 1.0 kΩ Output Voltage(1 V/div) Bcont = Open Time (4 µs / div) Bcont = 10 kΩ Bcont = 50 kΩ [1] [2] <Test Condition> [1] RL VIN [2] RL RL CL CL RL RL = 1 kΩ + CL = 15 pF CL 12 RL - Data Sheet S15022EJ1V0DS CL CL µPD16732D Figure9− −3. Output Wave Form (LPC = H) Bcont = Open Output Voltage(1 V/div) Bcont = 1.0 kΩ Time (4 µs / div) Bcont = 10 kΩ Bcont = 50 kΩ Data Sheet S15022EJ1V0DS 13 µPD16732D 10. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°C, VSS1 = VSS2 = 0 V) Parameter Symbol Rating Unit Logic Part Supply Voltage VDD1 –0.5 to +4.0 V Driver Part Supply Voltage VDD2 –0.5 to +10.0 V Logic Part Input Voltage VI1 –0.5 to VDD1 + 0.5 V Driver Part Input Voltage VI2 –0.5 to VDD2 + 0.5 V Logic Part Output Voltage VO1 –0.5 to VDD1 + 0.5 V Driver Part Output Voltage VO2 –0.5 to VDD2 + 0.5 V Operating Ambient Temperature TA –10 to +75 °C Storage Temperature Tstg –55 to +125 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = –10 to +75°C, VSS1 = VSS2 = 0 V) Parameter Condition MIN. TYP. MAX. Unit 3.6 V 8.5 9.0 V Logic Part Supply Voltage VDD1 2.3 Driver Part Supply Voltage VDD2 8.0 High-Level Input Voltage VIH 0.7 VDD1 VDD1 V Low-Level Input Voltage VIL 0 0.3 VDD1 V V γ -Corrected Voltage ★ ★ Symbol V0 to V4 0.5 VDD2 VDD2 – 0.1 V5 to V9 VSS2 + 0.1 0.5 VDD2 V Driver Part Output Voltage VO VSS2 + 0.1 VDD2 – 0.1 V Clock Frequency fCLK 2.3 ≤ V VDD1 < 3.0 V 45 MHz 3.0 V ≤ VDD1 ≤ 3.6 V 65 MHz 14 Data Sheet S15022EJ1V0DS µPD16732D Electrical Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.0 to 9.0 V, VSS1 = VSS2 = 0 V, Unless otherwise specified, LPC = H or open, Bcont = open) Parameter ★ Symbol Condition Input Leak Current IIL High-Level Output Voltage VOH STHR (STHL), IOH = 0 mA Low-Level Output Voltage VOL STHR (STHL), IOL = 0 mA γ -Corrected Resistance Rγ V0 to V4 = V5 to V9 = 4.0 V Driver Output Current IVOH VX = 7.0 V, VOUT = 6.5 V MIN. TYP. Unit ±1.0 µA VDD1 – 0.1 8 V 16 Note Note MAX. 0.1 V 32 kΩ –30 µA µA IVOL VX = 1.0 V, VOUT = 1.5 V Output Voltage Deviation ∆VO VDD1 = 3.3 V, VDD2 = 8.5 V ±7 ±20 mV Output Swing Difference ∆VP–P VOUT = 2.0 V, 4.25 V, 6.5 V ±2 ±15 mV Output Voltage Range VO All input data VDD2 – 0.1 V Logic Part Dynamic Current IDD1 VDD1, with no load 1.0 6.0 mA IDD21 VDD2 = 8.0 to 9.0 V, with no load, 3.0 6.0 mA 2.0 4.0 mA 30 Deviation ★ 0.1 Consumption ★ Driver Part Dynamic Current Consumption LPC =H, Bcont = open IDD22 VDD2 = 8.0 to 9.0 V, with no load, LPC =L, Bcont = open Note VX refers to the output voltage of analog output pins S1 to S384. VOUT refers to the voltage applied to analog output pins S1 to S384. Cautions 1. STB cycle is 20 µs, fCLK = 40 MHz 2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 3. Refers to the current consumption per driver when cascades are connected under the assumption of XGA+ single-sided mounting (8 units). Data Sheet S15022EJ1V0DS 15 µPD16732D Switching Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.0 to 9.0 V, VSS1 = VSS2 = 0 V, Unless otherwise specified, LPC = H or open, Bcont = open) Parameter ★ Start Pulse Delay Time Symbol tPLH1 ★ Driver Output Delay Time Condition MIN. TYP. Unit CL = 10 pF, 2.3 ≤ V VDD1 < 3.0 V 10 17 ns CL = 10 pF, 3.0 V ≤ VDD1 ≤ 3.6 V 7 10.5 ns 2.5 5 µs tPLH3 5 8 µs tPHL2 2.5 5 µs tPLH2 CL = 75 pF, RL = 5 kΩ 5 8 µs CI1 Exclude STHR (STHL), TA = 25°C 5 10 pF CI2 STHR (STHL),TA = 25°C 8 10 pF tPHL3 Input Capacitance MAX. <Test Condition> RL1 RL2 RL4 RL3 RL5 RLn = 1 kΩ CLn = 15 pF Output CL1 CL2 CL5 CL4 CL3 Timing Requirements (TA = –10 to +75°°C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 8.0 ns) Parameter ★ ★ ★ Clock Pulse Width Symbol PW CLK Clock Pulse High Period PW CLK(H) Clock Pulse Low Period PW CLK(L) ★ Condition MIN. TYP. MAX. Unit 2.3 ≤ V VDD1 < 3.0 V 22 ns 3.0 V ≤ VDD1 ≤ 3.6 V 15 ns 4 ns 2.3 ≤ V VDD1 < 3.0 V 6 ns 3.0 V ≤ VDD1 ≤ 3.6 V 4 ns Data Setup Time tSETUP1 4 ns Data Hold Time tHOLD1 0 ns Start Pulse Setup Time tSETUP2 4 ns Start Pulse Hold Time tHOLD2 0 ns POL21,POL22 Setup Time tSETUP3 4 ns POL21,POL22 Hold Time tHOLD3 0 ns STB Pulse Width PW STB 2 CLK Last Data Timing tLDT 2 CLK CLK-STB Time tCLK-STB CLK ↑ → STB ↑ 6 ns STB-CLK Time tSTB-CLK STB ↑ → CLK ↑, 9 ns 6 ns VDD1 = 2.3 to 3.6 V STB ↑ → CLK ↑, VDD1 = 3.0 to 3.6 V Time Between STB and Start Pulse tSTB-STH STB ↑ → STHR(STHL) ↑ 2 CLK POL-STB Time tPOL-STB POL ↑ or ↓ → STB ↑ –5 ns STB-POL Time tSTB-POL STB ↓ → POL ↓ or ↑ 6 ns Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1. 16 Data Sheet S15022EJ1V0DS 2 3 1 64 65 66 513 tr 2 tf VDD1 90% 514 10% tSETUP2 tHOLD2 VSS1 tCLK-STB tSTB-CLK VDD1 STHR (1st Dr.) VSS1 tSETUP1 Dn0 to Dn5 INVALID D1 to D6 tHOLD1 D7 to D12 tSETUP3 tSTB-STH D373 to D378 D379 to D384 D385 to D390 VDD1 D3067 to D3072 INVALID D1 to D6 D7 to D12 VSS1 tHOLD3 VDD1 POL21,POL22 INVALID INVALID Data Sheet S15022EJ1V0DS VSS1 tPLH1 VDD1 STHL (1st Dr.) VSS1 tLDT PWSTB VDD1 STB VSS1 tPOL-STB tSTB-POL VDD1 POL VSS1 tPLH3 Hi-Z tPLH2 Switching Characteristic Waveform(R,/L= H) 1 CLK PWCLK(H) Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1. PWCLK(L) PWCLK Target Voltage +0.1 VDD2 6-bit accuracy Sn (VX) 17 µPD16732D tPHL2 tPHL3 µPD16732D 11. RECOMMENDED MOUNTING CONDITIONS The following conditions must be met for mounting conditions of the µPD16732D. For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. µPD16732DN-xxx : TCP (TAB Package) Mounting Condition Thermocompression Mounting Method Condition Soldering Heating tool 300 to 350°C, heating for 2 to 3 seconds : pressure 100g ACF Temporary bonding 70 to 100°C : pressure 3 to 8 kg/cm2: time 3 to 5 (Adhesive sec. Real bonding 165 to 180°C: pressure 25 to 45 kg/cm2: time 30 to Conductive Film) 40 sec. (When using the anisotropy conductive film SUMIZAC1003 of (per solder) Sumitomo Bakelite,Ltd). Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time. 18 Data Sheet S15022EJ1V0DS µPD16732D NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S15022EJ1V0DS 19 µPD16732D Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades On NEC Semiconductor Devices (C11531E) • The information in this document is current as of June, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4