DATA SHEET MOS INTEGRATED CIRCUIT µ PD16772B 480-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALES) DESCRIPTION The µ PD16772B is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as VSS2 + 0.1 V to VDD2 – 0.1 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a clock frequency of 45 MHz when driving at 2.3 V, this driver is applicable to UXGA-standard TFT-LCD panels. FEATURES • CMOS level input (2.3 to 3.6 V) • 480 outputs • Input of 6 bits (gradation data) by 6 dots • Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-DAC) • Logic power supply voltage (VDD1): 2.3 to 3.6 V • Driver power supply voltage (VDD2): 8.5 V ± 0.5 V • Output dynamic range: VSS2 + 0.1 V to VDD2 – 0.1 V • High-speed data transfer: fCLK = 45 MHz (internal data transfer speed when operating at VDD1 = 2.3 V) • Apply for dot-line inversion, n-line inversion and column line inversion • Output voltage polarity inversion function (POL) • Display data inversion function (POL21, POL22) • Current consumption reduction function (LPC, Bcont) ORDERING INFORMATION Part Number Package µ PD16772BN-xxx TCP (TAB package) Remark The TCP’s external shape is customized. To order the required shape, so please contact one of our sales representatives. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15996EJ1V0DS00 (1st edition) Date Published July 2002 NS CP (K) Printed in Japan The mark ! shows major revised points. © 2002 µPD16772B ★ 1. BLOCK DIAGRAM STHR R,/L CLK STB STHL VDD1 VSS1 80-bit bidirectional shift register C1 C2 C79 D00 to D05 D10 to D15 D20 to D25 D30 to D35 D40 to D45 D50 to D55 POL21, POL22 C80 Data register Latch POL VDD2 Level shifter VSS2 V0 to V9 D/A converter Voltage follower output LPC Bcont S1 S2 S3 S480 Remark /xxx indicates active low signal. ★ 2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER S1 V5 S479 5 V0 V4 S2 Multiplexer 6-bit D/A converter 5 V9 POL 2 Data Sheet S15996EJ1V0DS S480 µPD16772B 3. PIN CONFIGURATION (µPD16772B) (Copper Foil Surface, Face-up) STHL D55 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 D30 VDD1 R,/L V9 V8 V7 V6 V5 VDD2 VSS2 Bcont V4 V3 V2 V1 V0 VSS1 LPC CLK STB POL POL21 POL22 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 STHR Remark S480 S479 S478 S477 Copper Foil Surface S4 S3 S2 S1 This figure does not specify the TCP package. Data Sheet S15996EJ1V0DS 3 µPD16772B ★ 4. PIN FUNCTIONS (1/2) Pin Symbol Pin Name S1 to S480 Driver D00 to D05 Display data I/O Description Output The D/A converted 64-gray-scale analog voltage is output. Input The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 D10 to D15 dots (2 pixels). D20 to D25 DX0: LSB, DX5: MSB D30 to D35 D40 to D45 D50 to D55 R,/L Shift direction control Input These refer to the start pulse I/O pins when driver ICs are connected in cascade. The shift directions of the shift registers are as follows. R,/L = H: STHR input, S1 → S480, STHL output R,/L = L: STHL input, S480 → S1, STHR output STHR Right shift start pulse I/O These refer to the start pulse I/O pins when driver ICs are connected in cascade. Fetching of display data starts when H is read at the rising edge of CLK. R,/L = H (right shift): STHR input, STHL output STHL Left shift start pulse I/O R,/L = L (left shift): STHL input, STHR output A high level should be input as the pulse of one cycle of the clock signal. If the start pulse input is more than 2 CLK, the fist 1 CLK of the high-level input is valid. CLK Shift clock Input Refers to the shift register’s shift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 80th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. If 82 clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB’s rising edge. STB Latch Input The contents of the data register are transferred to the latch circuit at the rising edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL Polarity Input POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to V9 as the reference supply. POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to V4 as the reference supply. S2n–1 indicates the odd output: and S2n indicates the even output. Input of the POL signal is allowed the setup time(tPOL-STB) with respect to STB’s rising edge. POL21, Data inversion Input POL22 Data inversion can invert when display data is loaded. POL21, POL22 = H: Data inversion loads display data after inverting it. POL21, POL22 = L: Data inversion does not invert input data. POL21: D00 to D05, D10 to D15, D20 to D25 POL22: D30 to D35, D40 to D45, D50 to D55 LPC Low power control Input The current consumption of VDD2 is lowered by controlling the constant current source of the output amplifier. This pin is pulled up to the VDD1 power supply inside the IC. For details, see 9. CURRENT CONSUMPTION REDUCTION FUNCTION. Bcont Bias control Input This pin can be used to finely control the bias current inside the output amplifier. When this fine-control function is not required, leave this pin open. For details, see 9. CURRENT CONSUMPTION REDUCTION FUNCTION. 4 Data Sheet S15996EJ1V0DS µPD16772B (2/2) Pin Symbol V0 to V9 Pin Name γ -corrected power I/O − supplies Description Input the γ -corrected power supplies from outside by using operational amplifier. Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. VDD2 − 0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 0.5 VDD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V VDD1 Logic power supply − 2.3 to 3.6 V VDD2 Driver power supply − 8.5 V ± 0.5 V VSS1 Logic ground − Grounding VSS2 Driver ground − Grounding Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down (Simultaneous power application to VDD2 and V0 to V9 is possible.). 2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.01 µF is also advised between the γ -corrected power supply terminals (V0, V1, V2,....., V9) and VSS2. Data Sheet S15996EJ1V0DS 5 µPD16772B 5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE The µ PD16772B incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD’s counter electrode (common electrode) voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel γ -compensated voltages to V0’ to V63’ and V0” to V63” is almost equivalent. For the 2 sets of five γ -compensated power supplies, V0 to V4 and V5 to V9, respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine gray scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the γ -compensated power supplies V1 to V3 and V6 to V8. Figure 5–1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2, common electrode potential VCOM, and γ -corrected voltages V0 to V9 and the input data. Be sure to maintain the voltage relationships as follows. VDD2 − 0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 0.5 VDD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V Figure 5–2 shows γ -corrected power supply voltage and ladder resistors ratio and Figure 5–3 shows the relationship between the input data and the output voltage and the resistance values of the resistor strings. Figure 5–1. Relationship between Input Data and γ -corrected Power Supplies VDD2 0.1 V V0 16 V1 16 V2 V3 16 15 V4 0.5 VDD2 Split interval V5 15 V6 16 V7 16 V8 16 V9 0.1 V VSS2 00 6 10 20 Input data (HEX) Data Sheet S15996EJ1V0DS 30 3F µPD16772B Figure 5–2. γ -corrected Power Supply Voltage and Ladder Resistors Ratio V0 V0 ’ V5 r0 V63’’ r62 V1 ’ V62’’ r61 r1 V61’’ V2’ r60 r2 V60’’ V3’ r59 r3 r49 r14 V15’ V49’’ r48 r15 V16’ V1 V48’’ V6 r47 r16 V17’ V47’’ r46 r17 r17 r46 V47’ V17’’ r16 r47 V48’ V3 V16’’ V8 r15 r48 V49’ V15’’ r14 r49 r2 r60 V2’’ V61’ r1 r61 V62’ V1’’ r62 V4 r0 V63’ V9 V0’’ rn r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r48 r49 r50 r51 r52 r53 r54 r55 r56 r57 r58 r59 r60 r61 r62 Value 722 628 628 596 596 502 470 454 454 408 330 298 266 266 236 220 204 204 172 156 156 142 142 142 142 126 126 110 110 110 110 110 110 110 94 94 94 110 110 94 110 94 110 94 110 126 110 110 110 126 126 126 142 142 126 188 188 220 220 236 360 564 2022 Ratio (1) 7.68 6.68 6.68 6.34 6.34 5.34 5.00 4.83 4.83 4.34 3.51 3.17 2.83 2.83 2.51 2.34 2.17 2.17 1.83 1.66 1.66 1.51 1.51 1.51 1.51 1.34 1.34 1.17 1.17 1.17 1.17 1.17 1.17 1.17 1.00 1.00 1.00 1.17 1.17 1.00 1.17 1.00 1.17 1.00 1.17 1.34 1.17 1.17 1.17 1.34 1.34 1.34 1.51 1.51 1.34 2.00 2.00 2.34 2.34 2.51 3.83 6.00 21.51 Ratio (2) 0.0454 0.0395 0.0395 0.0375 0.0375 0.0315 0.0295 0.0285 0.0285 0.0256 0.0207 0.0187 0.0167 0.0167 0.0148 0.0138 0.0128 0.0128 0.0108 0.0098 0.0098 0.0089 0.0089 0.0089 0.0089 0.0079 0.0079 0.0069 0.0069 0.0069 0.0069 0.0069 0.0069 0.0069 0.0059 0.0059 0.0059 0.0069 0.0069 0.0059 0.0069 0.0059 0.0069 0.0059 0.0069 0.0079 0.0069 0.0069 0.0069 0.0079 0.0079 0.0079 0.0089 0.0089 0.0079 0.0118 0.0118 0.0138 0.0138 0.0148 0.0226 0.0354 0.1271 rtotal 15912 169.28 1.0000 Remark The resistance ratio1 is a relative ratio in the case of setting the minimum resistance value to 1. The resistance ratio2 is a relative ratio in the case of setting the total resistance to 1. Caution There is no connection between V4 and V5 terminal in the chip. Data Sheet S15996EJ1V0DS 7 µPD16772B Figure 5− −3. Relationship between Input Data and Output Voltage (POL21, POL22 = L) ★ (Output Voltage 1) VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 (Output Voltage 2) 0.5 VDD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V Input Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 8 V0' V1' V2' V3' V4' V5' V6' V7' V8' V9' V10' V11' V12' V13' V14' V15' V16' V17' V18' V19' V20' V21' V22' V23' V24' V25' V26' V27' V28' V29' V30' V31' V32' V33' V34' V35' V36' V37' V38' V39' V40' V41' V42' V43' V44' V45' V46' V47' V48' V49' V50' V51' V52' V53' V54' V55' V56' V57' V58' V59' V60' V61' V62' V63' Output Voltage1 V0 V1+(V0-V1)× 6352 V1+(V0-V1)× 5724 V1+(V0-V1)× 5096 V1+(V0-V1)× 4500 V1+(V0-V1)× 3904 V1+(V0-V1)× 3402 V1+(V0-V1)× 2932 V1+(V0-V1)× 2478 V1+(V0-V1)× 2024 V1+(V0-V1)× 1616 V1+(V0-V1)× 1286 V1+(V0-V1)× 988 V1+(V0-V1)× 722 V1+(V0-V1)× 456 V1+(V0-V1)× 220 V1 V2+(V1-V2)× 2058 V2+(V1-V2)× 1854 V2+(V1-V2)× 1682 V2+(V1-V2)× 1526 V2+(V1-V2)× 1370 V2+(V1-V2)× 1228 V2+(V1-V2)× 1086 V2+(V1-V2)× 944 V2+(V1-V2)× 802 V2+(V1-V2)× 676 V2+(V1-V2)× 550 V2+(V1-V2)× 440 V2+(V1-V2)× 330 V2+(V1-V2)× 220 V2+(V1-V2)× 110 V2 V3+(V2-V3)× 1570 V3+(V2-V3)× 1460 V3+(V2-V3)× 1366 V3+(V2-V3)× 1272 V3+(V2-V3)× 1178 V3+(V2-V3)× 1068 V3+(V2-V3)× 958 V3+(V2-V3)× 864 V3+(V2-V3)× 754 V3+(V2-V3)× 660 V3+(V2-V3)× 550 V3+(V2-V3)× 456 V3+(V2-V3)× 346 V3+(V2-V3)× 220 V3+(V2-V3)× 110 V3 V4+(V3-V4)× 4786 V4+(V3-V4)× 4660 V4+(V3-V4)× 4534 V4+(V3-V4)× 4408 V4+(V3-V4)× 4266 V4+(V3-V4)× 4124 V4+(V3-V4)× 3998 V4+(V3-V4)× 3810 V4+(V3-V4)× 3622 V4+(V3-V4)× 3402 V4+(V3-V4)× 3182 V4+(V3-V4)× 2946 V4+(V3-V4)× 2586 V4+(V3-V4)× 2022 V4 / / / / / / / / / / / / / / / 7074 7074 7074 7074 7074 7074 7074 7074 7074 7074 7074 7074 7074 7074 7074 / / / / / / / / / / / / / / / 2262 2262 2262 2262 2262 2262 2262 2262 2262 2262 2262 2262 2262 2262 2262 / / / / / / / / / / / / / / / 1680 1680 1680 1680 1680 1680 1680 1680 1680 1680 1680 1680 1680 1680 1680 / / / / / / / / / / / / / / 4896 4896 4896 4896 4896 4896 4896 4896 4896 4896 4896 4896 4896 4896 V0'' V1'' V2'' V3'' V4'' V5'' V6'' V7'' V8'' V9'' V10'' V11'' V12'' V13'' V14'' V15'' V16'' V17'' V18'' V19'' V20'' V21'' V22'' V23'' V24'' V25'' V26'' V27'' V28'' V29'' V30'' V31'' V32'' V33'' V34'' V35'' V36'' V37'' V38'' V39'' V40'' V41'' V42'' V43'' V44'' V45'' V46'' V47'' V48'' V49'' V50'' V51'' V52'' V53'' V54'' V55'' V56'' V57'' V58'' V59'' V60'' V61'' V62'' V63'' Data Sheet S15996EJ1V0DS Output Voltage2 V9 V9+(V8-V9)× 722 V9+(V8-V9)× 1350 V9+(V8-V9)× 1978 V9+(V8-V9)× 2574 V9+(V8-V9)× 3170 V9+(V8-V9)× 3672 V9+(V8-V9)× 4142 V9+(V8-V9)× 4596 V9+(V8-V9)× 5050 V9+(V8-V9)× 5458 V9+(V8-V9)× 5788 V9+(V8-V9)× 6086 V9+(V8-V9)× 6352 V9+(V8-V9)× 6618 V9+(V8-V9)× 6854 V8 V8+(V7-V8)× 204 V8+(V7-V8)× 408 V8+(V7-V8)× 580 V8+(V7-V8)× 736 V8+(V7-V8)× 892 V8+(V7-V8)× 1034 V8+(V7-V8)× 1176 V8+(V7-V8)× 1318 V8+(V7-V8)× 1460 V8+(V7-V8)× 1586 V8+(V7-V8)× 1712 V8+(V7-V8)× 1822 V8+(V7-V8)× 1932 V8+(V7-V8)× 2042 V8+(V7-V8)× 2152 V7 V7+(V6-V7)× 110 V7+(V6-V7)× 220 V7+(V6-V7)× 314 V7+(V6-V7)× 408 V7+(V6-V7)× 502 V7+(V6-V7)× 612 V7+(V6-V7)× 722 V7+(V6-V7)× 816 V7+(V6-V7)× 926 V7+(V6-V7)× 1020 V7+(V6-V7)× 1130 V7+(V6-V7)× 1224 V7+(V6-V7)× 1334 V7+(V6-V7)× 1460 V7+(V6-V7)× 1570 V6 V6+(V5-V6)× 110 V6+(V5-V6)× 236 V6+(V5-V6)× 362 V6+(V5-V6)× 488 V6+(V5-V6)× 630 V6+(V5-V6)× 772 V6+(V5-V6)× 898 V6+(V5-V6)× 1086 V6+(V5-V6)× 1274 V6+(V5-V6)× 1494 V6+(V5-V6)× 1714 V6+(V5-V6)× 1950 V6+(V5-V6)× 2310 V6+(V5-V6)× 2874 V5 / / / / / / / / / / / / / / / 7074 7074 7074 7074 7074 7074 7074 7074 7074 7074 7074 7074 7074 7074 7074 / / / / / / / / / / / / / / / 2262 2262 2262 2262 2262 2262 2262 2262 2262 2262 2262 2262 2262 2262 2262 / / / / / / / / / / / / / / / 1680 1680 1680 1680 1680 1680 1680 1680 1680 1680 1680 1680 1680 1680 1680 / / / / / / / / / / / / / / 4896 4896 4896 4896 4896 4896 4896 4896 4896 4896 4896 4896 4896 4896 µPD16772B 6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format : 6 bits x 2 RGBs (6 dots) Input width : 36 bits (2-pixel data) (1) R,/L = H (Right shift) Output S1 S2 S3 S4 """ S479 S480 Data D00 to D05 D10 to D15 D20 to D25 D30 to D35 """ D40 to D45 D50 to D55 (2) R,/L = L (Left shift) Output S1 S2 S3 S4 """ S479 S480 Data D00 to D05 D10 to D15 D20 to D25 D30 to D35 """ D40 to D45 D50 to D55 Note Note S2n–1 S2n L V0 to V4 V5 to V9 H V5 to V9 V0 to V4 POL Note S2n–1 (Odd output), S2n (Even output) ★ 7. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM The output voltage is written to the LCD panel synchronized with the STB falling edge. STB POL S2n-1 Selected voltage V0 to V4 Selected voltage V5 to V9 Selected voltage V0 to V4 S2n Selected voltage V0 to V4 Selected voltage V5 to V9 Hi-Z Hi-Z Data Sheet S15996EJ1V0DS Selected voltage V5 to V9 Hi-Z 9 µPD16772B ★ 8. RELATIONSHIP BETWEEN STB, CLK AND OUTPUT WAVEFORM Figure 8–1. Output Circuit Block Diagram Output Amp − DAC + SW1 Sn (VX) VAMP(IN) Figure 8–2. Output Circuit Timing Waveform [1] [1'] CLK tSTB-CLK STB SW1: OFF VAMP(IN) Sn (VX) Hi-Z The output voltage is written to the LCD panel synchronized with the STB falling edge. STB = H is loaded with the rising edge of CLK [1]. However, when not satisfying the specification of tSTB-CLK, STB = H is loaded with the rising edge of the next CLK [1']. Latch operation of display data is completed with the falling edge of the next CLK which loaded STB = H. Therefore, in order to complete latch operation of display data, it is necessary to input at least 2 CLK in STB = H period. Besides, after loading STB = H to the timing of [1], it is necessary to continue inputting CLK. 10 Data Sheet S15996EJ1V0DS µPD16772B 9. CURRENT CONSUMPTION REDUCTION FUNCTION The µ PD16772B has a low power control function (LPC) which can switch the bias current of the output amplifier between two levels and a bias control function (Bcont) which can be used to finely control the bias current. • Low Power Control Function (LPC) The bias current of the output amplifier can be switched between two levels using this pin (Bcont: Open). LPC = H or Open: Low power mode LPC = L: Normal power mode The VDD2 of static current consumption can be reduced to two thirds of that in normal mode. Input a stable DC current (VDD1/VSS1) to this pin. • Bias Current Control Function (Bcont) It is possible to fine-control the current consumption by using the bias current control function (Bcont pin). When using this function, connect this pin to the stabilized ground potential (VSS2) via an external resistor (REXT). When not using this function, leave this pin open. Figure 9–1. Bias Current Control Function (Bcont) µ PD16772B Bcont LPC REXT H/L VSS2 Refer to the table below for the percentage of current regulation when using the bias current control function. Table 9–1. Current Consumption Regulation Percentage Compared to Normal Mode (VDD1 = 3.3 V, VDD2 = 8.7 V) REXT (kΩ) Current Consumption Regulation Percentage (%) LPC = L LPC = H/Open ∞ (Open) 100 65 50 120 80 20 140 100 0 240 210 Remark The above current consumption regulation percentages are not product-characteristic guaranteed as they re based on the results of simulation. Caution Because the low-power and bias-current control functions control the bias current in the output amplifier and regulate the over-all current consumption of the driver IC, when this occurs, the characteristics of the output amplifier will simultaneously change. Therefore, when using these functions, be sure to sufficiently evaluate the picture quality. Data Sheet S15996EJ1V0DS 11 µPD16772B 10. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°C, VSS1 = VSS2 = 0 V) Parameter Symbol Rating Unit –0.5 to +4.0 V –0.5 to +10.0 V –0.5 to VDD1 + 0.5 V Logic Part Supply Voltage VDD1 Driver Part Supply Voltage VDD2 Logic Part Input Voltage VI1 Driver Part Input Voltage VI2 –0.5 to VDD2 + 0.5 V Logic Part Output Voltage VO1 –0.5 to VDD1 + 0.5 V Driver Part Output Voltage VO2 –0.5 to VDD2 + 0.5 V Operating Ambient Temperature TA –10 to +75 °C Storage Temperature Tstg –55 to +125 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = –10 to +75°C, VSS1 = VSS2 = 0 V) Parameter ★ Symbol Condition MIN. TYP. MAX. Unit 3.6 V 8.5 9.0 V Logic Part Supply Voltage VDD1 2.3 Driver Part Supply Voltage VDD2 8.0 High-Level Input Voltage VIH 0.7 VDD1 VDD1 V Low-Level Input Voltage VIL γ -Corrected Voltage V0 to V4 0 0.5 VDD2 0.3 VDD1 VDD2 − 0.1 V V5 to V9 0.1 0.5 VDD2 V Driver Part Output Voltage VO 0.1 VDD2 – 0.1 V Clock Frequency fCLK 45 MHz 12 VDD1 = 2.3 V Data Sheet S15996EJ1V0DS V µPD16772B Electrical Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.5 V ± 0.5 V, VSS1 = VSS2 = 0 V, unless otherwise specified, the input level is defined to be LPC = L, Bcont = Open) Parameter Symbol Input Leak Current Condition MIN. TYP. Except LPC IIL LPC T.B.D. STHR (STHL), IOH = 0 mA MAX. Unit ±1.0 T.B.D. µA µA High-Level Output Voltage VOH VDD1 – 0.1 Low-Level Output Voltage VOL STHR (STHL), IOL = 0 mA γ -Corrected Resistance Rγ V0 to V4 = V5 to V9 = 4.0 V Driver Output Current IVOH VX = 7.0 V, VOUT = 6.5 V IVOL VX = 1.0 V, VOUT = 1.5 V Output Voltage Deviation ∆VO TA = 25°C, VDD1 = 3.3 V, VDD2 = 8.5 V, ±7 ±20 mV Output Swing Difference ∆VP–P VOUT = 2.0 V, 4.25 V, 6.5 V ±2 ±15 mV IDD1 VDD1 1.0 7.5 mA IDD2 VDD2, with no load 3.5 7.5 mA T.B.D. V T.B.D. 0.1 V T.B.D. kΩ –30 µA Note Note µA 30 Deviation Logic Part Dynamic Current Consumption Driver Part Dynamic Current Consumption Note VX refers to the output voltage of analog output pins S1 to S480. VOUT refers to the voltage applied to analog output pins S1 to S480. ★ Remark T.B.D. (To be determined.) Cautions 1. fSTB = 50 kHz, fCLK = 40 MHz. 2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 3. Refers to the current consumption per driver when cascades are connected under the assumption of UXGA single-sided mounting (10 units). Switching Characteristics (TA = –10 to +75°°C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.5 V ± 0.5 V, VSS1 = VSS2 = 0 V, unless otherwise specified, the input level is defined to be LPC = L, Bcont = Open) Parameter Symbol Start Pulse Delay Time TYP. MAX. Unit CL = 10 pF 10 20 ns 10 20 ns CL = 75 pF, RL = 5 kΩ 2.5 5 µs tPLH3 5 8 µs tPHL2 2.5 5 µs tPLH1 Condition MIN. tPHL1 Driver Output Delay Time tPLH2 5 8 µs CI1 STHR (STHL) excluded, TA = 25°C 5 10 pF CI2 STHR (STHL), TA = 25°C 8 10 pF tPHL3 Input Capacitance <Test Condition> RL1 RL2 RL3 RL4 Measurement point RL5 Output CL1 CL2 CL3 CL4 CL5 GND RLn = 1 kΩ CLn = 15 pF Data Sheet S15996EJ1V0DS 13 µPD16772B Timing Requirements (TA = –10 to +75°°C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns) Parameter Symbol Clock Pulse Width PW CLK Clock Pulse High Period PW CLK(H) Clock Pulse Low Period PW CLK(L) Condition MIN. TYP. 22 MAX. Unit ns 4 ns 2.3 V ≤ VDD1 < 3.0 V 7 ns 3.0 V ≤ VDD1 ≤ 3.6 V 4 ns Data Setup Time tSETUP1 3 ns Data Hold Time tHOLD1 0 ns Start Pulse Setup Time tSETUP2 3 ns Start Pulse Hold Time tHOLD2 0 ns POL21, POL22 Setup Time tSETUP3 POL21, POL22 Hold Time tHOLD3 3 ns 2.3 V ≤ VDD1 < 3.0 V 1 ns 3.0 V ≤ VDD1 ≤ 3.6 V 0 ns STB Pulse Width PW STB 2 CLK Last Data Timing tLDT 2 CLK CLK-STB Time tCLK-STB CLK ↑ → STB ↑ 6 ns STB-CLK Time tSTB-CLK STB ↑ → CLK ↑ 2.3 V ≤ VDD1 < 3.0 V 14 ns STB ↑ → CLK ↑ 3.0 V ≤ VDD1 ≤ 3.6 V 6 ns Time Between STB and Start Pulse tSTB-STH STB ↑ → STHR(STHL) ↑ 2 CLK POL-STB Time tPOL-STB POL ↑ or ↓ → STB ↑ –5 ns STB-POL Time tSTB-POL STB ↓ → POL ↓ or ↑ 6 ns Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1. 14 Data Sheet S15996EJ1V0DS 2 3 1 64 65 66 513 tr 2 tf VDD1 90% 514 10% tSETUP2 tHOLD2 VSS1 tCLK-STB tSTB-CLK VDD1 STHR (1st Dr.) VSS1 tSETUP1 Dn0 to Dn5 INVALID D1 to D6 D7 to D12 tSETUP3 POL21, POL22 tHOLD1 tSTB-STH D373 to D378 D379 to D384 D385 to D390 VDD1 D3067 to D3072 INVALID D1 to D6 D7 to D12 VSS1 tHOLD3 VDD1 INVALID INVALID Data Sheet S15996EJ1V0DS VSS1 tPLH1 tPHL1 VDD1 STHL (1st Dr.) VSS1 tLDT PWSTB VDD1 STB VSS1 tPOL-STB tSTB-POL VDD1 POL VSS1 tPLH3 Hi-Z tPLH2 Sn (VX) ★ Switching Characteristic Waveform (R,/L = H) 1 CLK PWCLK(H) Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1. PWCLK(L) PWCLK Target Voltage ± 0.1 VDD2 6-bit accuracy tPHL3 15 µPD16772B tPHL2 µPD16772B 11. RECOMMENDED MOUNTING CONDITIONS The following conditions must be met for mounting conditions of the µ PD16772B. For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. µ PD16772BN-xxx: TCP (TAB Package) Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350°C, heating for 2 to 3 seconds : pressure 100 g (per solder) ACF Temporary bonding 70 to 100°C : pressure 3 to 8 kg/cm2: time 3 to 5 (Adhesive sec. Real bonding 165 to 180°C: pressure 25 to 45 kg/cm2: time 30 to Conductive Film) 40 sec. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd). Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time. 16 Data Sheet S15996EJ1V0DS µPD16772B [MEMO] Data Sheet S15996EJ1V0DS 17 µPD16772B [MEMO] 18 Data Sheet S15996EJ1V0DS µPD16772B NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S15996EJ1V0DS 19 µPD16772B Reference Documents NEC Semiconductor Device Reliability/Quality Control System(C10983E) Quality Grades On NEC Semiconductor Devices(C11531E) • The information in this document is current as of July 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. 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"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4