DATA SHEET MOS INTEGRATED CIRCUIT µ PD16770A 420-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALES) DESCRIPTION The µ PD16770A is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as VSS2 + 0.1 V to VDD2 – 0.1 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a clock frequency of 45 MHz when driving at 2.3 V, this driver is applicable to SXGA + standard TFT-LCD panels. FEATURES • CMOS level input (2.3 to 3.6 V) • 420 Outputs • Input of 6 bits (gray-scale data) by 6 dots • Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter • Logic power supply voltage (VDD1): 2.3 to 3.6 V • Driver power supply voltage (VDD2): 8.5 ± 0.5 V • Output dynamic range VSS2 + 0.1 V to VDD2 – 0.1 V • High-speed data transfer: fCLK = 45 MHz (internal data transfer speed when operating at VDD1 = 2.3 V) • Apply for dot-line inversion, n-line inversion and column line inversion • Output Voltage polarity inversion function (POL) • Display data inversion function (capable of controlling by each input port) (POL21, POL22) • Current consumption control function (LPC, HPC, Bcont) • Slim chip ORDERING INFORMATION Part Number µ PD16770AN -××× Package TCP (TAB package) Remark The TCP’s external shape is customized. To order the required shape, please contact one of our sales representatives. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15261EJ1V0DS00 (1st edition) Date Published May 2001 NS CP(K) Printed in Japan The mark ★ shows major revised points. © 2001 µ PD16770A 1. BLOCK DIAGRAM STHR R,/L CLK STB STHL VDD1 VSS1 70-bit bidirectional shift register C1 C2 C69 D00 - D05 D10 - D15 D20 - D25 D30 - D35 D40 - D45 D50 - D55 POL21, POL22 C70 Data register Latch POL VDD2 Level shifter VSS2 V0 - V9 D/A converter HPC LPC Bcont Voltage follower output S1 S2 S3 S420 Remark /xxx indicates active low signal. 2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER S1 V5 S419 5 V0 V4 S2 Multiplexer 6-bit D/A converter 5 V9 POL 2 Data Sheet S15261EJ1V0DS S420 µ PD16770A 3. PIN CONFIGURATION (µPD16770AN-xxx: Copper foil surface, Face-up) STHL D55 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 D30 VDD1 R,/L V9 V8 V7 V6 V5 VDD2 VSS2 Bcont V4 V3 V2 V1 V0 HPC VSS1 LPC CLK STB POL POL21 POL22 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 STHR S420 S419 S418 S417 Copper foil surface S4 S3 S2 S1 Remark This figure does not specify the TCP package. Data Sheet S15261EJ1V0DS 3 µ PD16770A 4. PIN FUNCTIONS (1/2) Pin Symbol Pin Name Description S1 to S420 Driver output The D/A converted 64-gray-scale analog voltage is output. D00 to D05 Display data input The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). D10 to D15 DX0: LSB, DX5: MSB D20 to D25 D30 to D35 D40 to D45 D50 to D55 R,/L Shift direction control These refer to the start pulse input/output pins when driver ICs are connected in input cascade. The shift directions of the shift registers are as follows. R,/L = H: STHR input, S1 → S420, STHL output R,/L = L: STHL input, S420 → S1, STHR output STHR Right shift start pulse input/output STHL Left shift start pulse input/output CLK Shift clock input STB Latch input These refer to the start pulse I/O pins when driver ICs are connected in cascade. Fetching of display data starts when H is read at the rising edge of CLK. R,/L = H (right shift): STHR input, STHL output R,/L = L (left shift): STHL input, STHR output The start pulse width (H level) for next-level drivers is 1 CLK. Refers to the shift register’s shift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 70 th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. If 72 clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB’s rising edge. The contents of the data register are transferred to the latch circuit at the rising edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL Polarity input POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to V9 as the reference supply. POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to V4 as the reference supply. S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge. POL21, Data inversion POL22 Data inversion can invert when display data is loaded. POL21, POL22 = H: Data inversion loads display data after inverting it. POL21, POL22 = L: Data inversion does not invert input data. POL21: D00 to D05, D10 to D15, D20to D25 POL22: D30 to D35, D40 to D45, D50 to D55 LPC Low power control input Controls the write function of the driver section by digitally controlling the bypass current of the output amplifier. HPC High power control input This pin is pulled up to the VDD1 power supply inside the IC. Refer to 9. CURRENT CONSUMPTION CONTROL FUNCTION. 4 Data Sheet S15261EJ1V0DS µ PD16770A (2/2) Pin Symbol Bcont Pin Name Bias control Description This pin can be used to finely control the bias current inside the output amplifier. When this fine-control function is not required, leave this pin open. Refer to 9. CURRENT CONSUMPTION CONTROL FUNCTION. V0 to V9 γ -corrected power Input the γ -corrected power supplies from outside by using operational amplifier. supplies Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 > 0.5 V DD2 > V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V VDD1 Logic power supply 2.3 to 3.6 V VDD2 Driver power supply 8.5 V ± 0.5 V VSS1 Logic ground Grounding VSS2 Driver ground Grounding Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down. 2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.01 µF is also recommended between the γ -corrected power supply terminals (V0, V1, V2, ···, V9) and VSS2. Data Sheet S15261EJ1V0DS 5 µ PD16770A 5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE The µ PD16770A incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD’s counter electrode (common electrode) voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel γ -compensated voltages to V0’ to V63’ and V0” to V63” is almost equivalent. For the 2 sets of five γ -compensated power supplies, V0 to V4 and V5 to V9, respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine gray scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the γ -compensated power supplies V1 to V3 and V6 to V8. Figure 5−1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2, common electrode potential VCOM, and γ -corrected voltages V0 to V9 and the input data. Be sure to maintain the voltage relationships of VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 > 0.5 VDD2 > V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V. Figures 5−2 and 5−3 show the relationship between the input data and the output data and the resistance values of the resistor strings. Figure 5− −1. Relationship between Input Data and γ - corrected Power Supplies VDD2 0.1 V V0 16 V1 16 V2 16 V3 15 V4 VCOM Split interval V5 15 V6 16 V7 16 V8 16 V9 0.1 V VSS2 00 10 20 Input Data (HEX) 6 Data Sheet S15261EJ1V0DS 30 3F µ PD16770A Figure 5− −2. Relationship between Input Data and Output Voltage VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 > 0.5 VDD2, POL21, POL22 = L V0 V0' r0 V1' r1 V2' r2 V3' r3 r14 V15' r15 V1 V16' r16 V17' r17 r46 r47 V47' V48' V3 r48 V49' r49 r60 r61 V61' V62' r62 V4 V63' Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0' V1' V2' V3' V4' V5' V6' V7' V8' V9' V10' V11' V12' V13' V14' V15' V16' V17' V18' V19' V20' V21' V22' V23' V24' V25' V26' V27' V28' V29' V30' V31' V32' V33' V34' V35' V36' V37' V38' V39' V40' V41' V42' V43' V44' V45' V46' V47' V48' V49' V50' V51' V52' V53' V54' V55' V56' V57' V58' V59' V60' V61' V62' V63' Output Voltage V0 V1+(V0-V1)× 6500 V1+(V0-V1)× 5800 V1+(V0-V1)× 5100 V1+(V0-V1)× 4400 V1+(V0-V1)× 3700 V1+(V0-V1)× 3350 V1+(V0-V1)× 3000 V1+(V0-V1)× 2650 V1+(V0-V1)× 2300 V1+(V0-V1)× 1950 V1+(V0-V1)× 1600 V1+(V0-V1)× 1250 V1+(V0-V1)× 900 V1+(V0-V1)× 600 V1+(V0-V1)× 300 V1 V2+(V1-V2)× 2100 V2+(V1-V2)× 1900 V2+(V1-V2)× 1700 V2+(V1-V2)× 1500 V2+(V1-V2)× 1300 V2+(V1-V2)× 1150 V2+(V1-V2)× 1000 V2+(V1-V2)× 850 V2+(V1-V2)× 700 V2+(V1-V2)× 600 V2+(V1-V2)× 500 V2+(V1-V2)× 400 V2+(V1-V2)× 300 V2+(V1-V2)× 200 V2+(V1-V2)× 100 V2 V3+(V2-V3)× 1550 V3+(V2-V3)× 1450 V3+(V2-V3)× 1350 V3+(V2-V3)× 1250 V3+(V2-V3)× 1150 V3+(V2-V3)× 1050 V3+(V2-V3)× 950 V3+(V2-V3)× 850 V3+(V2-V3)× 750 V3+(V2-V3)× 650 V3+(V2-V3)× 550 V3+(V2-V3)× 450 V3+(V2-V3)× 350 V3+(V2-V3)× 250 V3+(V2-V3)× 150 V3 V4+(V3-V4)× 4100 V4+(V3-V4)× 3950 V4+(V3-V4)× 3800 V4+(V3-V4)× 3650 V4+(V3-V4)× 3500 V4+(V3-V4)× 3350 V4+(V3-V4)× 3200 V4+(V3-V4)× 2950 V4+(V3-V4)× 2700 V4+(V3-V4)× 2450 V4+(V3-V4)× 2150 V4+(V3-V4)× 1850 V4+(V3-V4)× 1550 V4+(V3-V4)× 1100 V4 / / / / / / / / / / / / / / / 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 / / / / / / / / / / / / / / / 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 / / / / / / / / / / / / / / / 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 / / / / / / / / / / / / / / 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 (Ω) rn r0 1150 r1 700 r2 700 r3 700 r4 700 r5 350 r6 350 r7 350 r8 350 r9 350 r10 350 r11 350 r12 350 r13 300 r14 300 r15 300 r16 200 r17 200 r18 200 r19 200 r20 200 r21 150 r22 150 r23 150 r24 150 r25 100 r26 100 r27 100 r28 100 r29 100 r30 100 r31 100 r32 100 r33 100 r34 100 r35 100 r36 100 r37 100 r38 100 r39 100 r40 100 r41 100 r42 100 r43 100 r44 100 r45 100 r46 100 r47 150 r48 150 r49 150 r50 150 r51 150 r52 150 r53 150 r54 150 r55 250 r56 250 r57 250 r58 300 r59 300 r60 300 r61 450 r62 1100 rtotal 15850 Caution There is no connection between V4 and V5 terminal in the chip. Data Sheet S15261EJ1V0DS 7 µ PD16770A Figure 5− −3. Relationship between Input Data and Output Voltage 0.5 VDD2 > V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V, POL21, POL22 = L V5 V63'' r62 V62'' r61 V61'' r60 V60'' r59 r49 V49'' r48 V48'' V6 r47 V47'' r46 r17 V17'' r16 V16'' V8 r15 V15'' r14 r2 V2'' r1 V1'' r0 V0'' V9 Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0'' V1'' V2'' V3'' V4'' V5'' V6'' V7'' V8'' V9'' V10'' V11'' V12'' V13'' V14'' V15'' V16'' V17'' V18'' V19'' V20'' V21'' V22'' V23'' V24'' V25'' V26'' V27'' V28'' V29'' V30'' V31'' V32'' V33'' V34'' V35'' V36'' V37'' V38'' V39'' V40'' V41'' V42'' V43'' V44'' V45'' V46'' V47'' V48'' V49'' V50'' V51'' V52'' V53'' V54'' V55'' V56'' V57'' V58'' V59'' V60'' V61'' V62'' V63'' Output Voltage V9 V9+(V8-V9)× 1150 V9+(V8-V9)× 1850 V9+(V8-V9)× 2550 V9+(V8-V9)× 3250 V9+(V8-V9)× 3950 V9+(V8-V9)× 4300 V9+(V8-V9)× 4650 V9+(V8-V9)× 5000 V9+(V8-V9)× 5350 V9+(V8-V9)× 5700 V9+(V8-V9)× 6050 V9+(V8-V9)× 6400 V9+(V8-V9)× 6750 V9+(V8-V9)× 7050 V9+(V8-V9)× 7350 V8 V8+(V7-V8)× 200 V8+(V7-V8)× 400 V8+(V7-V8)× 600 V8+(V7-V8)× 800 V8+(V7-V8)× 1000 V8+(V7-V8)× 1150 V8+(V7-V8)× 1300 V8+(V7-V8)× 1450 V8+(V7-V8)× 1600 V8+(V7-V8)× 1700 V8+(V7-V8)× 1800 V8+(V7-V8)× 1900 V8+(V7-V8)× 2000 V8+(V7-V8)× 2100 V8+(V7-V8)× 2200 V7 V7+(V6-V7)× 100 V7+(V6-V7)× 200 V7+(V6-V7)× 300 V7+(V6-V7)× 400 V7+(V6-V7)× 500 V7+(V6-V7)× 600 V7+(V6-V7)× 700 V7+(V6-V7)× 800 V7+(V6-V7)× 900 V7+(V6-V7)× 1000 V7+(V6-V7)× 1100 V7+(V6-V7)× 1200 V7+(V6-V7)× 1300 V7+(V6-V7)× 1400 V7+(V6-V7)× 1500 V6 V6+(V5-V6)× 150 V6+(V5-V6)× 300 V6+(V5-V6)× 450 V6+(V5-V6)× 600 V6+(V5-V6)× 750 V6+(V5-V6)× 900 V6+(V5-V6)× 1050 V6+(V5-V6)× 1300 V6+(V5-V6)× 1550 V6+(V5-V6)× 1800 V6+(V5-V6)× 2100 V6+(V5-V6)× 2400 V6+(V5-V6)× 2700 V6+(V5-V6)× 3150 V5 / / / / / / / / / / / / / / / 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 7650 / / / / / / / / / / / / / / / 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 2300 / / / / / / / / / / / / / / / 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 1650 / / / / / / / / / / / / / / 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 4250 Caution There is no connection between V4 and V5 terminal in the chip. 8 Data Sheet S15261EJ1V0DS (Ω) rn r0 1150 r1 700 r2 700 r3 700 r4 700 r5 350 r6 350 r7 350 r8 350 r9 350 r10 350 r11 350 r12 350 r13 300 r14 300 r15 300 r16 200 r17 200 r18 200 r19 200 r20 200 r21 150 r22 150 r23 150 r24 150 r25 100 r26 100 r27 100 r28 100 r29 100 r30 100 r31 100 r32 100 r33 100 r34 100 r35 100 r36 100 r37 100 r38 100 r39 100 r40 100 r41 100 r42 100 r43 100 r44 100 r45 100 r46 100 r47 150 r48 150 r49 150 r50 150 r51 150 r52 150 r53 150 r54 150 r55 250 r56 250 r57 250 r58 300 r59 300 r60 300 r61 450 r62 1100 rtotal 15850 µ PD16770A 6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format: 6 bits × 2 RGBs (6 dots) Input width: 36 bits (2-pixel data) R,/L = H (Right shift) Output S1 S2 S3 S4 xxx S419 S420 Data D00 to D05 D10 to D15 D20 to D25 D30 to D35 xxx D40 to D45 D50 to D55 R,/L = L (Left shift) Output S1 S2 S3 S4 xxx S419 S420 Data D00 to D05 D10 to D15 D20 to D25 D30 to D35 xxx D40 to D45 D50 to D55 POL S2n–1Note S2nNote L V0 to V4 V5 to V9 H V5 to V9 V0 to V4 Note S2n-1 (Odd output), S2n (Even output) 7. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM The output voltage is written to the LCD panel synchronized with the STB falling edge. STB POL S2n-1 Selected voltage V0 to V4 Selected voltage V5 to V9 Selected voltage V0 to V4 S2n Selected voltage V0 to V4 Selected voltage V5 to V9 Hi-Z Hi-Z Data Sheet S15261EJ1V0DS Selected voltage V5 to V9 Hi-Z 9 µ PD16770A 8. RELATIONSHIP BETWEEN STB, CLK, AND OUTPUT WAVEFORM The output voltage is written to the LCD panel synchronized with the STB falling edge. Figure8− −1. Output Circuit Block Diagram Output Amp DAC + SW1 Sn (VOUT) VAMP(IN) Figure8− −2. Output Circuit Timing Waveform [1] [2] CLK (External Input) STB (External Input) SW1 : ON SW1 : OFF SW1 : ON VAMP(IN) Sn (VOUT: External Output) Output Hi-Z Output Remarks 1. STB = L: SW1 = ON, STB = H: SW1 = OFF 2. STB = “H” is acknowledged at timing [1]. 3. The display data latch is completed at timing [2] and the input voltage (VAMP(IN): gray-scale level voltage) of the output amplifier changes. 10 Data Sheet S15261EJ1V0DS µ PD16770A 9. CURRENT CONSUMPTION CONTROL FUNCTION The µ PD16770A has a power control function which can switch the bias current of the output amplifier between four levels and a bias control function (Bcont) which can be used to finely control the bias current. <Power control function (LPC, HPC)> The bias current of the output amplifier can be switched between four levels using LPC (Low Power Control) pins and HPC (High Power Control) pins. Power mode LPC HPC L L Middle H or Open L Normal L H or Open H or Open H or Open High Low Following graph shows the relationship between each power modes and bias current. HIGH MID NOMAL IDD2 LOW 6.00 7.00 8.00 9.00 VDD2 Remark This relationship is founded on results of simulation and don’t assuring a characteristics of this product. Data Sheet S15261EJ1V0DS 11 µ PD16770A <Bias Current Control Function (Bcont)> It is possible to fine-control the current consumption by using the bias current control function (Bcont pin). When using this function, connect this pin to the stabilized ground potential (VSS2) via an external resistor (REXT). When not using this function, leave this pin open. Figure9− −1. Bias Current Control Function (Bcont) µPD16770A Bcont HPC H/L LPC H/L REXT VSS2 Refer to the table below for the percentage of current regulation when using the bias current control function. Table9− −1. Current Consumption Regulation Percentage Compared to Normal Mode Current Consumption Regulation Percentage REXT LPC = L, HPC = H/open LPC = H/open, HPC = H/open ∞ (Open) 100% 65% VDD1 = 3.3 V 50 kΩ 110% 70% VDD2 = 8.7 V 20 kΩ 115% 80% 10 kΩ 120% 85% Remark The above current consumption regulation percentages are founded on results of simulation and don’t assuring a characteristics of this product. Caution Because the power and bias-current control functions control the bias current in the output amplifier and regulate the over-all current consumption of the driver IC, when this occurs, the characteristics of the output amplifier will simultaneously change. Therefore, when using these functions, be sure to sufficiently evaluate the picture quality. 12 Data Sheet S15261EJ1V0DS µ PD16770A 10. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C, VSS1 = VSS2 = 0 V) Parameter Symbol Rating Unit Logic Part Supply Voltage VDD1 –0.5 to +4.0 V Driver Part Supply Voltage VDD2 –0.5 to +10.0 V Logic Part Input Voltage VI1 –0.5 to VDD1 + 0.5 V Driver Part Input Voltage VI2 –0.5 to VDD2 + 0.5 V Logic Part Output Voltage VO1 –0.5 to VDD1 + 0.5 V Driver Part Output Voltage VO2 –0.5 to VDD2 + 0.5 V Operating Ambient Temperature TA –10 to +75 °C Storage Temperature Tstg –55 to +125 °C Caution Product qualify may suffer if the absolute maximum rating is exceeded even momentarily for any parameter/ That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = –10 to +75°C, VSS1 = VSS2 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 3.6 V 9.0 V Logic Part Supply Voltage VDD1 2.3 Driver Part Supply Voltage VDD2 8.0 High-Level Input Voltage VIH 0.7 VDD1 VDD1 V Low-Level Input Voltage VIL 0 0.3 VDD1 V V0 to V9 VSS2 + 0.1 VDD2 − 0.1 V Driver Part Output Voltage VO VSS2 + 0.1 VDD2 − 0.1 V Maximum Clock Frequency fCLK 45 MHz γ -Corrected Voltage VDD1 = 2.3 V Data Sheet S15261EJ1V0DS 8.5 13 µ PD16770A Electrical Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.5 V ± 0.5 V, VSS1 = VSS2 = 0 V, unless otherwise specified, power mode: normal, Bcont = open) Parameter Symbol Input Leak Current Conditions MIN. TYP. IIL High-Level Output Voltage VOH STHR (STHL), IOH = 0 mA Low-Level Output Voltage VOL STHR (STHL), IOL = 0 mA γ -Corrected Supply Current Iγ VDD2 = 8.5 V Driver Output Current Output Voltage Deviation Unit ±1.0 µA VDD1 − 0.1 V 0.1 V V0 pin, V5 pin 126 252 504 µA V4 pin, V9 pin −504 −252 −126 µA −30 µA V0 to V4 = V5 to V9 = 4.0 V MAX. IVOH VX = 7.0 V, VOUT = 6.5 VNote IVOL VX = 1.0 V, VOUT = 1.5 V Note ∆VO TA = 25°C µA 30 ±7 ±20 mV VOUT = 2.0 V, 4.25 V, 6.5 V ±2 ±15 mV IDD1 VDD1 1.0 6.5 mA IDD2 VDD2, with no load 3.0 6.5 mA VDD1 = 3.3 V, VDD2 = 8.5 V, ∆VP–P Output swing difference deviation Logic Part Dynamic Current Consumption Driver Part Dynamic Current Consumption Note VX refers to the output voltage of analog output pins S1 to S420. VOUT refers to the voltage applied to analog output pins S1 to S420. ★ Cautions 1. fSTB = 64 kHz, fCLK = 40 MHz. 2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 3. Refers to the current consumption per driver when cascades are connected under the assumption of SXGA+ single-sided mounting (10 units). Switching Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.5 V ± 0.5 V, VSS1 = VSS2 = 0 V, unless otherwise specified, power mode: normal, Bcont = open) Parameter Start Pulse Delay Time Symbol TYP. MAX. Unit 10 20 ns 10 20 ns 2.5 5 µs tPLH3 5 8 µs tPHL2 2.5 5 µs tPHL3 5 8 µs tPLH1 Conditions CL = 10 pF tPHL1 Driver Output Delay Time Input Capacitance 14 tPLH2 CL = 75 pF, RL = 5 kΩ MIN. CI1 STHR (STHL) excluded, TA = 25°C 5 10 pF CI2 STHR (STHL),TA = 25°C 8 10 pF Data Sheet S15261EJ1V0DS µ PD16770A Timing Requirement (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns) Parameter Clock Pulse Width Symbol PWCLK Conditions VDD1 = 2.3 V to 3.6 V MIN. TYP. MAX. Unit 22 ns Clock Pulse High Period PWCLK(H) 4 ns Clock Pulse Low Period PWCLK(L) 4 ns Data Setup Time tSETUP1 4 ns Data Hold Time tHOLD1 0 ns Start Pulse Setup Time tSETUP2 4 ns Start Pulse Hold Time tHOLD2 0 ns POL21, POL22 Setup Time tSETUP3 4 ns POL21, POL22 Hold Time tHOLD3 0 ns tSPL 1 CLK STB Pulse Width PWSTB 2 CLK Last Data Timing tLDT 2 CLK Start Pulse Low Period CLK-STB Time tCLK-STB CLK ↑ → STB ↑ 6 ns STB-CLK Time tSTB-CLK STB ↑ → CLK ↑ 9 ns Time Between STB and Start Pulse tSTB-STH STB ↑ → STHR(STHL) ↑ 2 CLK POL-STB Time tPOL-STB POL ↑ or ↓ → STB ↑ –5 ns STB-POL Time tSTB-POL STB ↓ → POL ↓ or ↑ 6 ns Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1. Data Sheet S15261EJ1V0DS 15 ★ 2 3 1 70 71 72 701 tr 2 tf VDD1 90% 702 10% tSETUP2 tHOLD2 tCLK-STB tSTB-CLK VSS1 tSPL VDD1 STHR (1st Dr.) VSS1 tSETUP1 Dn0 to Dn5 INVALID D1 to D6 D7 to D12 tSETUP3 Data Sheet S15261EJ1V0DS POL21, POL22 tHOLD1 tSTB-STH D409 to D414 D415 to D420 D421 to D426 VDD1 D4195 to D4200 INVALID D1 to D6 D7 to D12 VSS1 tHOLD3 VDD1 INVALID INVALID VSS1 tPLH1 tPHL1 VDD1 STHL (1st Dr.) VSS1 tLDT PWSTB VDD1 STB VSS1 tPOL-STB tSTB-POL VDD1 POL VSS1 tPLH3 Hi-Z tPLH2 tPHL2 tPHL3 µ PD16770A Target Voltage +0.1 VDD2 6-bit accuracy Sn (VOUT) Switching characteristics waveform (R,/L = H) 1 CLK PWCLK(H) Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1. 16 PWCLK(L) PWCLK µ PD16770A 11. RECOMMENDED SOLDERING CONDITIONS The following conditions must be met for soldering conditions of the µ PD16770A. For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. µPD16770AN-×××: TCP (TAB package) Mounting Condition Mounting Method Condition Thermocompression Soldering Heating tool 300 to 350°C: heating for 2 to 3 seconds: pressure 100g (per solder) ACF (Adhesive Conductive Film) Temporary bonding 70 to 100°C: pressure 3 to 8 kg/cm2 : time 3 to 5 seconds. Real bonding 165 to 180°C: pressure 25 to 45 kg/cm2 : time 30 to 40 seconds. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.) Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more packaging methods at a time. Data Sheet S15261EJ1V0DS 17 µ PD16770A [MEMO] 18 Data Sheet S15261EJ1V0DS µ PD16770A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S15261EJ1V0DS 19 µ PD16770A Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Semiconductor Device Mounting Technology (C10535E) • The information in this document is current as of May, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4