DATA SHEET MOS INTEGRATED CIRCUIT µ PD168002 MONOLITHIC 6-CHANNEL H-BRIDGE DRIVER DESCRIPTION The µ PD168002 is a monolithic 6-channel H-bridge driver that consists of a CMOS control circuit and a MOS output stage. It can reduce the current consumption and the voltage loss at the output stage compared with conventional driver using bipolar transistors, thanks to employment of a MOS process. The µ PD168002 employs P-channel MOS FET in the output stage, and is eliminated the charge pump circuit. Therefore, the circuit current consumption during operation can be significantly reduced. The package is a 48-pin TQFP that helps reduce the mounting area and height. The µ PD168002 can be used to drive one stepping motor and four DC motors, and is suitable for the motor driver of CD-ROM/CD audios. FEATURES • Six H-bridge circuits employing power MOS FET • Low current consumption due to elimination of charge pump circuit • Input logic frequency: 100 kHz supported • 3 V power supply supported for logic Minimum operating supply voltage: 2.7 V • 5 V, 10 V power supply supported for motor ch1, ch2, ch5 and ch6: 10 V driving ch3 and ch4: 5 V driving • Undervoltage lockout circuit Shuts down the internal circuit at VDD = 1.7 V TYP. • Overheat protection circuit • 48-pin TQFP (□7 mm) ORDERING INFORMATION Part Number Package µ PD168002GA-9EU 48-pin plastic TQFP (fine pitch) (7 x 7) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S16040EJ1V0DS00 (1st edition) Date Published November 2003 NS CP(K) Printed in Japan 2002 µ PD168002 37 PGND OUT6B VM6 OUT6A PGND OUT5B VM5 OUT5A PGND LGND (NC) (NC) 1. BLOCK DIAGRAM 36 25 24 PGND PGND OUT2A OUT4A VM2 Spindle H-bridge 5 Sled H-bridge 2 OUT2B Loading H-bridge 6 VM4 Tracking H-bridge 4 OUT4B PGND PGND OUT1A OUT3A Sled H-bridge 1 VM1 Focus H-bridge 3 H-bridge ch3 to ch6 control circuit OUT1B VM3 OUT3B PGND PGND H-bridge ch1 to ch2 control circuit IN1A STB6 IN1/IN1B STB5 EN12/IN2A STB34 13 48 1 STB12 SEL12 IN6B IN6A IN5B IN5A VDD IN4B IN4A IN3B IN3A IN2/IN2B 12 Cautions 1. Be sure to connect all of the pins which have more than one. 2. A pull-down resistor (50 to 200 kΩ) is internally connected to the logic input pins. Logic input pins: IN1A, IN1/IN1B, EN12/IN2A, IN2/IN2B, IN3A, IN3B, IN4A, IN4B, IN5A, IN5B, IN6A, IN6B, SEL12, STB12, STB34, STB5 and STB6 3. The power supply pins for motor, VM1 and VM2, VM3 and VM4, and VM5 and VM6, are connected each other inside. These pins must be applied from the same potential. 2 Data Sheet S16040EJ1V0DS µ PD168002 2. PIN FUNCTIONS Package: 48-pin plastic TQFP (fine pitch) (7 x 7) (1/2) Pin No. Pin Name Function 1 IN2/IN2B ch2 input pin or ch2 input pin B 2 IN3A ch3 input pin A 3 IN3B ch3 input pin B 4 IN4A ch4 input pin A 5 IN4B ch4 input pin B 6 VDD Logic power supply pin 7 IN5A ch5 input pin A 8 IN5B ch5 input pin B 9 IN6A ch6 input pin A 10 IN6B ch6 input pin B 11 SEL12 ch1 and ch2 input logic selection pin 12 STB12 ch1 and ch2 standby pin 13 STB34 ch3 and ch4 standby pin 14 STB5 ch5 standby pin 15 STB6 ch6 standby pin 16 PGND GND pin 17 OUT3B ch3 output B 18 VM3 ch3 power supply pin 19 OUT3A ch3 output A 20 PGND GND pin 21 OUT4B ch4 output B 22 VM4 ch4 power supply pin 23 OUT4A ch4 output A 24 PGND GND pin 25 PGND GND pin 26 OUT6B ch6 output B 27 VM6 ch6 power supply pin 28 OUT6A ch6 output A 29 PGND GND pin 30 OUT5B ch5 output B 31 VM5 ch5 power supply pin 32 OUT5A ch5 output A 33 PGND GND pin 34 LGND GND pin 35 (NC) Unused Caution Be sure to connect all of the pins which have more than one. Data Sheet S16040EJ1V0DS 3 µ PD168002 (2/2) Pin No. Pin Name Function 36 (NC) Unused 37 PGND GND pin 38 OUT2A ch2 output A 39 VM2 ch2 power supply pin 40 OUT2B ch2 output B 41 PGND GND pin 42 OUT1A ch1 output A 43 VM1 ch1 power supply pin 44 OUT1B ch1 output B 45 PGND GND pin 46 IN1A ch1 input pin A 47 IN1/IN1B ch1 input pin or ch1 input pin B 48 EN12/IN2A ch1 and ch2 control pin or ch2 input pin A Caution Be sure to connect all of the pins which have more than one. 4 Data Sheet S16040EJ1V0DS µ PD168002 3. STANDARD CONNECTION EXAMPLE M PGND VM6 OUT6A PGND OUT5B VM5 OUT5A PGND LGND Loading motor 36 25 24 PGND PGND OUT2A OUT4A Spindle H-bridge 5 Sled H-bridge 2 VM2 Sled motor (NC) (NC) 37 M OUT6B Spindle motor M Loading H-bridge 6 VM4 Tracking H-bridge 4 OUT2B OUT4B PGND PGND OUT1A OUT3A VM1 Sled H-bridge 1 H-bridge ch3 to ch6 control circuit OUT1B 8V VM3 Focus H-bridge 3 5V Focus coil OUT3B PGND PGND H-bridge ch1 to ch2 control circuit IN1A Tracking coil STB6 STB5 IN1/IN1B STB34 EN12/IN2A 13 48 1 STB12 SEL12 IN6B IN6A IN5B IN5A VDD IN4B IN4A IN3B IN3A IN2/IN2B 12 3V Caution This diagram is the example of connection and is not what was created as a purpose of mass production. Data Sheet S16040EJ1V0DS 5 µ PD168002 4. FUNCTION OPERATION TABLE 4.1 Relationship between SEL Pin and Input Pins SEL pin 46-pin 47-pin 48-pin 1-pin L Unused ch1 input pin IN1 ch1 and ch2 control pin EN12 ch2 input pin IN2 H ch1 input pin IN1A ch1 input pin IN1B ch2 input pin IN2A ch2 input pin IN2B Remark L: Low level, H: High level 4.2 ch1 and ch2 Input/output Truth Table (1) SEL12 = L Input EN12 Output IN Output Status OUTA OUTB L x Z Z Stop (output high impedance) H L H L Forward revolution (OUTA → OUTB) H H L H Reverse revolution (OUTB → OUTA) Remark x: High level or low level, Z: Output high impedance (2) SEL12 = H Input Output Output Status INA INB OUTA OUTB L L L L Stop (short brake) L H L H Reverse revolution (OUTB → OUTA) H L H L Forward revolution (OUTA → OUTB) H H H H Stop (short brake) 4.3 ch3 to ch5 Input/output Truth Table Input INA Output INB OUTA Output Status OUTB L L L L Stop (short brake) L H L H Reverse revolution (OUTB → OUTA) H L H L Forward revolution (OUTA → OUTB) (H) (H) (H) (H) Stop (short brake) Caution At ch3 to ch5, inputting INA = H and INB = H prohibits. 4.4 ch6 Input/output Truth Table Input INA 6 Output INB OUTA Output Status OUTB L L L L Stop (short brake) L H L H Reverse revolution (OUTB → OUTA) H L H L Forward revolution (OUTA → OUTB) H H H H Stop (short brake) Data Sheet S16040EJ1V0DS µ PD168002 5. STANDBY FUNCTION The µ PD168002 realizes a standby function by combination of an input signal. The specified output is set to high impedance (Hi-Z) status by setting STB to low level. Each pin can be independently controlled, and can be set to standby status of the self current consumption of the IC reduced as much as possible by setting all pins to low level. In the standby status, the overheat protection circuit and the undervoltage lockout circuit do not operate. Pin Function Output Status when Pin = L ch1 ch2 ch3 ch4 ch5 ch6 STB12 Sled block standby Hi-Z Hi-Z ON ON ON ON STB34 Focus and tracking ON ON Hi-Z Hi-Z ON ON block standby STB5 Spindle block standby ON ON ON ON Hi-Z ON STB6 Loading block standby ON ON ON ON ON Hi-Z Remark ON: Status which can turn on output, Hi-Z: High impedance 6. OPERATION WAVEFORM EXAMPLES (1) Example of the clockwise revolution of the right figure when 2-phase diving <1> <2> <3> <4> <1> <2> <3> <4> <1> Phase A IN (IN1) Phase B IN (IN2) (2) <4> (2) Example of the counter-clockwise revolution of the right figure when 2-phase diving <1> <4> <3> <2> <1> <4> <3> <2> OUTB → OUTA OUTA → OUTB ch2 <1> <3> Phase A IN (IN1) OUTA → OUTB ch1 <1> <2> OUTB → OUTA (1) Phase B IN (IN2) Remark SEL12 = L, EN12 = H Data Sheet S16040EJ1V0DS 7 µ PD168002 7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C, glass epoxy board of 100 mm x 100 mm x 1 mm with copper foil area of 15%) Parameter Power supply voltage Symbol Condition Rating Unit VDD Control block −0.5 to +6.0 V VM Motor block (ch3 and ch4) −0.5 to +6.0 V Motor block (ch1, ch2, ch5 and ch6) −0.5 to +12.0 V Input voltage VIN −0.5 to VDD + 0.5 V Output pin voltage 1 VOUT1 Motor block (ch3 and ch4) 6.2 V Output pin voltage 2 VOUT2 Motor block (ch1, ch2, ch5 and ch6) 12.2 V DC output current 1 ID(DC)1 DC (ch3 to ch5) ±0.3 A/ch DC output current 2 ID(DC)2 DC (ch1, ch2 and ch6) ±0.15 A/ch Instantaneous output current 1 ID(pulse)1 PW < 10 ms, Duty Cycle ≤ 20% (ch3 to ch5) ±0.6 A/ch Instantaneous output current 2 ID(pulse)2 PW < 10 ms, Duty Cycle ≤ 20% (ch1, ch2 and ch6) ±0.3 A/ch Power consumption PT 1.0 W Peak junction temperature Tch(MAX) 150 °C Storage temperature Tstg −55 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions (TA = 25°C, glass epoxy board of 100 mm x 100 mm x 1 mm with copper foil area of 15%) Parameter Power supply voltage Symbol Condition MIN. TYP. MAX. Unit 5.5 V VDD Control block 2.7 VM Motor block (ch3 and ch4) 2.7 5.5 V Motor block (ch1, ch2, ch5 and ch6) 6.0 11.0 V 0 VDD V Input voltage VIN DC output current 1 ID(DC)1 DC (ch3 to ch5) −0.2 +0.2 A/ch DC output current 2 ID(DC)2 DC (ch1, ch2 and ch6) −0.1 +0.1 A/ch Instantaneous output current 1 ID(pulse)1 PW < 10 ms, Duty Cycle ≤ 20% (ch3 to ch5) −0.4 +0.4 A/ch Instantaneous output current 2 ID(pulse)2 PW < 10 ms, Duty Cycle ≤ 20% (ch1, ch2 and −0.2 +0.2 A/ch 100 kHz 85 °C ch6) Logic input frequency fIN Operating temperature range TA 8 −40 Data Sheet S16040EJ1V0DS µ PD168002 Electrical Characteristics (Unless otherwise specified, TA = 25°C, VDD = 3 V, VM = 5 V (ch3 and ch4), VM = 8 V (ch1, ch2, ch5 and ch6) ) Parameter Symbol VDD pin current in standby mode IDD(STB) VDD pin current in during operation IDD(ACT) VM pin current in during operation IM Condition MIN. TYP. All control pin: Low level Output with no load, IN pin, EN pin: Low MAX. Unit 1.0 µA 1.0 mA 100 µA 60 µA level High-level input current IIH VIN = VDD Low-level input current IIL VIN = 0 V Input pull-down resistance RIND High-level input voltage VIH 2.7 V ≤ VDD ≤ 5.5 V Low-level input voltage VIL 2.7 V ≤ VDD ≤ 5.5 V H-bridge on-state resistance 1 Ron1 IM = 0.1 A (ch1 and ch2), IM = 0.2 A (ch1, ch2 and ch5) µA −1.0 50 200 0.7 x VDD kΩ V 0.3 x VDD V 2.0 3.0 Ω 1.2 2.0 Ω 3.5 5.0 Ω 10 µA 1.7 2.5 V (ch5), sum of upper and lower stages H-bridge on-state resistance 2 Ron2 (ch3 and ch4) IM = 0.2 A, sum of upper and lower stages H-bridge on-state resistance 3 Ron3 (ch6) IM = 0.1 A, sum of upper and lower stages Output leakage current IM(off) Per VM pin, All control pin: Low level (VM = MAX. value in the recommended range) Low-voltage detection voltage Output turn-on time Output turn-off time Note Note VDDS ton2 IM = 0.1 A (ch1, ch2 and ch6), 0.2 0.6 2.0 µs toff2 Refer to Figure 7−1. H-bridge 0.05 0.3 1.0 µs Switching Waveform (when SEL12 = L) and Figure 7−2. H-bridge Switching Waveform (when SEL12 = H) . Output turn-on time Output turn-off time Note Note ton1 IM = 0.2 A (ch3 to ch5), 0.05 0.15 1.0 µs toff1 Refer to Figure 7−2. H-bridge 0.05 0.2 1.0 µs Switching Waveform (when SEL12 = H) (only when VINB = L) . Note For the turn-on time and the turn-off time, to fix one of two input pins to low level is conditions. Remark The overheat protection circuit operates under Tch > 150°C. All outputs goes high impedance in the protection status. Note that the overheat protection circuit and the undervoltage lockout circuit do not operate in the standby status. Data Sheet S16040EJ1V0DS 9 µ PD168002 Switching Characteristics Waveform Figure7−1. H-bridge Switching Waveform (when SEL12 = L) 100% EN12 50% 50% 0% ton toff tr tf 90% 90% IOUT 10% 10% 100% VIN 50% 50% 0% ton ton toff toff 100% 100% 90% 90% 50% 50% IOUT 0% tf 10% −10% 10% −10% −50% −90% tr tr −50% −90% −100% tf Remark The high impedance period of about 50 ns is prepared for the through-current prevention at the time of mode switching. The tr (rise time) is designed as 50 ns, and the tf (fall time) is designed as about 50 ns. 10 Data Sheet S16040EJ1V0DS µ PD168002 Figure7−2. H-bridge Switching Waveform (when SEL12 = H) When VINB = L 100% 90% VINA 10% toff ton tr tf OUT1A → OUT1B 90% 90% IOUT 10% Hi-Z 10% Hi-Z When VINB = H Note 100% 90% VINA 10% ton toff tr tr OUT1B → OUT1A 90% OUT1B → OUT1A 90% IOUT 10% Brake 10% Note The conditions of VINB = H is valid only at ch1, ch2 and ch6. The through current may be flowed, if the switching operation is performed under the conditions of VINB = H at ch3 to ch5. Remark The high impedance period of about 50 ns is prepared for the through-current prevention at the time of mode switching. The tr (rise time) is designed as 50 ns, and the tf (fall time) is designed as about 50 ns. Data Sheet S16040EJ1V0DS 11 µ PD168002 8. PACKAGE DRAWING 48-PIN PLASTIC TQFP (FINE PITCH) (7x7) A B 36 37 25 24 detail of lead end S C D Q 48 R 13 12 1 F G J H I M P K S N S L M NOTE ITEM Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 9.0±0.2 B 7.0±0.2 C 7.0±0.2 D 9.0±0.2 F 0.75 G 0.75 H 0.22 +0.05 −0.04 I J 0.10 0.5 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.145 +0.055 −0.045 N 0.10 P 1.0±0.1 Q 0.1±0.05 R +7° 3° −3° S 1.27 MAX. S48GA-50-9EU-2 12 Data Sheet S16040EJ1V0DS µ PD168002 9. RECOMMENDED SOLDERING CONDITIONS The µ PD168002 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Type of Surface Mount Device µ PD168002GA-9EU: 48-pin plastic TQFP (fine pitch) (7 x 7) Process Infrared reflow Conditions Package peak temperature: 235°C, Time: 60 seconds MAX. (at 210°C or higher) , Symbol IR35-00-3 Count: Three times or less, Exposure limit: None, Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended. Caution Do not use different soldering methods together (except for partial heating) . Data Sheet S16040EJ1V0DS 13 µ PD168002 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 14 Data Sheet S16040EJ1V0DS µ PD168002 Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades on NEC Semiconductor Devices (C11531E) • The information in this document is current as of November, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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