DATA SHEET MOS INTEGRATED CIRCUIT µPD16877 MONOLITHIC QUAD H-BRIDGE DRIVER CIRCUIT DESCRIPTION The µPD16877 is monolithic quad H-bridge driver LSI which uses power MOSFETs in the output stages. By using the MOS process, this driver IC has substantially improved saturation voltage and power consumption as compared with conventional driver circuits using bipolar transistors. By eliminating the charge pump circuit, the current during power-OFF is drastically decreased. In addition, a low-voltage malfunction prevention circuit is also provided that prevents the IC from malfunctioning when the supply voltage drops. As the package, a 24-pin plastic TSSOP is adopted to enable the creation of compact, slim application sets. This driver IC can drive two stepping motor at the same time, and is ideal for driving stepping motors in the lens of a camcorder. FEATURES Four H bridge circuits employing power MOSFETs Low current consumption by eliminating charge pump VM pin current when power-OFF: 10 µA MAX. VDD pin current: 10 µA MAX. Input logic frequency: 100 kHz 3-V power supply Minimum operating supply voltage: 2.5 V Low voltage malfunction prevention circuit 24-pin plastic TSSOP (5.72 mm (225)) ORDERING INFORMATION Part Number µPD16877MA-6A5 Package 24-pin plastic TSSOP (5.72 mm (225)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S13964EJ1V0DS00 (1st edition) Date Published March 2000 N CP(K) Printed in Japan © 2000 µPD16877 ABSOLUTE MAXIMUM RATINGS (TA = 25°°C) When mounted on a glass epoxy board (10 cm × 10 cm × 1 mm, 15% copper foil) Parameter Symbol Condition Rating Unit Control block supply voltage VDD −0.5 to +6.0 V Output block supply voltage VM −0.5 to +6.0 V Input voltage VIN −0.5 to VDD + 0.5 V Output terminal voltage VOUT 6.2 V ID(DC) DC ±0.3 A/ch ID(pulse) PW ≤ 10 ms, Duty ≤ 5% ±0.7 A/ch Output current Power consumption PT 0.7 W Peak junction temperature TCH(MAX) 150 °C Storage temperature range Tstg −55 to +150 °C RECOMMENDED OPERATING CONDITIONS When mounted on a glass epoxy board (10 cm × 10 cm × 1 mm, 15% copper foil) Parameter Symbol Condition MIN. TYP. MAX. Unit Control block supply voltage VDD 2.5 5.5 V Output block supply voltage VM 2.7 5.5 V Output current ID(DC) DC −0.2 +0.2 A Operating frequency fIN IN, EN terminal 100 kHz Operating temperature range TA 85 °C Peak junction temperature TCH(MAX) 125 °C MAX. Unit −10 CHARACTERISTICS (Unless otherwise specified, VDD = VM = 3 V, TA = 25°°C) Parameter Symbol MIN. TYP. Off state VM pin current IM(OFF) All control terminal: L level 10 µA VDD pin current IDD All control terminal: L level 10 µA High level input current IIH VIN = VDD 0.06 mA Low level input current IIL VIN = 0 V Input pull down resistance RIND High level input voltage VIH Low level input voltage VIL H-bridge ON resistance RON 2.5 V ≤ VM, VDD ≤ 5.5 V Upper + lower VDDS1 VM = 5 V −10°C ≤ TA ≤ +85°C VDDS2 VM = 3 V −10°C ≤ TA ≤ +85°C Low voltage malfunction prevention circuit operating voltage H bridge output turn-on time 2 Condition 2.5 V ≤ VDD ≤ 5.5 V 50 200 kΩ 0.7 × VDD VDD+0.3 V −3.0 0.3 × VDD V 3.0 Ω 0.8 2.5 V 0.65 2.5 V 0.7 20 µs 0.2 0.5 µs 0.4 1.0 µs 70 200 ns tONH H bridge output turn-off time tOFFH H bridge output rise time tr H bridge output fall time tf RM = 20 Ω Figure 1 Data Sheet S13964EJ1V0DS00 µA −1.0 0.1 µPD16877 Figure 1. Switching time condition 100% 50% 50% VIN 0% tONH tONH tOFFH tOFFH 100% 90% 100% 90% 50% 50% ID 10% −10% 0% 10% −10% tf −50% −50% −90% −100% tr tr −90% The current flowing in the direction from OUT_A to OUT_B is assumed to be (+). tf FUNCTION TABLE Channel 1 Channel 2 EN1 IN1 OUT1A OUT1B EN2 IN2 OUT2A H L H L H L H L H H L H H H L H L L Z Z L L Z Z L H Z Z L H Z Z EN3 IN3 OUT3A OUT3B EN4 IN4 OUT4A OUT4B H L H L H L H L H H L H H H L H L L Z Z L L Z Z L H Z Z L H Z Z Channel 3 OUT2B Channel 4 H: High-level, L: Low-level, Z: High impedance Data Sheet S13964EJ1V0DS00 3 µPD16877 PIN CONNECTION 4 Pin No. Pin name 1 VM1 2 VM1 1 24 VDD OUT1A 2 23 OUT1B PGND 3 22 PGND OUT2A 4 21 OUT2B OUT3A 5 20 VM23 PGND 6 19 OUT3B OUT4A 7 18 PGND VM4 8 17 OUT4B IN1 9 16 EN4 EN1 10 15 IN4 IN2 11 14 EN3 EN2 12 13 IN3 Pin function Pin No. Pin name Output block supply voltage input terminal 13 IN3 Control terminal (channel 3) OUT1A Output terminal 14 EN3 Enable terminal (channel 3) 3 PGND Ground terminal 15 IN4 Control terminal (channel 4) 4 OUT2A Output terminal 16 EN4 Enable terminal (channel 4) 5 OUT3A Output terminal 17 OUT4B Output terminal 6 PGND Ground terminal 18 PGND Ground terminal 7 OUT4A Output terminal 19 OUT3B Output terminal 8 VM4 Output block supply voltage input terminal 20 VM23 9 IN1 Control terminal (channel 1) 21 OUT2B Output terminal 10 EN1 Enable terminal (channel 1) 22 PGND Ground terminal 11 IN2 Control terminal (channel 2) 23 OUT1B Output terminal 12 EN2 Enable terminal (channel 2) 24 VDD Data Sheet S13964EJ1V0DS00 Pin function Output block supply voltage input terminal Control block supply voltage input terminal µPD16877 BLOCK DIAGRAM 24 Low volatge malfunction prevention circuit VDD VM1 1 IN1 9 EN1 10 OUT1A Control H-bridge circuit (1) (1) 2 OUT1B 23 PGND 3 VM23 20 IN2 11 EN2 12 OUT2A Control H-bridge circuit (2) (2) 4 OUT2B 21 PGND IN3 13 OUT3A Control EN3 14 22 5 H-bridge circuit (3) (3) OUT3B 19 PGND 6 VM4 8 IN4 15 EN4 16 OUT4A Control H-bridge circuit (4) (4) 7 OUT4B 17 PGND 18 Remark Plural terminal (VM, PGND) is not only 1 terminal and connect all terminals. Data Sheet S13964EJ1V0DS00 5 µPD16877 TYPICAL CHARACTERISTICS PT vs. TA characteristics IM (OFF) vs. VM characteristics 35 OFF state VM Pin current IM (OFF) (µ A) Total power dissipation PT (W) 1.0 0.8 0.7W 0.6 178°C/W 0.4 0.2 0 −10 0 20 40 60 80 100 25 20 15 10 5 1 2 3 4 5 6 Ambient temperature TA (°C) Output block supply voltage VM (V) IDD vs. VDD characteristics IIH, IIL vs. VDD characteristics 0.7 TA = 25°C control : "L" TA = 25°C 60 Input current IIH IIL (µA) 0.6 VDD pin current IDD (µ A) 30 0 120 TA = 25°C control : "L" 0.5 0.4 0.3 0.2 50 40 IIH 30 20 0.1 10 0 0 IIL 1 2 3 4 5 6 4 5 6 VIH, VIL vs. VDD characteristics VDDS vs. VM characteristics 3.0 VIH, VIL 2.0 1.0 1 2 3 4 5 6 Low voltage detection voltage VDDS (V) Input voltage VIH, VIL (V) 3 Control block supply voltage VDD (V) TA = 25°C TA = 25°C 2.0 VDD (L H) 1.5 VDD (H L) 1.0 0.5 0 Control block supply voltage VDD (V) 6 2 Control block supply voltage VDD (V) 4.0 0 1 1 2 3 4 5 6 Output block supply voltage VM (V) Data Sheet S13964EJ1V0DS00 µPD16877 RON vs. VM characteristics tONH, tOFFH vs. VM characteristics H-bridge ON resistance RON (Ω) 3.0 2.5 2.0 1.5 1.0 0.5 0 1 2 3 4 5 H-bridge Output turn-on time tONH (µs) H-bridge Output turn-off time tOFFH (µ s) 1.0 TA = 25°C TA = 25°C 0.8 tONH 0.6 0.4 tOFFH 0.2 6 Output block supply voltage VM (V) 0 1 2 3 4 5 6 Output block supply voltage VM (V) tr, tf vs. VM characteristics 1.0 H-bridge Output rise time tr (µ s) H-bridge Output fall time tf (µ s) TA = 25°C 0.8 0.6 tr 0.1 0.2 tf 0 1 2 3 4 5 6 Output block supply voltage VM (V) Data Sheet S13964EJ1V0DS00 7 µPD16877 STANDARD CONNECTION EXAMPLE VDD = VM = 2.7 V to 5.5 V DC/DC CONVERTER 1 to 10 µF 1 to 10 µF VM4 VDD low voltage malfunction prevention circuit IN1 EN1 IN2 CPU EN2 IN3 EN3 control circuit VM4 OUT1A H-bridge OUT1B (1) VM2 3 PGND H-bridge OUT2A (2) OUT2B PGND OUT3A level shift circuit IN4 EN4 H-bridge OUT3B (3) PGND OUT4A H-bridge OUT4B (4) PGND 8 motor1 Data Sheet S13964EJ1V0DS00 motor2 µPD16877 PACKAGE DIMENSION 24-PIN PLASTIC TSSOP (5.72 mm (225)) 13 24 detail of lead end F G R P L S 12 1 E A H A' I J S D M N K C M S B NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 6.65±0.10 A' 6.5±0.1 B 0.575 C 0.5 (T.P.) D E 0.22±0.05 0.1±0.05 F 1.2 MAX. G 1.0±0.05 H I J K L M 4.4±0.1 1.0±0.1 0.145±0.025 0.5 0.10 6.4±0.1 N 0.08 P 3°+5° −3° R 0.25 S 0.6±0.15 S24MA-50-6A5 Data Sheet S13964EJ1V0DS00 9 µPD16877 RECOMMENDED SOLDERING CONDITIONS Solder this product under the following recommended conditions. For soldering methods and conditions other than those recommended, consult NEC. For details of the recommended soldering conditions, refer to information document “Semiconductor Device Mounting Technology Manual”. Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C; Time: 30 secs. max. (210°C min.); Number of times: 3 times max; Number of day: none; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2Wt% max.) is recommended. IR35-00-3 VPS Package peak temperature: 215°C; Time: 40 secs. max. (200°C min.); Number of times: 3 times max.; Number of day: none; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2 Wt% max.) is recommended. VP15-00-3 Wave soldering Package peak temperature: 260°C; Time: 10 secs. max.; Preheating temperature: 120°C max.; Number of times: once; Flux: Rosin-based flux with little chlorine content (chlorine: 0.2 Wt% max.) is recommended. WS60-00-1 Caution Do not use two or more soldering methods in combination. 10 Data Sheet S13964EJ1V0DS00 µPD16877 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S13964EJ1V0DS00 11 µPD16877 • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. 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The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8