NEC UPD29F064115F9-DB85X-CD6

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD29F064115-X
64M-BIT CMOS LOW-VOLTAGE DUAL OPERATION FLASH MEMORY
4M-WORD BY 16-BIT (WORD MODE)
PAGE MODE
Description
The µPD29F064115-X is a flash memory organized of 67,108,864 bits and 142 sectors. Sectors of this memory can
be erased at a low voltage (1.65 to 1.95 V, 1.8 to 2.1 V ) supplied from a power source, or the contents of the entire
chip can be erased. Memory organization is 4,194,304 words × 16 bits, so that the memory can be programmed in
word units. µPD29F064115-X can be read high speed with page mode.
The µPD29F064115-X can be read while its contents are being erased or programmed. The memory cell is divided
into four banks. While sectors in any bank are being erased or programmed, data can be read from the other three
banks thanks to the simultaneous execution architecture. The banks are 8M bits, 24M bits, 24M bits and 8M bits.
Input /output voltage is supplied to 2.7 to 3.3 V.
Because the µPD29F064115-X enables the boot sector to be erased, it is ideal for storing a boot program. In
addition, program code that controls the flash memory can be also stored, and the program code can be programmed
or erased without the need to load it into RAM. 16 small sectors for storing parameters are provided, each of which
can be erased in 4K words units.
Once a program or erase command sequence has been executed, an automatic program or automatic erase
function internally executes program or erase and verification automatically. The programming time is about 0.5
seconds per sector. The erase time is less than 1 second per sector.
Because the µPD29F064115-X can be electrically erased or programmed by writing an instruction, data can be
reprogrammed on-board after the flash memory has been installed in a system, making it suitable for a wide range of
applications.
This flash memory is packed in 48-pin PLASTIC TSOP (I), 63-pin TAPE FBGA and 85-pin TAPE FBGA.
Features
• Four bank organization enabling simultaneous execution of program / erase and read
• High-speed read with page mode
• Bank organization : 4 banks (8M bits + 24M bits + 24M bits + 8M bits)
• Memory organization : 4,194,304 words × 16 bits
• Sector organization : 142 sectors (4K words × 16 sectors, 32K words × 126 sectors)
The boot sector is located at the highest address (sector) and the lowest address (sector)
• 3-state output
• Automatic program
• Program suspend / resume
• Unlock bypass program
• Automatic erase
• Chip erase
• Sector erase (sectors can be combined freely)
• Erase suspend / resume
• Program / Erase completion detection
• Detection through data polling and toggle bits
• Detection through RY (/BY) pin
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M16062EJ2V0DS00 (2nd edition)
Date Published September 2002 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
©
2002
µPD29F064115-X
• Sector group protection
• Any sector group can be protected
• Any protected sector group can be temporary unprotected
• Any sector group can be unprotected
• Sectors can be used for boot application
• Hardware reset and standby using /RESET pin
• Automatic sleep mode
• Boot block sector protect by /WP (ACC) pin
• Extra One Time Protect Sector provided
µPD29F064115
Access time
ns (MAX.)
-DB80X, -DB85X
-EB80X
Note
, -EB85X, -EB90X
80, 85
80
Note
, 85, 90
Operating supply voltage V
Power supply current (MAX.)
I/O
VCC
VCCQ
Read
Program / Erase
1.95 ± 0.15
3.0 ± 0.3
20
35
15
25
1.8 ± 0.15
At active
At standby µA
Chip
mA
25
Note Under Development
• Program / erase time
• Program : 11.0 µs / word (TYP.)
• Sector erase :
Program / erase cycle : 100,000 cycle
0.15 s (TYP.) (4K words sector), 0.5 s (TYP.) (32K words sector)
Program / erase cycle : 300,000 cycle
0.5 s (TYP.) (4K words sector), 0.7 s (TYP.) (32K words sector)
• Program / erase cycle : 300,000 cycle (MIN.)
Ordering Information
Part number
Access time
ns (MAX.)
Operating supply voltage V
Operating
Chip
I/O
temperature
VCC
VCCQ
°C
1.95 ± 0.15
3.0 ± 0.3
−25 to +85
Package
µPD29F064115GZ-DB80X-MJH
80
µPD29F064115GZ-DB85X-MJH
85
(Normal bent)
µPD29F064115F9-DB80X-CD6
80
63-pin TAPE FBGA (11 × 8)
µPD29F064115F9-DB85X-CD6
85
µPD29F064115F9-DB80X-CD5
80
48-pin PLASTIC TSOP (I) (12 × 20)
85-pin TAPE FBGA (11 × 8)
µPD29F064115F9-DB85X-CD5
85
µPD29F064115GZ-EB85X-MJH
85
µPD29F064115GZ-EB90X-MJH
90
(Normal bent)
µPD29F064115F9-EB85X-CD6
85
63-pin TAPE FBGA (11 × 8)
µPD29F064115F9-EB90X-CD6
90
µPD29F064115F9-EB85X-CD5
85
µPD29F064115F9-EB90X-CD5
90
2
1.8 ± 0.15
48-pin PLASTIC TSOP (I) (12 × 20)
85-pin TAPE FBGA (11 × 8)
Data Sheet M16062EJ2V0DS
µPD29F064115-X
Pin Configurations
/xxx indicates active low signal.
48-pin PLASTIC TSOP (I) (12 × 20) (Normal bent)
[ µPD29F064115GZ-DB80X-MJH ]
[ µPD29F064115GZ-DB85X-MJH ]
[ µPD29F064115GZ-EB85X-MJH ]
[ µPD29F064115GZ-EB90X-MJH ]
Marking Side
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
/WE
/RESET
A21
/WP (ACC)
RY (/BY)
A18
A17
A7
A6
A5
A4
A3
A2
A1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A0 to A21
A16
VCCQ
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
/OE
GND
/CE
A0
: Address inputs
I/O0 to I/O15 : Data Inputs / Outputs
/CE
: Chip Enable
/WE
: Write Enable
/OE
: Output Enable
/RESET
: Hardware reset input
RY (/BY)
: Ready (Busy) output
/WP (ACC)
: Write Protect (Accelerated) input
VCC
: Supply Voltage
VCCQ
: Input / Output Supply Voltage
GND
: Ground
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M16062EJ2V0DS
3
µPD29F064115-X
63-pin TAPE FBGA (11 × 8)
[ µPD29F064115F9-DB80X-CD6 ]
[ µPD29F064115F9-DB85X-CD6 ]
[ µPD29F064115F9-EB85X-CD6 ]
[ µPD29F064115F9-EB90X-CD6 ]
Top View
Bottom View
8
7
6
5
4
3
2
1
A B C D E F G H J K L M
M L K J H G F E D C B A
Top View
A
B
8
NC
NC
7
NC
NC
6
5
C
D
E
3
2
NC
1
NC
G
H
J
K
A13
A12
A14
A15
A16
VCCQ
I/O15
GND
A9
A8
A10
A11
I/O7
I/O14
I/O13
I/O6
/WE
/RESET
A21
A19
I/O5
I/O12
VCC
I/O4
A18
A20
I/O2
I/O10
I/O11
I/O3
RY(/BY) /WP(ACC)
4
F
A7
A17
A6
A5
I/O0
I/O8
I/O9
I/O1
A3
A4
A2
A1
A0
/CE
/OE
GND
NC
A0 to A21
L
M
NC
NC
NC
NC
NC
NC
NC
NC
: Address inputs
I/O0 to I/O15 : Data Inputs / Outputs
/CE
: Chip Enable
/WE
: Write Enable
/OE
: Output Enable
/RESET
: Hardware reset input
RY (/BY)
: Ready (Busy) output
/WP (ACC)
: Write Protect (Accelerated) input
VCC
: Supply Voltage
VCCQ
: Input / Output Supply Voltage
GND
NC
Note
: Ground
: No Connection
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the index mark.
4
Data Sheet M16062EJ2V0DS
µPD29F064115-X
85-pin TAPE FBGA (11 × 8)
[ µPD29F064115F9-DB80X-CD5 ]
[ µPD29F064115F9-DB85X-CD5 ]
[ µPD29F064115F9-EB85X-CD5 ]
[ µPD29F064115F9-EB90X-CD5 ]
Top View
Bottom View
10
9
8
7
6
5
4
3
2
1
Top View
Bottom View
M L K J H G F E D C B A
A B C D E F G H J K L M
A B C D E F G H
A
B
10
NC
NC
9
NC
NC
8
NC
7
C
D
Top View
E
F
H G F E D C B A
G
H
J
K
L
M
NC
NC
NC
NC
Top View
NC
D
NC
NC
A14
A14
A10
A10
A
8
7
6
NC
5
NC
4
6
5
4
3
2
NC
1
NC
3
NC
2
NC
1
NC
B
C
A15
A21
A15
NC
A12
A11
A13
A11
A13
A12
A19
A9
A8
A8
A19
A9
/WE
NC
A20
CE2s
A20
/WE
/WP(ACC) /RESET RY(/BY)
/WP(ACC) /RESET RY(/BY)
A18
A17
NC
NC
A18
A17
/LB
/UB
A4
A6
A7
A5
A7
A6
A5
A4
A2
A1
A3
A3
A2
A1
NC
NC
A0 to A21
NC
E
A16
A16
NC
SA
I/O6
I/O6
I/O1
I/O1
GND
VSS
A0
A0
NC
G
H
F
NC
GND
CIOf
VSS
I/O15
I/O14
I/O7
I/O15, A-1 I/O7
I/O14
I/O13
I/O12
I/O5
I/O12
I/O5
I/O13
VCCQ
I/O4
NC
I/O4
CIOs
VCCs
I/O3
I/O11
VCC
VCCf
I/O3
I/O11
I/O2
I/O9
I/O10
I/O9
I/O10
I/O2
I/O0
/OE
I/O8
/OE
I/O0
I/O8
NC
/CE
/CEf
/CE1s
NC
NC
NC
NC
NC
NC
NC
NC
: Address inputs
I/O0 to I/O15 : Data Inputs / Outputs
/CE
: Chip Enable
/WE
: Write Enable
/OE
: Output Enable
/RESET
: Hardware reset input
RY (/BY)
: Ready (Busy) output
/WP (ACC)
: Write Protect (Accelerated) input
VCC
: Supply Voltage
VCCQ
: Input / Output Supply Voltage
GND
NC
Note
: Ground
: No Connection
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the index mark.
INPUT / OUTPUT PIN FUNCTION
Refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
Data Sheet M16062EJ2V0DS
5
µPD29F064115-X
Block Diagram
VCC
VCCQ
GND
Bank A address
X-decoder
Cell matrix
(Bank A)
Y-decoder
Y-gating
Address latch
Address
buffers
Address latch
A0 to A21
Bank C address
X-decoder
Cell matrix
(Bank C)
Y-decoder
Y-gating
Bank / Sector
decoder
I/O0 to I/O15
/WP(ACC)
Program / Erase
voltage generator
/RESET
/WE
SA / WC
State
control
(Command
register)
Input / Output
buffers
Data latch circuit
/CE
/OE
SA / WC
Y-decoder
Y-gating
X-decode
Cell matrix
(Bank B)
Bank D address
6
Data Sheet M16062EJ2V0DS
Address latch
Bank B address
Address latch
RY(/BY)
Y-decoder
Y-gating
X-decoder
Cell matrix
(Bank D)
µPD29F064115-X
Sector Organization / Sector Address Table
Bank
Bank D
Sector
Organization
K words
4
4
4
4
4
4
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Bank C
32
32
32
32
32
32
32
32
32
32
32
32
32
Address
3FFFFFH
3FF000H
3FEFFFH
3FE000H
3FDFFFH
3FD000H
3FCFFFH
3FC000H
3FBFFFH
3FB000H
3FAFFFH
3FA000H
3F9FFFH
3F9000H
3F8FFFH
3F8000H
3F7FFFH
3F0000H
3EFFFFH
3E8000H
3E7FFFH
3E0000H
3DFFFFH
3D8000H
3D7FFFH
3D0000H
3CFFFFH
3C8000H
3C7FFFH
3C0000H
3B7FFFH
3B8000H
3B7FFFH
3B0000H
3AFFFFH
3A8000H
3A7FFFH
3A0000H
39FFFFH
398000H
397FFFH
390000H
38FFFFH
388000H
387FFFH
380000H
37FFFFH
378000H
377FFFH
370000H
36FFFFH
368000H
367FFFH
360000H
35FFFFH
358000H
357FFFH
350000H
34FFFFH
348000H
347FFFH
340000H
33FFFFH
338000H
337FFFH
330000H
32FFFFH
328000H
327FFFH
320000H
31FFFFH
318000H
(1/4)
Sectors
Address
Sector Address Table
Bank Address Table
SA141
A21
1
A20
1
A19
1
A18
1
A17
1
A16
1
A15
1
A14
1
A13
1
A12
1
SA140
1
1
1
1
1
1
1
1
1
0
SA139
1
1
1
1
1
1
1
1
0
1
SA138
1
1
1
1
1
1
1
1
0
0
SA137
1
1
1
1
1
1
1
0
1
1
SA136
1
1
1
1
1
1
1
0
1
0
SA135
1
1
1
1
1
1
1
0
0
1
SA134
1
1
1
1
1
1
1
0
0
0
SA133
1
1
1
1
1
1
0
x
x
x
SA132
1
1
1
1
1
0
1
x
x
x
SA131
1
1
1
1
1
0
0
x
x
x
SA130
1
1
1
1
0
1
1
x
x
x
SA129
1
1
1
1
0
1
0
x
x
x
SA128
1
1
1
1
0
0
1
x
x
x
SA127
1
1
1
1
0
0
0
x
x
x
SA126
1
1
1
0
1
1
1
x
x
x
SA125
1
1
1
0
1
1
0
x
x
x
SA124
1
1
1
0
1
0
1
x
x
x
SA123
1
1
1
0
1
0
0
x
x
x
SA122
1
1
1
0
0
1
1
x
x
x
SA121
1
1
1
0
0
1
0
x
x
x
SA120
1
1
1
0
0
0
1
x
x
x
SA119
1
1
1
0
0
0
0
x
x
x
SA118
1
1
0
1
1
1
1
x
x
x
SA117
1
1
0
1
1
1
0
x
x
x
SA116
1
1
0
1
1
0
1
x
x
x
SA115
1
1
0
1
1
0
0
x
x
x
SA114
1
1
0
1
0
1
1
x
x
x
SA113
1
1
0
1
0
1
0
x
x
x
SA112
1
1
0
1
0
0
1
x
x
x
SA111
1
1
0
1
0
0
0
x
x
x
SA110
1
1
0
0
1
1
1
x
x
x
SA109
1
1
0
0
1
1
0
x
x
x
SA108
1
1
0
0
1
0
1
x
x
x
SA107
1
1
0
0
1
0
0
x
x
x
SA106
1
1
0
0
0
1
1
x
x
x
Data Sheet M16062EJ2V0DS
7
µPD29F064115-X
Sector Organization / Sector Address Table
Bank
Bank C
Sector
Organization
K words
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
8
Address
317FFFH
310000H
30FFFFH
308000H
307FFFH
300000H
2FFFFFH
2F8000H
2F7FFFH
2F0000H
2EFFFFH
2E8000H
2E7FFFH
2E0000H
2DFFFFH
2D8000H
2D7FFFH
2D0000H
2CFFFFH
2C8000H
2C7FFFH
2C0000H
2BFFFFH
2B8000H
2B7FFFH
2B0000H
2AFFFFH
2A8000H
2A7FFFH
2A0000H
29FFFFH
298000H
297FFFH
290000H
28FFFFH
288000H
287FFFH
280000H
27FFFFH
278000H
277FFFH
270000H
26FFFFH
268000H
267FFFH
260000H
25FFFFH
258000H
257FFFH
250000H
24FFFFH
248000H
247FFFH
240000H
23FFFFH
238000H
237FFFH
230000H
22FFFFH
228000H
227FFFH
220000H
21FFFFH
218000H
217FFFH
210000H
20FFFFH
208000H
207FFFH
200000H
(2/4)
Sectors
Address
Sector Address Table
Bank Address Table
SA105
A21
1
A20
1
A19
0
A18
0
A17
0
A16
1
A15
0
A14
x
A13
x
A12
x
SA104
1
1
0
0
0
0
1
x
x
x
SA103
1
1
0
0
0
0
0
x
x
x
SA102
1
0
1
1
1
1
1
x
x
x
SA101
1
0
1
1
1
1
0
x
x
x
SA100
1
0
1
1
1
0
1
x
x
x
SA99
1
0
1
1
1
0
0
x
x
x
SA98
1
0
1
1
0
1
1
x
x
x
SA97
1
0
1
1
0
1
0
x
x
x
SA96
1
0
1
1
0
0
1
x
x
x
SA95
1
0
1
1
0
0
0
x
x
x
SA94
1
0
1
0
1
1
1
x
x
x
SA93
1
0
1
0
1
1
0
x
x
x
SA92
1
0
1
0
1
0
1
x
x
x
SA91
1
0
1
0
1
0
0
x
x
x
SA90
1
0
1
0
0
1
1
x
x
x
SA89
1
0
1
0
0
1
0
x
x
x
SA88
1
0
1
0
0
0
1
x
x
x
SA87
1
0
1
0
0
0
0
x
x
x
SA86
1
0
0
1
1
1
1
x
x
x
SA85
1
0
0
1
1
1
0
x
x
x
SA84
1
0
0
1
1
0
1
x
x
x
SA83
1
0
0
1
1
0
0
x
x
x
SA82
1
0
0
1
0
1
1
x
x
x
SA81
1
0
0
1
0
1
0
x
x
x
SA80
1
0
0
1
0
0
1
x
x
x
SA79
1
0
0
1
0
0
0
x
x
x
SA78
1
0
0
0
1
1
1
x
x
x
SA77
1
0
0
0
1
1
0
x
x
x
SA76
1
0
0
0
1
0
1
x
x
x
SA75
1
0
0
0
1
0
0
x
x
x
SA74
1
0
0
0
0
1
1
x
x
x
SA73
1
0
0
0
0
1
0
x
x
x
SA72
1
0
0
0
0
0
1
x
x
x
SA71
1
0
0
0
0
0
0
x
x
x
Data Sheet M16062EJ2V0DS
µPD29F064115-X
Sector Organization / Sector Address Table
Bank
Bank B
Sector
Organization
K words
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Address
1FFFFFH
1F8000H
1F7FFFH
1F0000H
1EFFFFH
1E8000H
1E7FFFH
1E0000H
1DFFFFH
1D8000H
1D7FFFH
1D0000H
1CFFFFH
1C8000H
1C7FFFH
1C0000H
1BFFFFH
1B8000H
1B7FFFH
1B0000H
1AFFFFH
1A8000H
1A7FFFH
1A0000H
19FFFFH
198000H
197FFFH
190000H
18FFFFH
188000H
187FFFH
180000H
17FFFFH
178000H
177FFFH
170000H
16FFFFH
168000H
167FFFH
160000H
15FFFFH
158000H
157FFFH
150000H
14FFFFH
148000H
147FFFH
140000H
13FFFFH
138000H
137FFFH
130000H
12FFFFH
128000H
127FFFH
120000H
11FFFFH
118000H
117FFFH
110000H
10FFFFH
108000H
107FFFH
100000H
0FFFFFH
0F8000H
0F7FFFH
0F0000H
0EFFFFH
0E8000H
0E7FFFH
0E0000H
(3/4)
Sectors
Address
Sector Address Table
Bank Address Table
SA70
A21
0
A20
1
A19
1
A18
1
A17
1
A16
1
A15
1
A14
x
A13
x
A12
x
SA69
0
1
1
1
1
1
0
x
x
x
SA68
0
1
1
1
1
0
1
x
x
x
SA67
0
1
1
1
1
0
0
x
x
x
SA66
0
1
1
1
0
1
1
x
x
x
SA65
0
1
1
1
0
1
0
x
x
x
SA64
0
1
1
1
0
0
1
x
x
x
SA63
0
1
1
1
0
0
0
x
x
x
SA62
0
1
1
0
1
1
1
x
x
x
SA61
0
1
1
0
1
1
0
x
x
x
SA60
0
1
1
0
1
0
1
x
x
x
SA59
0
1
1
0
1
0
0
x
x
x
SA58
0
1
1
0
0
1
1
x
x
x
SA57
0
1
1
0
0
1
0
x
x
x
SA56
0
1
1
0
0
0
1
x
x
x
SA55
0
1
1
0
0
0
0
x
x
x
SA54
0
1
0
1
1
1
1
x
x
x
SA53
0
1
0
1
1
1
0
x
x
x
SA52
0
1
0
1
1
0
1
x
x
x
SA51
0
1
0
1
1
0
0
x
x
x
SA50
0
1
0
1
0
1
1
x
x
x
SA49
0
1
0
1
0
1
0
x
x
x
SA48
0
1
0
1
0
0
1
x
x
x
SA47
0
1
0
1
0
0
0
x
x
x
SA46
0
1
0
0
1
1
1
x
x
x
SA45
0
1
0
0
1
1
0
x
x
x
SA44
0
1
0
0
1
0
1
x
x
x
SA43
0
1
0
0
1
0
0
x
x
x
SA42
0
1
0
0
0
1
1
x
x
x
SA41
0
1
0
0
0
1
0
x
x
x
SA40
0
1
0
0
0
0
1
x
x
x
SA39
0
1
0
0
0
0
0
x
x
x
SA38
0
0
1
1
1
1
1
x
x
x
SA37
0
0
1
1
1
1
0
x
x
x
SA36
0
0
1
1
1
0
1
x
x
x
SA35
0
0
1
1
1
0
0
x
x
x
Data Sheet M16062EJ2V0DS
9
µPD29F064115-X
Sector Organization / Sector Address Table
Bank
Bank B
Sector
Organization
K words
32
32
32
32
32
32
32
32
32
32
32
32
Bank A
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
4
4
4
4
4
4
4
10
Address
0DFFFFH
0D8000H
0D7FFFH
0D0000H
0CFFFFH
0C8000H
0C7FFFH
0C0000H
0BFFFFH
0B8000H
0B7FFFH
0B0000H
0AFFFFH
0A8000H
0A7FFFH
0A0000H
09FFFFH
098000H
097FFFH
090000H
08FFFFH
088000H
087FFFH
080000H
07FFFFH
078000H
077FFFH
070000H
06FFFFH
068000H
067FFFH
060000H
05FFFFH
058000H
057FFFH
050000H
04FFFFH
048000H
047FFFH
040000H
03FFFFH
038000H
037FFFH
030000H
02FFFFH
028000H
027FFFH
020000H
01FFFFH
018000H
017FFFH
010000H
00FFFFH
008000H
007FFFH
007000H
006FFFH
006000H
005FFFH
005000H
004FFFH
004000H
003FFFH
003000H
002FFFH
002000H
001FFFH
001000H
000FFFH
000000H
(4/4)
Sectors
Address
Sector Address Table
Bank Address Table
SA34
A21
0
A20
0
A19
1
A18
1
A17
0
A16
1
A15
1
A14
x
A13
x
A12
x
SA33
0
0
1
1
0
1
0
x
x
x
SA32
0
0
1
1
0
0
1
x
x
x
SA31
0
0
1
1
0
0
0
x
x
x
SA30
0
0
1
0
1
1
1
x
x
x
SA29
0
0
1
0
1
1
0
x
x
x
SA28
0
0
1
0
1
0
1
x
x
x
SA27
0
0
1
0
1
0
0
x
x
x
SA26
0
0
1
0
0
1
1
x
x
x
SA25
0
0
1
0
0
1
0
x
x
x
SA24
0
0
1
0
0
0
1
x
x
x
SA23
0
0
1
0
0
0
0
x
x
x
SA22
0
0
0
1
1
1
1
x
x
x
SA21
0
0
0
1
1
1
0
x
x
x
SA20
0
0
0
1
1
0
1
x
x
x
SA19
0
0
0
1
1
0
0
x
x
x
SA18
0
0
0
1
0
1
1
x
x
x
SA17
0
0
0
1
0
1
0
x
x
x
SA16
0
0
0
1
0
0
1
x
x
x
SA15
0
0
0
1
0
0
0
x
x
x
SA14
0
0
0
0
1
1
1
x
x
x
SA13
0
0
0
0
1
1
0
x
x
x
SA12
0
0
0
0
1
0
1
x
x
x
SA11
0
0
0
0
1
0
0
x
x
x
SA10
0
0
0
0
0
1
1
x
x
x
SA9
0
0
0
0
0
1
0
x
x
x
SA8
0
0
0
0
0
0
1
x
x
x
SA7
0
0
0
0
0
0
0
1
1
1
SA6
0
0
0
0
0
0
0
1
1
0
SA5
0
0
0
0
0
0
0
1
0
1
SA4
0
0
0
0
0
0
0
1
0
0
SA3
0
0
0
0
0
0
0
0
1
1
SA2
0
0
0
0
0
0
0
0
1
0
SA1
0
0
0
0
0
0
0
0
0
1
SA0
0
0
0
0
0
0
0
0
0
0
Data Sheet M16062EJ2V0DS
µPD29F064115-X
Sector Group Address Table
Sector group
(1/2)
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Size
Sector
SGA0
0
0
0
0
0
0
0
0
0
0
4K words (1 Sector)
SA0
SGA1
0
0
0
0
0
0
0
0
0
1
4K words (1 Sector)
SA1
SGA2
0
0
0
0
0
0
0
0
1
0
4K words (1 Sector)
SA2
SGA3
0
0
0
0
0
0
0
0
1
1
4K words (1 Sector)
SA3
SGA4
0
0
0
0
0
0
0
1
0
0
4K words (1 Sector)
SA4
SGA5
0
0
0
0
0
0
0
1
0
1
4K words (1 Sector)
SA5
SGA6
0
0
0
0
0
0
0
1
1
0
4K words (1 Sector)
SA6
SGA7
0
0
0
0
0
0
0
1
1
1
4K words (1 Sector)
SA7
SGA8
0
0
0
0
0
0
1
×
×
×
96K words (3 Sectors)
SA8 to SA10
1
0
1
1
SGA9
0
0
0
0
1
×
×
×
×
×
128K words (4 Sectors)
SA11 to SA14
SGA10
0
0
0
1
0
×
×
×
×
×
128K words (4 Sectors)
SA15 to SA18
SGA11
0
0
0
1
1
×
×
×
×
×
128K words (4 Sectors)
SA19 to SA22
SGA12
0
0
1
0
0
×
×
×
×
×
128K words (4 Sectors)
SA23 to SA26
SGA13
0
0
1
0
1
×
×
×
×
×
128K words (4 Sectors)
SA27 to SA30
SGA14
0
0
1
1
0
×
×
×
×
×
128K words (4 Sectors)
SA31 to SA34
SGA15
0
0
1
1
1
×
×
×
×
×
128K words (4 Sectors)
SA35 to SA38
SGA16
0
1
0
0
0
×
×
×
×
×
128K words (4 Sectors)
SA39 to SA42
SGA17
0
1
0
0
1
×
×
×
×
×
128K words (4 Sectors)
SA43 to SA46
SGA18
0
1
0
1
0
×
×
×
×
×
128K words (4 Sectors)
SA47 to SA50
SGA19
0
1
0
1
1
×
×
×
×
×
128K words (4 Sectors)
SA51 to SA54
SGA20
0
1
1
0
0
×
×
×
×
×
128K words (4 Sectors)
SA55 to SA58
SGA21
0
1
1
0
1
×
×
×
×
×
128K words (4 Sectors)
SA59 to SA62
SGA22
0
1
1
1
0
×
×
×
×
×
128K words (4 Sectors)
SA63 to SA66
SGA23
0
1
1
1
1
×
×
×
×
×
128K words (4 Sectors)
SA67 to SA70
Remark × : VIH or VIL
Data Sheet M16062EJ2V0DS
11
µPD29F064115-X
Sector Group Address Table
Sector group
(2/2)
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
Size
Sector
SGA24
1
0
0
0
0
×
×
×
×
×
128K words (4 Sectors) SA71 to SA74
SGA25
1
0
0
0
1
×
×
×
×
×
128K words (4 Sectors) SA75 to SA78
SGA26
1
0
0
1
0
×
×
×
×
×
128K words (4 Sectors) SA79 to SA82
SGA27
1
0
0
1
1
×
×
×
×
×
128K words (4 Sectors) SA83 to SA86
SGA28
1
0
1
0
0
×
×
×
×
×
128K words (4 Sectors) SA87 to SA90
SGA29
1
0
1
0
1
×
×
×
×
×
128K words (4 Sectors) SA91 to SA94
SGA30
1
0
1
1
0
×
×
×
×
×
128K words (4 Sectors) SA95 to SA98
SGA31
1
0
1
1
1
×
×
×
×
×
128K words (4 Sectors) SA99 to SA102
SGA32
1
1
0
0
0
×
×
×
×
×
128K words (4 Sectors) SA103 to SA106
SGA33
1
1
0
0
1
×
×
×
×
×
128K words (4 Sectors) SA107 to SA110
SGA34
1
1
0
1
0
×
×
×
×
×
128K words (4 Sectors) SA111 to SA114
SGA35
1
1
0
1
1
×
×
×
×
×
128K words (4 Sectors) SA115 to SA118
SGA36
1
1
1
0
0
×
×
×
×
×
128K words (4 Sectors) SA119 to SA122
SGA37
1
1
1
0
1
×
×
×
×
×
128K words (4 Sectors) SA123 to SA126
SGA38
1
1
1
1
0
×
×
×
×
×
128K words (4 Sectors) SA127 to SA130
SGA39
1
1
1
1
1
0
0
×
×
×
96K words (3 Sectors)
SA131 to SA133
0
1
1
0
SGA40
1
1
1
1
1
1
1
0
0
0
4K words (1 Sector)
SA134
SGA41
1
1
1
1
1
1
1
0
0
1
4K words (1 Sector)
SA135
SGA42
1
1
1
1
1
1
1
0
1
0
4K words (1 Sector)
SA136
SGA43
1
1
1
1
1
1
1
0
1
1
4K words (1 Sector)
SA137
SGA44
1
1
1
1
1
1
1
1
0
0
4K words (1 Sector)
SA138
SGA45
1
1
1
1
1
1
1
1
0
1
4K words (1 Sector)
SA139
SGA46
1
1
1
1
1
1
1
1
1
0
4K words (1 Sector)
SA140
SGA47
1
1
1
1
1
1
1
1
1
1
4K words (1 Sector)
SA141
Remark × : VIH or VIL
12
Data Sheet M16062EJ2V0DS
µPD29F064115-X
Product ID Code (Manufacturer Code / Device Code)
Product ID Code
Output code
I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
HEX
Manufacturer Code
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0010H
Device code
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
0
221CH
Sector group protection
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0001H Note
Note If 0001H is output, the sector group is protected. If 0000H is output, the sector group is unprotected.
Data Sheet M16062EJ2V0DS
13
µPD29F064115-X
Command Sequence
Command sequence
Bus
1st bus Cycle
Cycle Address
3rd bus Cycle
4th bus Cycle
5th bus Cycle
6th bus Cycle
Data
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
×××H
F0H
RA
RD
–
–
–
–
–
–
–
–
3
555H
AAH
2AAH
55H
555H
F0H
RA
RD
–
–
–
–
Read / Reset
Note1
1
Read / Reset
Note1
Program
2nd bus Cycle
4
555H
AAH
2AAH
55H
555H
A0H
PA
PD
–
–
–
–
Program Suspend
Note 2
1
BA
B0H
–
–
–
–
–
–
–
–
–
–
Program Resume
Note 3
1
BA
30H
–
–
–
–
–
–
–
–
–
–
6
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
555H
10H
Chip Erase
Sector Erase
6
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
SA
30H
Sector Erase Suspend
Note 4, 5
1
BA
B0H
–
–
–
–
–
–
–
–
–
–
Sector Erase Resume
Note 4, 6
1
BA
30H
–
–
–
–
–
–
–
–
–
–
3
555H
AAH
2AAH
55H
555H
20H
–
–
–
–
–
–
2
×××H
A0H
PA
PD
–
–
–
–
–
–
–
–
2
×××H
80H
×××H
10H
–
–
–
–
–
–
–
–
2
×××H
80H
SA
30H
–
–
–
–
–
–
–
–
2
×××H
90H
×××H
3
555H
AAH
2AAH
Unlock Bypass Set
Unlock Bypass Program
Note 7
Unlock Bypass Chip Erase
Note 7
Unlock Bypass Sector Erase
Unlock Bypass Reset
Note 7
Note 7
Product ID / Sector Group Protection
Note11
00H
55H
Information / Read Mode Register
–
–
–
–
–
–
–
–
(BA)
90H
IA
ID
–
–
–
–
555H
Information
Sector Group Protection
Note 8
4
×××H
60H
SPA
60H
SPA
40H
SPA
SD
–
–
–
–
Sector Group Unprotect
Note 9
4
×××H
60H
SUA
60H
SUA
40H
SUA
SD
–
–
–
–
Extra One Time Protect Sector Entry
3
555H
AAH
2AAH
55H
555H
88H
–
–
–
–
–
–
Extra One Time Protect
4
555H
AAH
2AAH
55H
555H
90H
xxxH
00H
–
–
–
–
4
555H
AAH
2AAH
55H
555H
A0H
PA
PD
–
–
–
–
6
555H
AAH
2AAH
55H
555H
80H
555H
AAH
2AAH
55H
EOTPSA
30H
4
×××H
60H
EOTPSA
60H
EOTPSA
40H
EOTPSA
SD
–
–
–
–
3
555H
AAH
2AAH
55H
REGD
C0H
–
–
–
–
–
–
Sector Reset
Note 10
Extra One Time Protect Sector
Program
Note 10
Extra One Time Protect
Sector Erase
Note 10
Extra One Time Protect Sector
Protection
Note 10
Read Mode Register Set
14
Data Sheet M16062EJ2V0DS
µPD29F064115-X
Notes 1. Both these read / reset commands reset the device to the read mode.
2. Programming is suspended if B0H is input to the bank address being programmed to in a program
operation.
3. Programming is resumed if 30H is input to the bank address being suspended to in a program-suspend
operation.
4. If automatic erase resume and suspend are repeated at intervals of less than 100 µ s, since it will become
suspend operation, without starting automatic erase, the erase operation may not be correctly completed.
5. Erasure is suspended if B0H is input to the bank address being erased in a sector erase operation.
6. Erasure is resumed if 30H is input to the bank address being suspended in a sector-erase-suspend
operation.
7. Valid only in the Unlock Bypass mode.
8. Valid only in /RESET = VID (except in the Extra One Time Protect Sector mode).
9. The command sequence that protects a sector group is excluded.
10. Valid only in the Extra One Time Protect Sector mode.
11. This command can be used even if this data is F0H.
Remarks 1. The system should generate the following address pattern:
555H or 2AAH (A10 to A0)
2. RA
: Read address
RD
: Read data
IA
: Address input as follows
Information
ID
A21 to A12
A11 to A4
A3 to A0
Manufacturer code
Bank address
Don’t care
0000
Device code
Bank address
Don’t care
0001
Sector group protection information
Sector group address
Don’t care
0010
Read mode register information
Bank address
Don’t care
0100
: Code output. For the manufacture code, device code and sector group protection information,
refer to the Product ID code (Manufacture Code / Device Code). For read mode register
information, refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY
Information (M15451E).
PA
: Program address
PD
: Program data
SA
: Erase sector address. The sector to be erased is selected by the combination of A21 to A12.
Refer to the Sector Organization / Sector Address Table.
BA
: Bank address. Refer to the Sector Organization / Sector Address Table.
Data Sheet M16062EJ2V0DS
15
µPD29F064115-X
SPA
: Sector group address to be protected or protection-verified. Set the sector group address
(SGA) and (A6, A3, A2, A1, A0) = (VIL, VIL, VIL, VIH, VIL).
Sector group protection can be set for each sector group address. For details, refer to PAGE
MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
Refer to the Sector Group Address Table for the sector group address.
SUA
: Sector group address to be unprotected or unprotection-verified. Set the sector group address
(SGA) and (A6, A3, A2, A1, A0) = (VIH, VIL, VIL, VIH, VIL).
Sector group unprotect is performed for all sector group using a single command, however,
unprotect verification must be performed for each sector group address. For details, refer to
PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
Refer to the Sector Group Address Table for the sector group address.
EOTPSA : Extra One Time Protect Sector area addresses. These addresses are 000000H to 007FFFH.
SD
: Data for verifying whether sector groups read from the address specified by SPA, SUA,
EOTPSA are protected or unprotected.
REGD
: Read mode register information. Description for setting, refer to PAGE MODE FLASH
MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
3. The sector group address is don't care except when a program / erase address or read address are
selected.
4. For the operation of bus, refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY
Information (M15451E).
5. × of address bit indicates VIH or VIL.
BUS OPERATIONS, COMMANDS, HARDWARE SEQUENCE FLAGS, HARDWARE DATA PROTECTION
Refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
16
Data Sheet M16062EJ2V0DS
µPD29F064115-X
Electrical Characteristics
Before turning on power, input GND ± 0.2 V to the /RESET pin until VCC ≥ VCC (MIN.) and keep that state for 200 µs.
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Supply voltage
VCC
with respect to GND
–0.5 to +2.4
V
Input / Output
VCCQ
with respect to GND
–0.5 to +4.0
V
–0.5 Note 1 to VCCQ + 0.5 Note 2
V
supply voltage
Input voltage
VIN
with respect except /WP(ACC), /RESET
to GND
/WP(ACC), /RESET
–0.5
with respect to GND
–0.5
Note 1
Note 1
to VCCQ + 0.5 Note 2
to +13.0
Input /Output voltage
VI/O
V
Ambient operation
TA
–25 to +85
°C
Tstg
–65 to +150
°C
temperature
Storage temperature
Tbias
at bias
–25 to +85
Notes 1. –2.0 V (MIN.) (pulse width ≤ 20 ns)
2. VCCQ + 2.0 V (MAX.) (pulse width ≤ 20 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Input / Output supply voltage
High level input voltage
Symbol
Test condition
-DB80X, -DB85X
-EB85X, -EB90X
MIN.
MAX.
MIN.
MAX.
VCC
1.8
2.1
1.65
1.95
VCCQ
2.7
3.3
2.7
3.3
VIH
VID
High voltage is
2.4
VCCQ+0.3
9.0
Note1
Unit
V
V
Note1
2.4
VCCQ+0.3
11.0
9.0
11.0
V
−0.5 Note2
+0.5
−0.5 Note2
+0.5
V
8.5
9.5
8.5
9.5
V
−25
+85
−25
+85
°C
V
applied (/RESET)
Low level input voltage
Accelerated programming
VIL
VACC
voltage
High voltage is
applied
Ambient operating temperature
Notes 1.
TA
VCCQ + 0.6 V (MAX.) (pulse width ≤ 20 ns)
2. –0.6 V (MIN.) (pulse width ≤ 20 ns)
Data Sheet M16062EJ2V0DS
17
µPD29F064115-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
(1/2)
-DB80X, -DB85X
MIN.
High level output voltage
VOH1
IOH = −2.0 mA, VCC = VCC (MIN.),
TYP.
Unit
MAX.
2.4
V
VCCQ = VCCQ (MIN.)
VOH2
IOH = −100 µA, VCC = VCC (MIN.),
VCCQ–0.1
VCCQ = VCCQ (MIN.)
Low level output voltage
VOL
IOL = 4.0 mA, VCCQ = VCCQ (MIN.)
0.45
V
Input leakage current
ILI1
VIN = GND to VCCQ, VCCQ = VCCQ (MAX.)
1.0
µA
ILI2
/RESET = 11.0 V
35
I/O leakage current
High voltage is applied
ILO
VI/O = GND to VCCQ, VCCQ = VCCQ (MAX.)
1.0
µA
Power
Read
ICC1
/CE = VIL, /OE = VIH, Cycle = 5 MHz, IOUT = 0 mA
20
mA
supply
Program, Erase
ICC2
/CE = VIL, /OE = VIH,
35
mA
15
25
µA
current
10
Automatic programming / erase
Standby
ICC3
VCC = VCC(MAX.) , /OE = VIL,
/CE = /RESET = /WP(ACC) = VCCQ ± 0.3 V
Standby / Reset
ICC4
VCC = VCC (MAX.), /RESET = GND ± 0.2 V
15
25
µA
Automatic sleep mode
ICC5
VIH = VCCQ ± 0.2 V, VIL = GND ± 0.2 V
15
25
µA
Read during
ICC6
VIH = VCCQ ± 0.2 V, VIL = GND ± 0.2 V
55
mA
Read during erasing
ICC7
VIH = VCCQ ± 0.2 V, VIL = GND ± 0.2 V
55
mA
Programming
ICC8
/CE = VIL, /OE = VIH,
35
mA
mA
programming
during suspend
Automatic programming during suspend
Accelerated
IACC
programming
Note
Low VCC lock-out voltage
/WP (ACC) pin
5
10
VCC
15
35
VLKO
1.0
V
Note When VCC is equal to or lower than VLKO, the device ignores all write cycles. Refer to PAGE MODE FLASH
MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
Remark
18
VIN : Input voltage, VI/O : Input / Output voltage
Data Sheet M16062EJ2V0DS
µPD29F064115-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
(2/2)
-EB85X, -EB90X
MIN.
High level output voltage
VOH1
IOH = −2.0 mA, VCC = VCC (MIN.),
TYP.
Unit
MAX.
2.4
V
VCCQ = VCCQ (MIN.)
VOH2
IOH = −100 µA, VCC = VCC (MIN.),
VCCQ–0.1
VCCQ = VCCQ (MIN.)
Low level output voltage
VOL
IOL = 4.0 mA, VCCQ = VCCQ (MIN.)
0.45
V
Input leakage current
ILI1
VIN = GND to VCCQ, VCCQ = VCCQ (MAX.)
1.0
µA
ILI2
/RESET = 11.0 V
35
I/O leakage current
High voltage is applied
ILO
VI/O = GND to VCCQ, VCCQ = VCCQ (MAX.)
1.0
µA
Power
Read
ICC1
/CE = VIL, /OE = VIH, Cycle = 5 MHz, IOUT = 0 mA
15
mA
supply
Program, Erase
ICC2
/CE = VIL, /OE = VIH,
25
mA
15
25
µA
current
8
Automatic programming / erase
Standby
ICC3
VCC = VCC(MAX.), /OE = VIL,
/CE = /RESET = /WP(ACC) = VCCQ ± 0.3 V
Standby / Reset
ICC4
VCC = VCC (MAX.), /RESET = GND ± 0.2 V
15
25
µA
Automatic sleep mode
ICC5
VIH = VCCQ ± 0.2 V, VIL = GND ± 0.2 V
15
25
µA
Read during
ICC6
VIH = VCCQ ± 0.2 V, VIL = GND ± 0.2 V
40
mA
Read during erasing
ICC7
VIH = VCCQ ± 0.2 V, VIL = GND ± 0.2 V
40
mA
Programming
ICC8
/CE = VIL, /OE = VIH,
25
mA
mA
programming
during suspend
Automatic programming during suspend
Accelerated
IACC
programming
Note
Low VCC lock-out voltage
/WP (ACC) pin
5
10
VCC
12
25
VLKO
1.0
V
Note When VCC is equal to or lower than VLKO, the device ignores all write cycles. Refer to PAGE MODE FLASH
MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
Remark
VIN : Input voltage, VI/O : Input / Output voltage
Capacitance (TA = 25°°C, f = 1 MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
CIN
VIN = 0 V
6.0
7.5
pF
Input / Output capacitance
CI/O
VI/O = 0 V
8.5
12.0
pF
Remarks 1. VIN : Input voltage, VI/O : Input / Output voltage
2. These parameters are not 100% tested.
Data Sheet M16062EJ2V0DS
19
µPD29F064115-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Input Waveform (Rise and Fall Time ≤ 5 ns)
VCCQ
VCCQ / 2
Test points
VCCQ / 2
VCCQ / 2
Test points
VCCQ / 2
0V
Output Waveform
Output Load
1 TTL + 30 pF
20
Data Sheet M16062EJ2V0DS
µPD29F064115-X
Read Cycle
Parameter
Symbol
-DB80X
-DB85X
-EB90X
Unit
Note
-EB85X
MIN.
MAX.
MAX.
MAX.
tRC
Address access time
tACC
Page read cycle time
tPRC
Page address access time
tPACC
30
30
30
ns
1
/CE access time
tCE
80
85
90
ns
2
/OE access time
tOE
25
25
25
ns
Output disable time
tDF
25
25
25
ns
Output hold time
tOH
0
0
0
ns
/RESET pulse width
tRP
500
500
500
ns
/RESET hold time before read
tRH
50
50
50
ns
At automatic mode
80
30
tREADY
to read mode Except automatic mode
/OE low level time from /WE high level
tOEH
85
MIN.
Read cycle time
/RESET low
80
MIN.
20
90
85
30
ns
90
30
ns
ns
20
20
20
µs
500
500
500
ns
20
20
1
ns
Notes 1. /CE = /OE = VIL
2. /OE = VIL
Remark
tDF is the time from inactivation of /CE or /OE to high impedance state output.
Data Sheet M16062EJ2V0DS
21
µPD29F064115-X
Write Cycle (Program / Erase)
Parameter
(1/2)
Symbol
-DB80X
-DB85X
-EB90X
Unit
Note
-EB85X
MIN.
TYP. MAX. MIN.
TYP. MAX. MIN.
TYP. MAX.
Write cycle time
tWC
80
85
90
ns
Address setup time (/WE to address)
tAS
0
0
0
ns
Address setup time (/CE to address)
tAS
0
0
0
ns
Address hold time (/WE to address)
tAH
45
45
45
ns
Address hold time (/CE to address)
tAH
45
45
45
ns
Input data setup time
tDS
45
45
45
ns
Input data hold time
tDH
0
0
0
ns
tOEH
0
0
0
ns
/OE hold time
Read
10
10
10
Read recovery time before write (/OE to /CE)
Toggle bit, Data polling
tGHEL
0
0
0
ns
Read recovery time before write (/OE to /WE)
tGHWL
0
0
0
ns
/WE setup time (/CE to /WE)
tWS
0
0
0
ns
/CE setup time (/WE to /CE)
tCS
0
0
0
ns
/WE hold time (/CE to /WE)
tWH
0
0
0
ns
/CE hold time (/WE to /CE)
tCH
0
0
0
ns
Write pulse width
tWP
35
35
35
ns
/CE pulse width
tCP
35
35
35
ns
Write pulse width high
tWPH
30
30
30
ns
/CE pulse width high
tCPH
30
30
30
ns
Word programming operation time
tWPG
11
200
11
200
11
200
µs
Chip programming operation time
tCPG
47
840
47
840
47
840
s
Sector erase
4K words sector
tSER
0.15
1.0
0.15
1.0
0.15
1.0
s
operation time
32K words sector
0.5
1.5
0.5
1.5
0.5
1.5
4K words sector
0.5
3.0
0.5
3.0
0.5
3.0
32K words sector
Chip erase operation time
Accelerated programming time
tCER
tACCPG
Program / erase cycle
0.7
5.0
0.7
5.0
0.7
5.0
65.4
205
65.4
205
65.4
205
96.2
678
96.2
678
96.2
678
7
150
7
150
7
150
1,3
s
µs
300,000
300,000
300,000
cycle
tVCS
200
200
200
µs
RY (/BY) recovery time
tRB
0
0
0
ns
/RESET pulse width
tRP
500
500
500
ns
/RESET high-voltage (VID) hold time from high of
tRRB
20
20
20
µs
tRH
50
50
50
ns
RY (/BY) when sector group is temporarily unprotect
Notes 1. The preprogramming time prior to the erase operation is not included.
2. Program / erase cycle : 100,000 cycles
3. Program / erase cycle : 300,000 cycles
22
Data Sheet M16062EJ2V0DS
1,2
1,3
VCC setup time
/RESET hold time
1,2
µPD29F064115-X
Write Cycle (Program / Erase)
Parameter
(2/2)
Symbol
-DB80X
-DB85X
-EB90X
Unit
Note
-EB85X
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.
From completion of automatic program /
tEOE
80
85
90
ns
tBUSY
80
85
90
ns
erase to data output time
RY (/BY) delay time from valid program or
erase operation
Address setup time to /OE low in toggle bit
tASO
15
15
15
ns
Address hold time to /CE or /OE high in toggle bit
tAHT
0
0
0
ns
/CE pulse width high for toggle bit
tCEPH
20
20
20
ns
/OE pulse width high for toggle bit
tOEPH
20
20
20
ns
Voltage transition time
tVLHT
4
4
4
µs
Rise time to VID (/RESET)
tVIDR
500
500
500
ns
tVACCR
500
500
500
ns
Erase timeout time
tTOW
50
50
50
µs
2
Erase suspend transition time
tSPD
µs
2
Rise time to VACC (/WP(ACC))
20
20
20
1
Notes 1. Sector group protection only.
2. Table only.
Write operation (Program / Erase) Performance
Parameter
Sector erase time
Chip erase time
Description
TYP.
MAX.
Unit
Note
0.15
1.0
s
1
prior to the erase operation 32K words sector
0.5
1.5
is not included.
4K words sector
0.5
3.0
32K words sector
0.7
5.0
The preprogramming time prior to
65.4
205
the erase operation is not included.
96.2
678
The preprogramming time
MIN.
4K words sector
2
s
2
Word programming time
Excludes system-level overhead
11
200
µs
Chip programming time
Excludes system-level overhead
47
840
s
Accelerated programming time
Excludes system-level overhead
7
150
Program / erase cycle
300,000
1
µs
cycle
Notes 1. Program / erase cycle : 100,000 cycles
2. Program / erase cycle : 300,000 cycles
TIMING CHARTS, FLOW CHARTS
Refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
Data Sheet M16062EJ2V0DS
23
µPD29F064115-X
Package Drawings
48-PIN PLASTIC TSOP (I) (12x20)
detail of lead end
1
48
F
G
R
Q
24
L
25
S
E
P
I
A
J
C
S
K
N
S
NOTES
1) Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
2) "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
B
D
M M
ITEM
A
MILLIMETERS
12.0±0.1
B
0.45 MAX.
C
0.5 (T.P.)
D
0.22±0.05
E
0.1±0.05
F
1.2 MAX.
G
1.0±0.05
I
18.4±0.1
J
0.8±0.2
K
0.145±0.05
L
0.5
M
0.10
N
0.10
P
20.0±0.2
Q
3°+5°
−3°
R
0.25
S
0.60±0.15
S48GZ-50-MJH-1
24
Data Sheet M16062EJ2V0DS
µPD29F064115-X
63-PIN TAPE FBGA (11x8)
w S B
E
ZD
ZE
B
8
7
6
5
4
3
2
1
D
A
M L K J H G F E D C B A
w S A
INDEX MARK
A
y1
A2
S
S
y
S
A1
e
φb
φx
M
S AB
Data Sheet M16062EJ2V0DS
ITEM
D
MILLIMETERS
8.00±0.10
E
11.00±0.10
w
0.20
A
0.97±0.10
A1
0.27±0.05
A2
0.70
e
0.80
b
0.45±0.05
x
0.08
y
0.10
y1
0.20
ZD
1.20
ZE
1.10
P63F9-80-CD6
25
µPD29F064115-X
85-PIN TAPE FBGA (11x8)
ZD
w S B
E
ZE
B
10
9
8
7
6
5
4
3
2
1
D
A
INDEX MARK
w S A
M L K J HG F E D C B A
A
y1
A2
S
S
y
φb
26
A1
e
S
φx
M
S AB
Data Sheet M16062EJ2V0DS
ITEM
D
MILLIMETERS
8.00±0.10
E
11.00±0.10
w
0.20
e
0.80
A
1.11±0.10
A1
0.27±0.05
A2
0.84
b
0.45±0.05
x
0.08
y
0.10
y1
0.20
ZD
0.40
ZE
1.10
P85F9-80-CD5
µPD29F064115-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD29F064115-X.
Types of Surface Mount Device
µPD29F064115GZ-MJH : 48-pin PLASTIC TSOP(I) (12 × 20) (Normal bent)
µPD29F064115F9-CD6 : 63-pin TAPE FBGA (11 × 8)
µPD29F064115F9-CD5 : 85-pin TAPE FBGA (11 × 8)
Data Sheet M16062EJ2V0DS
27
µPD29F064115-X
Revision History
Edition/
Date
Page
Type of
This
Previous
edition
edition
2nd edition/
Throughout
−
Sep.2002
p.16
p.14
p.21
p.19
28
Location
Description
revision
(Previous edition -> This edition)
−
Modification
Addition
Preliminary Data Sheet → Data Sheet
Command Sequence
Remark 2 : SPA, SUA
Read Cycle
tOEH
Data Sheet M16062EJ2V0DS
µPD29F064115-X
[ MEMO ]
Data Sheet M16062EJ2V0DS
29
µPD29F064115-X
[ MEMO ]
30
Data Sheet M16062EJ2V0DS
µPD29F064115-X
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M16062EJ2V0DS
31
µPD29F064115-X
Related Document
Document Name
PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information
Document Number
M15451E
• The information in this document is current as of September, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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