TI SN74BCT646DW

SN54BCT646, SN74BCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS037C – AUGUST 1989 – REVISED NOVEMBER 1993
•
•
•
•
•
description
SN54BCT646 . . . JT OR W PACKAGE
SN74BCT646 . . . DW OR NT PACKAGE
(TOP VIEW)
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
SN54BCT646 . . . FK PACKAGE
(TOP VIEW)
These devices consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal registers. Data on the
A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the ′BCT646.
Output-enable (OE) and direction-control (DIR)
inputs are provided to control the transceiver
functions. In the transceiver mode, data present at
the high-impedance port may be stored in either
register or in both.
DIR
SAB
CLKAB
NC
VCC
CLKBA
SBA
•
State-of-the-Art BiCMOS Design
Significantly Reduces ICCZ
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Bus Transceivers/ Registers
Independent Registers and Enables for
A and B Buses
Multiplexed Real-Time and Stored Data
Power-Up High-Impedance Mode
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK) and Flatpacks (W), and
Plastic and Ceramic 300-mil DIPs (JT, NT)
A1
A2
A3
NC
A4
A5
A6
4 3 2
1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
19
11
12 13 14 15 16 17 18
OE
B1
B2
NC
B3
B4
B5
A7
A8
GND
NC
B8
B7
B6
•
NC – No internal connection
The select-control (SAB and SBA) inputs can
multiplex stored and real-time (transparent mode)
data. The direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode
(OE high), A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
The SN54BCT646 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
SN74BCT646 is characterized for operation from 0°C to 70°C.
Copyright  1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–1
SN54BCT646, SN74BCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
21
OE
L
3
DIR
L
23
1
CLKAB CLKBA
X
X
22
SBA
L
2
SAB
X
BUS B
BUS A
BUS A
BUS B
SCBS037C – AUGUST 1989 – REVISED NOVEMBER 1993
21
OE
L
1
23
CLKAB CLKBA
X
↑
X
↑
↑
↑
2
SAB
X
X
X
22
SBA
X
X
X
STORAGE FROM
A, B, OR A AND B
21
OE
L
L
22
SBA
X
BUS B
3
DIR
L
H
1
CLKAB
X
L
23
CLKBA
L
X
2
SAB
X
H
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
Pin numbers shown are for the DW, JT, NT, and W packages.
2–2
2
SAB
L
BUS A
BUS B
BUS A
3
DIR
X
X
X
23
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
21
OE
X
X
H
1
CLKAB
X
3
DIR
H
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
22
SBA
H
X
SN54BCT646, SN74BCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS037C – AUGUST 1989 – REVISED NOVEMBER 1993
FUNCTION TABLE
INPUTS
DATA I/O
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1 THRU A8
X
X
↑
X
X
X
Input
B1 THRU B8
Unspecified†
OPERATION OR FUNCTION
X
X
X
↑
X
X
Unspecified†
Input
Store A, B unspecified†
Store B, A unspecified†
H
X
↑
↑
X
X
Input
Input
Store A and B data
H
X
H or L
H or L
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
L
H
H or L
X
H
X
Input
Output
Stored A data to B bus
† The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs.
logic symbol‡
21
OE
DIR
CLKBA
SBA
CLKAB
SAB
A1
3
23
22
1
2
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
≥1
4
1
5
6D
5
7
1
4D
5
A4
A5
A6
A7
A8
B1
1
≥1
2
7
19
A2
A3
20
6
18
7
17
8
16
9
15
10
14
11
13
B2
B3
B4
B5
B6
B7
B8
‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, NT, and W packages.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–3
SN54BCT646, SN74BCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS037C – AUGUST 1989 – REVISED NOVEMBER 1993
logic diagram (positive logic)
OE
DIR
CLKBA
SBA
CLKAB
SAB
21
3
23
22
1
2
One of Eight
Channels
1D
C1
A1
4
20
1D
C1
To Seven Other Channels
Pin numbers shown are for the DW, JT, NT, and W packages.
2–4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
B1
SN54BCT646, SN74BCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS037C – AUGUST 1989 – REVISED NOVEMBER 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range: Control inputs (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 5.5 V
Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC
Current into any output in the low state: SN54BCT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74BCT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Operating free-air temperature range: SN54BCT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
SN74BCT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
SN54BCT646
SN74BCT646
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IIK
Low-level input voltage
0.8
0.8
V
Input clamp current
–18
–18
mA
IOH
IOL
High-level output current
–12
–15
mA
Low-level output current
48
64
mA
TA
Operating free-air temperature
70
°C
High-level input voltage
2
– 55
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2
125
0
V
V
2–5
SN54BCT646, SN74BCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS037C – AUGUST 1989 – REVISED NOVEMBER 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VCC = 4.5 V,
VOH
II
IIH‡
IIL‡
IOS§
ICCL
A or B port
Control inputs
A or B port
Control inputs
A or B port
Control inputs
A or B port
ICCH
ICCZ
A or B port
Ci
Control inputs
A or B port
MIN
II = –18 mA
IOH = – 3 mA
VCC = 4.5 V
VOL
SN54BCT646
TYP†
MAX
TEST CONDITIONS
SN74BCT646
TYP†
MAX
MIN
–1.2
IOH = –12 mA
IOH = –15 mA
2.4
3.3
2
3.2
–1.2
2.4
0.38
VCC = 4
4.5
5V
VCC = 5
5.5
5V
V,
VI = 5
5.5
5V
VCC = 5
5.5
5V
V,
VI = 2
2.7
7V
VCC = 5
5.5
5V
V,
VI = 0
0.5
5V
VCC = 5.5 V,
VCC = 5.5 V,
VO = 0
VI = GND
VCC = 5.5 V,
VCC = 5.5 V,
VI = 4.5 V
VI = GND
VCC = 5 V,
VCC = 5 V,
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
3.1
0.55
0.42
– 100
0.55
1
1
1
1
70
70
20
20
– 0.7
– 0.7
– 0.7
– 0.7
– 225
42
V
3.3
V
2
IOL = 48 mA
IOL = 64 mA
UNIT
– 100
µA
mA
mA
67
mA
5.6
9
mA
10
16
mA
42
5.6
9
10
16
Cio
A or B port
12
† All typical values are at VCC = 5 V, TA = 25°C.
‡ For I/O ports, the parameters IIH and IIL include the off-state output current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
mA
– 225
67
6
V
6
pF
14
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°C
SN54BCT646
SN7BCTT646
MIN
MAX
MIN
MAX
MIN
MAX
83
0
83
0
83
UNIT
fclock
tw
Clock frequency
0
Pulse duration, CLK high or low
6
6
6
ns
tsu
th
Setup time, A or B before CLKAB↑ or CLKBA↑
6
7
6
ns
0.5
0.5
0.5
ns
2–6
Hold time, A or B after CLKAB↑ or CLKBA↑
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MHz
SN54BCT646, SN74BCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS037C – AUGUST 1989 – REVISED NOVEMBER 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Note 2)
PARAMETER
fmax
tPLH
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
TYP
SN54BCT646
MAX
83
MIN
MAX
83
SN74BCT646
MIN
83
MHz
3.6
7
9.4
3.6
12.4
3.6
11.2
3.9
7
9.2
3.9
11.5
3.9
10.6
3.1
6
8.1
3.1
11.1
3.1
9.5
3.7
6.8
8.9
3.7
12.1
3.7
10.5
4.5
8.8
11.2
4.5
15.2
4.5
13.8
3.3
6
8.1
3.3
9.8
3.3
9.1
3.9
7.7
10.2
3.9
13.3
3.9
12
4.7
8.3
10.8
4.7
13.7
4.7
12.9
4
7.9
10.7
4
14
4
13.2
4.6
8.8
11.8
4.6
15.4
4.6
14.4
4
7.2
9.4
4
12
4
10.9
3.4
7
9.3
3.4
11.6
3.4
10.5
2.8
7.8
10.7
2.8
14
2.8
13.1
3.8
8.9
11.9
3.8
15.6
3.8
14.6
3.8
8.4
10.7
3.8
13.2
3.8
DIR
A or B
tPLZ
3.2
7.3
9.9
3.2
12.6
3.2
† These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
12.6
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
CLKBA or CLKAB
A or B
A or B
B or A
SAB or SBA†
(with A or B high)
A or B
SAB or SBA†
(with A or B low)
A or B
OE
A or B
OE
A or B
DIR
A or B
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MAX
11.8
ns
ns
ns
ns
ns
ns
ns
ns
2–7
SN54BCT646, SN74BCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS037C – AUGUST 1989 – REVISED NOVEMBER 1993
2–8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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performed, except those mandated by government requirements.
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Copyright  1998, Texas Instruments Incorporated