TI 74AC11651

74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
•
•
•
•
•
•
•
•
DW OR NT PACKAGE
(TOP VIEW)
Independent Registers and Enables for A
and B Buses
Multiplexed Real-Time and Stored Data
Inverting Data Paths
Flow-Through Architecture Optimizes PCB
Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
OEAB
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
OEBA
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
CLKAB
SAB
B1
B2
B3
B4
VCC
VCC
B5
B6
B7
B8
CLKBA
SBA
description
These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and
OEBA) inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are
provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and
a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that
can be performed with the 74AC11651.
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when
all the other data sources to the two sets of bus lines are at high impedance, each set will remain at its last state.
The 74AC11651 is characterized for operation from – 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
1
14
OEAB OEBA
L
L
28
16
27
CLKAB CLKBA SAB
X
X
X
BUS B
BUS A
BUS A
BUS B
SCAS135 – MARCH 1990 – REVISED APRIL 1993
15
SBA
L
1
14
OEAB OEBA
H
H
14
OEBA
H
X
H
28
16
27
CLKAB CLKBA SAB
↑
X
↑
X
↑
↑
X
X
X
15
SBA
X
X
X
STORAGE FROM
A, B, OR A AND B
1
OEAB
H
15
SBA
X
BUS B
14
OEBA
L
28
CLKAB
16
CLKBA
27
SAB
15
SBA
H or L
H or L
H
H
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
2
27
SAB
L
BUS A
BUS A
1
OEAB
X
L
L
16
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
28
CLKAB
X
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
OEAB
OEBA
CLKAB
CLKBA
SAB
SBA
A1 THRU A8
B1 THRU B8
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
↑
↑
X
X
Input
H
↑
H or L
X
Input
H
H
↑
↑
X
X‡
Input
Unspecified†
Store A and B data
X
X
Input
Output
Store A in both registers
L
X
H or L
↑
X
Unspecified†
Input
Hold A, store B
L
L
↑
↑
X
X
X‡
Output
Input
Store B in both registers
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Output
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
Output
Stored A data to B bus and
stored B data to A bus
H
L
H or L
H or L
H
H
Output
Store A, hold B
† The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.
‡ When select control is low, clocks can occur simultaneously so long as allowances are made for propagation delays from A to B (B to A) plus
setup and hold times. When select control is high, clocks must be staggered in order to load both registers.
logic symbol§
14
OEBA
OEAB
CLKBA
SBA
CLKAB
SAB
A1
1
16
15
28
27
EN1 [BA]
EN2 [AB]
C4
G5
C6
G7
2
1
≥1
7
1
A3
A4
A5
A6
A7
A8
4D
26
B1
5 1
6D
A2
5
7
≥1
2
3
25
4
24
5
23
10
20
11
19
12
18
13
17
B2
B3
B4
B5
B6
B7
B8
§ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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• DALLAS, TEXAS 75265
3
74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
logic diagram (positive logic)
OEBA
OEAB
14
1
CLKBA 16
15
SBA
CLKAB 28
SAB
27
1 of 8
Channels
A1
1D
C1
26
2
B1
1D
C1
To 7 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
4
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• DALLAS, TEXAS 75265
74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
recommended operating conditions
VCC
Supply voltage
VIH
High-level input voltage
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
MIN
NOM
MAX
3
5
5.5
V
3.85
VCC = 3 V
VCC = 4.5 V
0.9
Low-level input voltage
VI
VO
Input voltage
0
Output voltage
0
IOH
High-level output current
1.35
VCC = 5.5 V
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
V
2.1
3.15
VIL
IOL
UNIT
V
1.65
VCC
VCC
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
V
V
–4
– 24
mA
– 24
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
12
24
mA
24
0
10
ns/V
– 40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = – 50 µA
VOH
2.9
2.9
4.4
4.4
5.4
5.4
2.58
2.48
4.5 V
3.94
3.8
IOH = – 24 mA
A
5.5 V
4.94
IOH = – 75 mA†
5.5 V
IOL = 12 mA
IOL = 24 mA
ICC
Ci
3V
4.5 V
3V
IOL = 50 µA
II
IOZ‡
MIN
5.5 V
IOH = – 4 mA
VOL
TA = 25°C
MIN
TYP
MAX
MAX
UNIT
V
4.8
3.85
3V
0.1
0.1
4.5 V
0.1
0.1
5.5 V
0.1
0.1
3V
0.36
0.44
4.5 V
0.36
0.44
5.5 V
0.36
0.44
V
IOL = 75 mA†
5.5 V
5.5 V
± 0.1
±1
µA
A or B ports
VI = VCC or GND
VO = VCC or GND
5.5 V
± 0.5
±5
µA
VI = VCC or GND,
VI = VCC or GND
8
80
µA
Control inputs
Control inputs
IO = 0
1.65
5.5 V
5V
4.5
Cio
A or B ports
VO = VCC or GND
5V
10
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
pF
pF
5
74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 2)
TA = 25°C
MIN
MAX
0
MAX
UNIT
0
45
MHz
fclock
tw
Clock frequency
Pulse duration, CLK high or low
10
10
ns
tsu
th
Setup time, A or B before CLKAB↑ or CLKBA↑
6.5
6.5
ns
0
0
ns
Hold time, A or B after CLKAB↑ or CLKBA↑
45
MIN
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 2)
TA = 25°C
MIN
MAX
0
90
MIN
MAX
UNIT
0
90
MHz
fclock
tw
Clock frequency
Pulse duration, CLK high or low
5.5
5.5
ns
tsu
th
Setup time, A or B before CLKAB↑ or CLKBA↑
4.5
4.5
ns
Hold time, A or B after CLKAB↑ or CLKBA↑
0.5
0.5
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER
fmax
tPLH
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
45
MIN
MAX
45
MHz
3.2
7.7
12.1
3.2
14
4.3
9.5
14.6
4.3
16.1
4.6
9.8
15
4.6
17.2
5.4
11.5
17.5
5.4
19.2
3.8
8.6
13.3
3.8
15.3
4.8
10.2
15.5
4.8
17.1
3.4
8.1
12.7
3.4
14.6
5
10.3
15.5
5
17.1
4.6
9.8
14.9
4.6
16.9
5.3
12.1
18.9
5.3
21.3
4.4
6.6
8.8
4.4
9.2
3.8
5.8
7.8
3.8
8.1
4.9
10.2
15.5
4.9
17.6
5.5
12.2
18.8
5.5
21.2
4.4
6.7
8.9
4.4
OEAB
B
tPLZ
3.5
5.7
7.8
3.5
† These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
9.3
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
6
A or B
B or A
CLKBA or CLKAB
A or B
SBA or SAB†
(A or B high)
A or B
SBA or SAB†
(A or B low)
A or B
OEBA
A
OEBA
A
OEAB
B
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
8
ns
ns
ns
ns
ns
ns
ns
ns
74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
90
A or B
B or A
CLKBA or CLKAB
A or B
SBA or SAB†
(A or B high)
A or B
SBA or SAB†
(A or B low)
A or B
OEBA
A
OEBA
A
OEAB
B
OEAB
B
MIN
MAX
90
UNIT
MHz
2.6
5.3
8
2.6
9.1
3.5
6.5
9.4
3.5
10.5
3.8
6.8
10
3.8
11.4
4.7
8.1
11.5
4.7
12.8
3.2
6
8.8
3.2
10.1
3.9
7
10.1
3.9
11.2
2.9
5.7
8.5
2.9
9.5
4.1
7.2
10.3
4.1
11.4
3.9
6.9
9.8
3.9
11.1
4.2
7.6
11
4.2
12.5
4.1
5.9
7.6
4.1
8
3.5
5.2
6.8
3.5
7.1
4.2
5.9
10.4
4.2
11.8
4.5
8
11.4
4.5
12.9
4.2
6
7.8
4.2
8.2
3.3
5.1
6.9
3.3
7.2
ns
ns
ns
ns
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
Power dissipation capacitance per transceiver
TEST CONDITIONS
Outputs enabled
Outputs disabled
POST OFFICE BOX 655303
pF
CL = 50 pF,
• DALLAS, TEXAS 75265
f = 1 MHz
TYP
64
14
UNIT
pF
7
74AC11651
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS135 – MARCH 1990 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
GND
CL = 50 pF
(see Note A)
S1
Open
2 × VCC
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
500 Ω
tw
LOAD CIRCUIT FOR OUTPUTS
VCC
Input
50%
50%
0V
VCC
50%
Timing Input
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tsu
th
VCC
Data Input
50%
50%
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
(see Note B)
50%
0V
tPLH
Output
(see Note D)
VOH
50%VCC
VOL
Output
Waveform 2
S1 at GND
(see Note C)
50%
0V
tPLZ
≈VCC
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
tPHL
50%VCC
50%
tPZL
VCC
50%
VCC
Output
Control
(low-level
enabling)
50%VCC
tPZH
20%VCC
VOL
tPHZ
VOH
50%VCC
80%VCC
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
For testing pulse duration: tr = tf = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
8
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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performed, except those mandated by government requirements.
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Copyright  1998, Texas Instruments Incorporated