74AC11652 OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS SCAS088A - DECEMBER 1989 - REVISED APRIL 1996 D D D D D D D DW PACKAGE (TOP VIEW) Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Inverting Data Paths Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C OEAB A1 A2 A3 A4 GND GND GND GND A5 A6 A7 A8 OEBA description 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 CLKAB SAB B1 B2 B3 B4 VCC VCC B5 B6 B7 B8 CLKBA SBA The 74AC11652 consists of bus transceiver 14 15 circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the 74AC11652. Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set remains at its last state. The 74AC11652 is characterized for operation from – 40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 74AC11652 OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS 1 14 OEAB OEBA L L 28 16 27 CLKAB CLKBA SAB X X X BUS B BUS A BUS A BUS B SCAS088A - DECEMBER 1989 - REVISED APRIL 1996 15 SBA L 1 14 OEAB OEBA H H 14 OEBA H X H 28 16 27 CLKAB CLKBA SAB ↑ X ↑ X ↑ ↑ X X X 15 SBA X X X STORAGE FROM A, B, OR A AND B 1 OEAB H 15 SBA X BUS B 14 OEBA L 28 CLKAB 16 CLKBA 27 SAB 15 SBA L L H H TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions 2 27 SAB L BUS A BUS A 1 OEAB X L L 16 CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A 28 CLKAB X POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 74AC11652 OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS SCAS088A - DECEMBER 1989 - REVISED APRIL 1996 FUNCTION TABLE DATA I/O† INPUTS OEAB OEBA L H L L H ↑ X H ↑ L H H ↑ L X L L L ↑ ↑ X L L X X X L L X L X H H X X L H H L X H H L CLKAB L CLKBA OPERATION OR FUNCTION SAB SBA A1 THRU A8 B1 THRU B8 L X X Input Input Isolation ↑ X X Input Input Store A and B data X Input Unspecified‡ Store A, hold B ↑ X X‡ X Store A in both registers X Input Unspecified‡ Output ↑ Input Hold A, store B Output Input Store B in both registers L Output Input Real-time B data to A bus H Output Input Stored B data to A bus X Input Output Real-time A data to B bus X Input Output Stored A data to B bus Output Stored A data to B bus and stored B data to A bus L H X X‡ H Output † The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs. ‡ Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered to load both registers. logic symbol§ 14 OEBA OEAB CLKBA SBA CLKAB SAB A1 1 16 15 28 27 EN1 [BA] EN2 [AB] C4 G5 C6 G7 2 1 ≥1 7 1 A3 A4 A5 A6 A7 A8 4D 26 B1 5 1 6D A2 5 7 ≥1 2 3 25 4 24 5 23 10 20 11 19 12 18 13 17 B2 B3 B4 B5 B6 B7 B8 § This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 74AC11652 OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS SCAS088A - DECEMBER 1989 - REVISED APRIL 1996 logic diagram (positive logic) OEBA OEAB CLKBA SBA CLKAB SAB 14 1 16 15 28 27 One of Eight Channels 1D C1 A1 2 26 B1 1D C1 To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 74AC11652 OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS SCAS088A - DECEMBER 1989 - REVISED APRIL 1996 recommended operating conditions VCC Supply voltage VIH High-level input voltage VCC = 3 V VCC = 4.5 V MIN NOM MAX 3 5 5.5 0.9 Low-level input voltage VI VO Input voltage 0 Output voltage 0 IOH High-level output current ∆t /∆v Input transition rise or fall rate TA Operating free-air temperature V 3.85 VIL VCC = 4.5 V VCC = 5.5 V 1.35 V 1.65 VCC VCC VCC = 3 V VCC = 4.5 V Low-level output current V 2.1 3.15 VCC = 5.5 V VCC = 3 V IOL UNIT V V –4 – 24 VCC = 5.5 V VCC = 3 V – 24 VCC = 4.5 V VCC = 5.5 V 24 mA 12 mA 24 Control pins 0 5 Data 0 10 – 40 85 ns/ V °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = – 50 µA VOH IOH = – 4 mA VOL ICC Ci A or B ports TA = 25°C TYP MAX MIN 3V 2.9 2.9 4.5 V 4.4 4.4 5.5 V 5.4 5.4 3V 2.58 2.48 3.8 MAX 3.94 5.5 V 4.94 IOH = – 75 mA† 5.5 V 3V 0.1 0.1 IOL = 50 µA 4.5 V 0.1 0.1 IOL = 75 mA† VI = VCC or GND VO = VCC or GND VI = VCC or GND, 4.8 3.85 5.5 V 0.1 0.1 3V 0.36 0.44 4.5 V 0.36 0.44 5.5 V 0.36 0.44 5.5 V IO = 0 V 1.65 5.5 V ± 0.1 ±1 µA 5.5 V ± 0.5 ±5 µA 5.5 V 8 80 µA Control inputs VI = VCC or GND 5V 4.5 Cio A or B ports VO = VCC or GND 5V 12 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ For I/O ports, the parameter IOZ includes the input leakage current. POST OFFICE BOX 655303 UNIT V 4.5 V IOL = 12 mA Control inputs MIN IOH = – 24 mA A IOL = 24 mA II IOZ‡ VCC • DALLAS, TEXAS 75265 pF pF 5 74AC11652 OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS SCAS088A - DECEMBER 1989 - REVISED APRIL 1996 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2) TA = 25°C MIN MAX fclock tw Clock frequency tsu th 0 Pulse duration, CLK high or low 65 MIN MAX UNIT 0 65 MHz 7.7 7.7 ns Setup time, A or B before CLKAB↑ or CLKBA↑ 6 6 ns Hold time, A or B after CLKAB↑ or CLKBA↑ 1 1 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2) TA = 25°C MIN MAX 0 MAX UNIT 0 105 MHz fclock tw Clock frequency Pulse duration, CLK high or low 4.8 4.8 ns tsu th Setup time, A or B before CLKAB↑ or CLKBA↑ 4.5 4.5 ns 1 1 ns Hold time, A or B after CLKAB↑ or CLKBA↑ 105 MIN switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ FROM (INPUT) TO (OUTPUT) MIN TA = 25°C TYP MAX 65 A or B B or A CLKBA or CLKAB A or B SBA or SAB† (A or B high) A or B SBA or SAB† (A or B low) A or B OEBA A OEBA A OEAB B POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX 65 UNIT MHz 2.9 8.5 11.1 2.9 12.9 3.9 10.3 12.9 3.9 14.2 4.3 11.2 14.3 4.3 16.2 5.3 13.1 16.2 5.3 17.8 3.4 9.4 12 3.4 13.7 4.7 11.5 14.3 4.7 15.6 3.9 10.5 13.3 3.9 14.9 4.8 12.1 16.3 4.8 17.7 4.3 11.1 14.5 4.3 16.5 5.2 14.4 19.8 5.2 22 3.7 6.4 8.1 3.7 8.5 3.5 6 7.8 3.5 8.2 4.7 11.6 15 4.7 16.9 5.6 14.8 19.9 5.6 21.9 4 8.6 3.5 8 4 6.6 8.2 OEAB B tPLZ 3.5 6.1 7.7 † These parameters are measured with the internal output state of the storage register opposite that of the bus input. 6 MIN ns ns ns ns ns ns ns ns 74AC11652 OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS SCAS088A - DECEMBER 1989 - REVISED APRIL 1996 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) MIN TA = 25°C TYP MAX 105 A or B B or A CLKBA or CLKAB A or B SBA or SAB (A or B high) A or B SBA or SAB (A or B low) A or B OEBA A OEBA A OEAB B OEAB B MIN MAX 105 UNIT MHz 2.4 5.2 7.6 2.4 8.6 3.1 6 8.7 3.1 9.6 3.6 6.7 9.5 3.6 10.7 4.4 7.8 10.8 4.4 12 2.9 5.6 8.1 2.9 9.1 3.8 6.9 9.6 3.8 10.7 3.3 6.2 8.8 3.3 9.9 4 7.1 9.9 4 10.9 3.3 6.6 9.6 3.3 10.9 4.2 7.4 10.9 4.2 12.2 3.6 5.5 7.2 3.6 7.6 3.3 5 6.7 3.3 7.1 4.1 7.2 10.1 4.1 11.3 4.6 7.9 11.1 4.6 12.3 3.9 5.6 7.3 3.9 7.6 3.4 5.2 6.8 3.4 7.2 ns ns ns ns ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d Power dissipation capacitance per transceiver TEST CONDITIONS Outputs enabled Outputs disabled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pF CL = 50 pF, f = 1 MHz TYP 60 14 UNIT pF 7 74AC11652 OCTAL BUS TRANSCEIVER AND REGISTERS WITH 3-STATE OUTPUTS SCAS088A - DECEMBER 1989 - REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 500 Ω CL = 50 pF (see Note A) LOAD CIRCUIT Timing Input (see Note B) 0V tw 50% 50% th tsu VCC Input VCC 50% VCC 50% 50% Data Input 0V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS VCC Input 50% 50% 0V tPHL tPLH In-Phase Output 50% VCC VOH 50% VCC VOL 50% VCC VOH 50% VCC VOL VCC Output Waveform 2 S1 at GND (see Note B) 50% 50% 0V tPZL [ VCC tPLZ Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH tPHL Out-of-Phase Output Output Control (low-level enabling) 50% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS 20% VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 2. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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