M66288FP REJ03F0156-0310 Rev. 03.10 Apr.4.2008 262144-word x 8-bit x 3-FIFO MEMORY Description The M66288FP is a high-speed field memory with three FIFO (First In First Out) memories of 262144-word x 8-bit configuration (2M-bit), which uses high-performance silicon gate CMOS process technology. One of three FIFO memories consists of two FIFO memories of 262144-word x 4-bit (1M-bit). Eight types of operation can be performed by mode settings. Features z Memory configuration Total memory capacity is 6M-bit (static memory). Eight types of memory configurations can be selected. 12.5 ns (Min.) fmax 80MHz 9.0 ns (Max.) 2.0 ns (Min.) Internal = 1.8 V ± 0.18 V, I/O = 3.3 V ± 0.3 V z High - speed cycle z High - speed access z Output hold z Supply voltage z Variable length delay bit z Eight modes can be selected z Write and Read function can be operated completely independently and asynchronously z Output type 3 state output z Package 100pin 14x14mm body LQFP (PLQP0100KB-A, 100P6Q-A) Application W-CDMA base station, Digital PPC, Digital television, VTR and so on. GND RCKA RRESA REA VccIO GND RCKB RRESB REB MODE1 MODE2 MODE3 RCKC RRESC REC VccIO GND QB7 QB6 QB5 QB4 QB3 QB2 QB1 QB0 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Pin Configuration (Top view) VccIO 76 50 GND GND 77 49 Vcc18 Vcc18 78 48 GND QA0 79 47 VccIO QA1 80 46 QC7 QA2 81 45 QC6 QA3 82 44 QC5 QA4 83 43 QC4 QA5 84 42 QC3 QA6 85 41 QC2 QA7 86 40 QC1 GND 87 39 QC0 VccIO 88 38 GND DA0 89 37 VccIO DA1 90 36 DC7 DA2 91 35 DC6 DA3 92 34 DC5 DA4 93 33 DC4 DA5 94 32 DC3 DA6 95 31 DC2 DA7 96 30 DC1 GND 97 29 DC0 Vcc18 98 28 GND TEST1 99 27 Vcc18 TEST2 100 26 GND 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 WRESB WEB VccIO GND WCKC WRESC WEC Vcc18 GND DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VccIO 5 VccIO 7 4 WEA GND 3 WRESA WCKB 2 WCKA 6 1 TEST3 M66288FP REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 1 of 23 M66288FP Mode Descriptions Drawing 1K-word = 1024-word 256K-word 8-bit bus I/F MODE 2 MODE 1 DA<7:0> 8 256K-w x 8-bit FIFO WCKA WRESA WEA DB<7:0> 8 8 8 256K-w x 8-bit FIFO WCKB WRESB WEB RCKA DA<7:0> WCKA RRESA WRESA REA WEA QA<7:0> 8 8 256K-w x 8-bit FIFO QB<7:0> 256K-w x 8-bit FIFO 8 RCKB RRESB REB 8 12-bit bus I/F MODE 3 QA<7:0> RCKA DA<7:0> RRESA WRESA REA WEA 8 256K-w x 8-bit FIFO WCKA 8 QB<7:0> 8 256K-w x 8-bit FIFO MODE 4 QA<7:0> RCKA RRESA REA 8 DA<11:0> DC<7:0> WCKC WRESC WEC 8 WRESA WEA 256K-w x 8-bit FIFO QC<7:0> 256K-w x 8-bit FIFO 8 RCKC RRESC REC The three pieces of 256K-word x 8-bit FIFO can be operated completely independently. 8 DC<7:0> QC<7:0> 3-system individual input 1-system input 3-system individual output The simultaneous output of the 1, 2, 3 line delay data. 768K-word MODE 6 DA<7:0> WCKA WRESA WEA 8 8 768K-w x 8-bit FIFO 256K-w x 8-bit FIFO WCKC WRESC WEC The three pieces of 256K-word x 8-bit FIFO are cascade-connected. (Note 1) 8 MODE 5 QA<11:0> DA<11:0> RCKA WCKA WRESA RRESA REA QC<7:0> RCKC WEA WRESB WEB 12 12 256K-w x 12-bit FIFO QB<11:0> 12 RCKB RRESB DA<7:0> WCKA RRESA WRESA REA WEA DC<7:0> WCKC WRESC WEC A piece of 768K-word x 8-bit FIFO can be operated completely independently. 1-system input 1-system output 8 8 8 256K-w x 8-bit FIFO RCKA RRESA 256K-w 12 x 12-bit FIFO QB<11:0> REA REC 512K-w x 8-bit FIFO 8 QA<11:0> REB The two pieces of 256K-word x 12-bit FIFO can be operated completely independently. (Note 2) The two pieces of 256K-word x 12-bit FIFO are cascade-connected (Note 1, Note 2) 2-system individual input. 1-system input 2-system individual output. The simultaneous output of the 1, 2 line delay data. 512K-word & 256K-word 8-bit bus I/F MODE 7 RCKA 12 256K-w x 12-bit FIFO RRESC The two pieces of 256K-word x 8-bit FIFO are cascade-connected and, a piece of 256K-word x 8-bit FIFO can be operated completely independently. (Note 1) (1) 1-system input (2) 1-system input (1) The simultaneous output of the 1, 2 line delay data. (2) 1-system output QA<7:0> 12 QB<7:0> DB<11:0> 8 256K-w x 12-bit FIFO WCKA WCKB 8 12 12 512K-word 12-bit bus I/F MODE 8 QA<7:0> DA<11:0> RCKA WCKA RRESA WRESA REA WEA 12 12 512K-w x 12-bit FIFO QA<11:0> RCKA RRESA REA QC<7:0> RCKC RRESC REC A piece of 512K-word x 8-bit FIFO and a piece of 256K-word x 8-bit FIFO can be operated completely independently. 2-system individual input 2-system individual output A piece of 512K-word x 12-bit FIFO can be operated completely independently. (Note 2) 1-system input 1-system output Note1: Write and read operation of FIFO after the 2nd line is controlled by the read system pin of the 1st line FIFO. Maximum number of words on this mode is 256K-word. Line delay is achieved without outer connection. Note2: Please refer to pin assignment tables in “Operation Description” of Mode 4, Mode 5, and Mode 8 for assignment of external pins, Dx<11:0> and Qx<11:0> when used in 12-bit bus interface. REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 2 of 23 M66288FP Block Diagram Data input DA<7:0> DB<7:0> DC<7:0> INPUT BUFFER Mode setting Mode setting input input MODE<3:1> MODE<3:1> MODE CONTROL CIRCUIT Read control inputs for A-system WCKC WRESC WEC Test setting input Test setting input TEST<3:1> TEST<3:1> 256K-word xx4-BIT 4bit 256K-WORD 256K-word xx4-BIT 4bit 256K-WORD 256K-word xx8-BIT 8bit 256K-WORD READ CONTROL CIRCUIT Write control inputs for C-system 256K-WORD 256K-word xx8-BIT 8bit READ ADDRESS COUNTER Write control inputs for B-system WCKB WRESB WEB MEMORY ARRAY WRITE ADDRESS COUNTER WCKA WRESA WEA WRITE CONTROL CIRCUIT Write control inputs for A-system RCKA RRESA REA Read control inputs for B-system RCKB RRESB REB Read control inputs for C-system RCKC RRESC REC MODE CONTROL CIRCUIT OUTPUT BUFFER VCC 18 Vcc18 VccIO VCC IO GND GND Data output Data output QA<7:0> QA<7:0> REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 3 of 23 QB<7:0> QB<7:0> QC<7:0> QC<7:0> M66288FP Pin Function Descriptions Pin name WCK x Write clock input Input / Output Input WE x Write enable input Input 3 They are write enable control inputs. When they are "L", a write enable status is provided. WRES x Write reset input Input 3 RCK x Read clock input Input 3 They are write reset inputs to initialize a write address counter of internal FIFO. When they are "L", a write reset status is provided. They are read clock inputs. RE x Read enable input Input 3 They are read enable control inputs. When they are "L", a read enable status is provided. RRES x Read reset input Input 3 Dx <7:0> Data input Input 24 They are read reset inputs to initialize a read address counter of internal FIFO. When they are "L", a read reset status is provided. They are 8-bit input data bus. Qx <7:0> Data output Output 24 They are 8-bit output data bus. MODE<3:1> Mode setting input Input 3 They are operation mode setting inputs. For setting, refer to Mode setting table of Page5. TEST<3:1> Test setting input Input 3 VccIO Power supply pin for I/O Power supply pin for internal circuit Ground pin - 9 They are test setting inputs. Setting of TEST1 depends on the rising time of the 1.8 V system power supply. For further details, refer to page 12. TEST2 and TEST3 should be fixed at "L". This is a 3.3 V power supply pin for I/O. - 5 This is a 1.8 V power supply pin for internal circuit. - 14 This is a ground pin. Vcc18 GND Name Number of pins 3 Note: X of the pin name shows A, B and C. A = A-system, B = B-system, C = C-system. REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 4 of 23 Function They are write clock inputs. M66288FP Mode Setting MODE<3:1> should be set to “L” or “H” as shown below to select the 8 operation modes. MODE 3 MODE 2 MODE 1 Operation mode L L L MODE 1 L L H MODE 2 L H L MODE 3 L H H MODE 4 H L L MODE 5 H L H MODE 6 H H L MODE 7 H H H MODE 8 Mode1 Operation Description <Mode 1> DA<7:0> WCKA WRESA WEA 8 8 256K-w x 8-bit FIFO(A) QA<7:0> RCKA RRESA REA In mode 1, three pieces of 256K-word x 8-bit FIFO can be controlled completely independently. Taking FIFO (A) as an example, the operation of FIFO memory is described below. The operation of FIFO (B) and FIFO (C) are the same as that of FIFO (A). DB<7:0> WCKB WRESB WEB 8 8 256K-w x 8-bit FIFO(B) QB<7:0> RCKB RRESB REB When write enable input WEA is "L", the contents of data input DA<7:0> are written into FIFO (A) in synchronization with the rising of write clock input WCKA. At this time, the write address counter of FIFO (A) is incremented. DC<7:0> WCKC WRESC WEC 8 8 256K-w x 8-bit FIFO(C) When WEA is "H", this IC disable to write data into FIFO (A) and the write address QC<7:0> RCKC RRESC REC counter of FIFO (A) is not incremented. When write reset input WRESA is "L", the write address counter of FIFO (A) is initialized. When read enable input REA is "L", the contents of FIFO (A) are outputted to data output QA<7:0> in synchronization with the rising of read clock input RCKA. At this time, the read address counter of FIFO (A) is incremented. When REA is "H", this IC disable to read data from FIFO (A) and the read address counter of FIFO (A) is not incremented. Also QA<7:0> become high impedance state. When read reset input RRESA is "L", the read address counter of FIFO (A) is initialized. REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 5 of 23 M66288FP Mode2 Operation Description <Mode 2> In mode 2, three pieces of 256K-word x 8-bit FIFO are cascade-connected and it is possible to generate delay data for 3-lines without external wiring. When write enable input WEA is "L", the contents of data input DA<7:0> are written into FIFO (A) in synchronization with the rising of write clock input WCKA. At this time, the write address counter of FIFO (A) is incremented. When WEA is "H", this IC disable to write data into FIFO (A) and the write address counter of FIFO (A) is not incremented. When write reset input WRESA is "L", the write address counter of FIFO (A) is initialized. When read enable input REA is "L", the contents of FIFO (A), FIFO (B) and FIFO (C) are outputted to each QA<7:0>, QB<7:0>, QC<7:0> in synchronization with the rising of read clock input RCKA. At this time, the read address counters of all FIFOs are incremented. Also the data of the upper FIFO is written into the lower FIFO in synchronization with the rising of RCKA. At this time, the write address counters of FIFO (B) and FIFO (C) are incremented simultaneously. When REA is "H", this IC disable to read data from FIFO (A), FIFO (B) and FIFO (C) and the read address counter of each FIFO is not incremented. All data outputs become high impedance state. And this IC also disable to write data into FIFO (B) and FIFO (C) and the write address counter of FIFO (B) and FIFO (C) is not incremented. When read reset input RRESA is "L", the read address counter of FIFO (A) and the write/read address counters of FIFO (B) and FIFO (C) are initialized. In mode 2, only all pins for the A-system, QB<7:0> and QC<7:0> are used. Therefore, the write/read control pins for the B/C-system, DB<7:0> and DC<7:0> should be fixed at "L" or "H". Note: Write and read operation of FIFO (B) and FIFO (C) after the 2nd line is controlled by the read system pin of the 1st line FIFO (A). Maximum number of words on this mode is 256K-word. REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 6 of 23 M66288FP Mode3 Operation Description <Mode 3> DA<7:0> WCKA WRESA WEA 8 8 256K-w x 8-bit FIFO(A) QA<7:0> RCKA RRESA REA In mode 3, two pieces of 256K-word x 8-bit FIFO are cascade-connected and the other FIFO is configured completely independently. This makes it possible to generate delay data for 2-lines without external wiring and to control the other independent one FIFO memory. 8 8 256K-w x 8-bit FIFO(B) QB<7:0> When write enable input WEA is "L", the contents of data input DA<7:0> are written into FIFO (A) in synchronization with the rising of write clock input WCKA. At this time, the write address counter of FIFO (A) is incremented. When WEA is "H", this IC disable to write data into FIFO (A) and the write address counter of FIFO (A) is not incremented. DC<7:0> WCKC WRESC WEC 8 8 256K-w x 8-bit FIFO(C) QC<7:0> RCKC RRESC REC When write reset input WRESA is "L", the write address counter of FIFO (A) is initialized. When read enable input REA is "L", the contents of FIFO (A) and FIFO (B) are outputted to each QA<7:0> and QB<7:0> in synchronization with the rising of read clock input RCKA. At this time, the read address counters of FIFO (A) and FIFO (B) are incremented. Also the data of FIFO (A) is written into FIFO (B) in synchronization with the rising of RCKA. At this time, the write address counter of FIFO (B) is incremented simultaneously. When REA is "H", this IC disable to read data from FIFO (A) and FIFO (B) and the read address counter of each FIFO is not incremented. QA<7:0> and QB<7:0> become high impedance state. And this IC also disable to write data into FIFO (B) and the write address counter of FIFO (B) is not incremented. When read reset input RRESA is "L", the read address counter of FIFO (A) and the write/read address counter of FIFO (B) are initialized. The operation of FIFO (C) is the same as that of mode 1. In mode 3, only all pins for the A/C-system and QB<7:0> are used. Therefore the write/read control pins for the B-system and DB<7:0> should be fixed at "L" or "H". Note: Write and read operation of FIFO (B) at the 2nd line is controlled by the read system pin of the 1st line FIFO (A). Maximum number of words on this mode is 256K-word. REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 7 of 23 M66288FP Mode4 Operation Description <Mode 4> DA<7:0> DB<3:0> 12 12 256K-w x 12-bit FIFO(A) WCKA WRESA WEA QA<7:0> QB<3:0> RCKA RRESA REA In mode 4, two pieces of 256K-word x 12-bit FIFO can be controlled completely independently. Taking FIFO (A) as an example, the operation of FIFO memory is described below. The operation of FIFO (B) is the same as that of FIFO (A). When write enable input WEA is "L", the contents of data input DA<7:0> and DB<3:0> are written into FIFO (A) in synchronization with the rising of write clock DC<7:0> DB<7:4> WCKB WRESB WEB 12 12 256K-w x 12-bit FIFO(B) QC<7:0> QB<7:4> input WCKA. At this time, the write address counter of FIFO (A) is incremented. RCKB RRESB REB counter of FIFO (A) is not incremented. When WEA is "H", this IC disable to write data into FIFO(A) and the write address When write reset input WRESA is "L", the write address counter of FIFO (A) is initialized. When read enable input REA is "L", the contents of FIFO (A) are outputted to data output QA<7:0> and QB<3:0> in synchronization with the rising of read clock input RCKA. At this time, the read address counter of FIFO (A) is incremented. When REA is "H", this IC disable to read data from FIFO (A) and the read address counter of FIFO (A) is not incremented. Also QA<7:0> and QB<3:0> become high impedance state. When read reset input RRESA is "L", the read address counter of FIFO (A) is initialized. Also, set the 12-bit I/O buses of FIFO (A) and FIFO (B) as shown in the table below. In mode 4, only all pins for the A/B-system, DC<7:0> and QC<7:0> are used. Therefore the write/read control pins for the C-system should be fixed at "L" or "H". External pin Data input name bus of FIFO (A) DA<7> 11th-bit th DA<6> 10 -bit th DA<5> 9 -bit DA<4> 8th-bit DA<3> 7th-bit DA<2> 6th-bit DA<1> 5th-bit DA<0> 4th-bit DB<3> 3rd-bit DB<2> 2nd-bit DB<1> 1st-bit DB<0> 0th-bit External pin Data output name bus of FIFO (A) QA<7> 11th-bit th QA<6> 10 -bit th QA<5> 9 -bit QA<4> 8th-bit QA<3> 7th-bit QA<2> 6th-bit QA<1> 5th-bit QA<0> 4th-bit QB<3> 3rd-bit QB<2> 2nd-bit QB<1> 1st-bit QB<0> 0th-bit REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 8 of 23 External pin Data input name bus of FIFO (B) DC<7> 11th-bit th DC<6> 10 -bit th DC<5> 9 -bit DC<4> 8th-bit DC<3> 7th-bit DC<2> 6th-bit DC<1> 5th-bit DC<0> 4th-bit DB<7> 3rd-bit DB<6> 2nd-bit DB<5> 1st-bit DB<4> 0th-bit External pin Data output Name bus of FIFO (B) QC<7> 11th-bit th QC<6> 10 -bit th QC<5> 9 -bit QC<4> 8th-bit QC<3> 7th-bit QC<2> 6th-bit QC<1> 5th-bit QC<0> 4th-bit QB<7> 3rd-bit QB<6> 2nd-bit QB<5> 1st-bit QB<4> 0th-bit M66288FP Mode5 Operation Description DA<7:0> DB<3:0> 12 12 256K-w x 12-bit FIFO(A) WCKA WRESA WEA 12 QA<7:0> QB<3:0> RCKA RRESA REA 12 256K-w x 12-bit FIFO(B) QC<7:0> QB<7:4> <Mode 5> In mode 5, two pieces of 256K-word x 12-bit FIFO are cascade-connected and it is possible to generate delay data for 2-lines without external wiring. When write enable input WEA is "L", the contents of data input DA<7:0> and DB<3:0> are written into FIFO (A) in synchronization with the rising of write clock input WCKA. At this time, the write address counter of FIFO (A) is incremented. When WEA is "H", this IC disable to write data into FIFO (A) and the write address counter of FIFO (A) is not incremented. When write reset input WRESA is "L", the write address counter of FIFO (A) is initialized. When read enable input REA is "L", the contents of FIFO (A) and FIFO (B) are outputted to each QA<7:0>, QB<3:0> and QC<7:0>,QB<7:4> in synchronization with the rising of read clock input RCKA. At this time, the read address counters of FIFO (A) and FIFO (B) are incremented. Also the data of FIFO (A) is written into FIFO (B) in synchronization with the rising of RCKA. At this time, the write address counter of FIFO (B) is incremented simultaneously. When REA is "H", this IC disable to read data from FIFO (A) and FIFO (B) and the read address counter of each FIFO is not incremented. Also all data outputs become high impedance state. And this IC also disable to write data into FIFO (B) and the write address counter of FIFO (B) is not incremented. When read reset input RRESA is "L", the read address counter of FIFO (A) and the write /read address counter of FIFO (B) are initialized. Also, set the 12-bit I/O buses of FIFO (A) and FIFO (B) as shown in the table below. In mode 5, only all pins for the A-system, DB<3:0>, QB<7:0> and QC<7:0> are used. Therefore the write/read control pins for the B/C-system, DB<7:4> and DC<7:0> should be fixed at "L" or "H". External pin Data input Name bus of FIFO (A) DA<7> 11th-bit DA<6> 10th-bit DA<5> 9th-bit DA<4> 8th-bit DA<3> 7th-bit DA<2> 6th-bit DA<1> 5th-bit DA<0> 4th-bit DB<3> 3rd-bit DB<2> 2nd-bit DB<1> 1st-bit DB<0> 0th-bit External pin Data output name bus of FIFO (A) QA<7> 11th-bit QA<6> 10th-bit QA<5> 9th-bit QA<4> 8th-bit QA<3> 7th-bit QA<2> 6th-bit QA<1> 5th-bit QA<0> 4th-bit QB<3> 3rd-bit QB<2> 2nd-bit QB<1> 1st-bit QB<0> 0th-bit External pin Data output Name bus of FIFO (B) QC<7> 11th-bit QC<6> 10th-bit QC<5> 9th-bit QC<4> 8th-bit QC<3> 7th-bit QC<2> 6th-bit QC<1> 5th-bit QC<0> 4th-bit QB<7> 3rd-bit QB<6> 2nd-bit QB<5> 1st-bit QB<4> 0th-bit Note: Write and read operation of FIFO(B) at the 2nd line is controlled by the read system pin of the 1st line FIFO(A). Maximum number of words on this mode is 256K-word. REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 9 of 23 M66288FP Mode6 Operation Description <Mode 6> In mode 6, one FIFO memory of the 768K-word x 8-bit composition can be 8 DA<7:0> WCKA WRESA WEA 8 768K-w x 8-bit FIFO(A) controlled. QA<7:0> RCKA RRESA REA The operation of FIFO (A) is the same as that of mode 1. In mode 6, only all pins for the A-system are used. Therefore, the all input pins for the B/C-system should be fixed at "L" or "H". Also QB<7:0> and QC<7:0> become high impedance state. Mode7 Operation Description <Mode 7> DA<7:0> 8 8 512K-w x 8-bit FIFO(A) WCKA WRESA WEA QA<7:0> RCKA RRESA REA In mode 7, one of 512K-word x 8-bit FIFO and one of 256K-word x 8-bit FIFO memory can be controlled completely independently. The operation of FIFO (A) and FIFO (B) are the same as that of mode 1. In mode 7, only all pins for the A/C-system are used. Therefore, the all input pins for the B-system should be fixed at "L" or "H". DC<7:0> WCKC WRESC WEC 8 8 256K-w x 8-bit FIFO(B) Also QB<7:0> become high impedance state. QC<7:0> RCKC RRESC REC Mode8 Operation Description <Mode 8> DA<7:0> DB<3:0> WCKA WRESA WEA 12 12 512K-w x 12-bit FIFO(A) QA<7:0> QB<3:0> In mode 8, one FIFO memory of the 512K-word x 12-bit composition can be RCKA RRESA REA The operation of FIFO (A) is the same as that of mode 4. controlled. Also, please set the 12-bit I/O buses of FIFO (A) as mentioned in the table of mode 4 FIFO (A). In mode 8, only all pins for the A-system, DB<3:0> and QB<3:0> are used. Therefore, the write/read control pins for the B/C-system, DB<7:4> and DC<7:0> should be fixed at "L" or "H". Also QB<7:4> and QC<7:0> become high impedance state. REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 10 of 23 M66288FP Electrical Characteristics Absolute Maximum Ratings Symbol VCC18 VCCIO VI VO Pd Tstg (Ta = 0 ~ 70°C, unless otherwise noted) Parameter Supply voltage (1.8 V power supply ) Supply voltage (3.3 V power supply ) Input voltage Output voltage Maximum power dissipation Storage temperature Conditions A value based on GND Ta = 70 °C Ratings -0.3~+2.5 Unit V -0.3~+3.8 V -0.3~VCCIO+0.3 -0.3~VCCIO+0.3 800 -55~150 V V mW °C Recommended Operating Conditions Symbol VCC18 VCCIO Topr Parameter Supply voltage for internal circuit (1.8 V power supply ) Supply voltage for I/O (3.3 V power supply ) Operating ambient temperature Test conditions A value based on GND Min. 1.62 Limits Typ. 1.8 Max. 1.98 V 3.0 3.3 3.6 V 70 °C 0 Unit DC Characteristics (Ta = 0 ~ 70°C, Vcc18 = 1.8 ± 0.18 V, VccIO = 3.3 ± 0.3 V, GND = 0 V, unless otherwise noted) Symbol Parameter Test conditions VIH "H" input voltage VIL "L" input voltage VOH "H" output voltage IOH = -4mA VOL IIH IIL IOZH IOZL ICC18 "L" output voltage "H" input current "L" input current Off state "H" output current Off state "L" output current Average operating supply current (1.8 V) Average operating supply current (3.3 V) IOL = 4mA VI = VCCIO VI = GND VO = VCCIO VO = GND VCC18 = 1.8 V ± 0.18 V VCCIO = 3.3 V ± 0.3 V VI = repeat "H" and "L" VO= Output open tWCK = tRCK = 12.5 ns f = 1 MHz f = 1 MHz ICCIO CI CO Input capacitance Off state output capacitance REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 11 of 23 A value based on GND Min. 0.8 x VccIO Limits Typ. Unit Max. V 0.2 x VccIO VccIO - 0.4 V V 0.4 10 -10 10 -10 180 V µA µA µA µA mA 120 mA 10 15 pF pF M66288FP Power - on After power-on, this IC initializes some circuits of internal FIFO (1.8 V), using the built-in power-on reset circuit. This power-on reset is performed by using the VCC18 = 1.8 V system power supply. Either of the following conditions (1) or (2) should be met according to the power-on time of the VCC18. (1) When the power-on time of the VCC18 is 1 msec or less: Some circuits of internal FIFO are initialized by the built-in power-on reset circuit. No restriction is imposed on the power-on sequence between VCC18 and VCCIO = 3.3 V system power supply. When powering on again after power-on, provide an interval of 100 ms or more for the VCC18. At this time, the TEST1 (pin 99) pin should be fixed at "L". 1ms(max) 100ms(min) Vcc18 VCC18 VCC18 Vcc18 Vcc18 X 10% VCC18 x 10% GND Vcc18 X 10% VCC18 x 10% (2) When the power-on time of the VCC18 is more than 1 msec: Some circuits of internal FIFO should be initialized by the TEST1 (pin 99) pin. Input an initialize reset pulse of 200 ns or more after the power supplies (VCCIO, VCC18) reach to the VCC level. There is no problem even if reaching to the VCC level on which power supply. 3.0V~3.6V 3.0V~3.6V VCCIO VccIO VCCIO VccIO GND 1ms or more 1.62V~1.98V Vcc18 VCC18 VCC18 Vcc18 GND 200ns(min) TEST1 200ns(min) VCCIO VccIO GND Note: Some circuits of internal FIFO can be initialized by the TEST1 pin even if the power-on time of the Vcc18 is 1 msec or less. Note: Important matter; Provide write reset cycles and read reset cycles of 100 cycles or more, respectively after the Vcc reaches to the specified voltage after power-on. When inputting a reset pulse using the TEST1 (pin 99) pin, provide write reset cycles and read reset cycles of 100 cycles or more, respectively after inputting a reset pulse at power-on. There is no problem in this reset operation if a total of 100 cycles or more is achieved, even if discontinuous reset input is made. REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 12 of 23 M66288FP Timing Requirements (Ta = 0 ~ 70°C, Vcc18 = 1.8 ± 0.18 V, VccIO = 3.3 ± 0.3 V, GND = 0 V, unless otherwise noted) Symbol Parameter Limits Min. t WCK Write clock (WCK) cycle t WCKH Typ. Unit Max. 12.5 ns Write clock (WCK) "H" pulse width 5 ns t WCKL Write clock (WCK) "L" pulse width 5 ns t RCK Read clock (RCK) cycle 12.5 ns t RCKH Read clock (RCK) "H" pulse width 5 ns t RCKL Read clock (RCK) "L" pulse width 5 ns t DS Input data setup time to WCK 3.5 ns t DH Input data hold time to WCK 1 ns t RESS Reset setup time to WCK or RCK 3.5 ns t RESH Reset hold time to WCK or RCK 1 ns t NRESS Reset non-select setup time to WCK or RCK 3.5 ns t NRESH Reset non-select hold time to WCK or RCK 1 ns t WES Write enable setup time to WCK 3.5 ns t WEH Write enable hold time to WCK 1 ns t NWES Write enable non-select setup time to WCK 3.5 ns t NWEH Write enable non-select hold time to WCK 1 ns t RES Read enable setup time to RCK 3.5 ns t REH Read enable hold time to RCK 1 ns t NRES Read enable non-select setup time to RCK 3.5 ns t NREH Read enable non-select hold time to RCK 1 ns t r, t f Input pulse rise / fall time 3 ns Switching Characteristics (Ta = 0 ~ 70°C, Vcc18 = 1.8 ± 0.18 V, VccIO = 3.3 ± 0.3 V, GND = 0 V, unless otherwise noted) Symbol Parameter Limits Min. Typ. Unit Max. t AC Output access time to RCK t OH Output hold time to RCK 2 t OEN Output enable time to RCK 2 9 ns t ODIS Output disable time to RCK 2 9 ns REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 13 of 23 9 ns ns M66288FP Switching Characteristics Measurement Circuit Vcc IO RL = 1 KΩ SW1 Qn Qn SW2 CL = 10 pF: tAC, tOH Parameter tODIS (LZ) tODIS (HZ) tOEN (ZL) tOEN (ZH) Input pulse level CL = 3 pF: tOEN, tODIS RL = 1 KΩ SW1 Close Open Close Open SW2 Open Close Open Close : 0 ~ VCCIO Input pulse rise/fall time : 1 ns Decision voltage input : 1/2 VCCIO Decision voltage output : 1/2 VCCIO (However, tODIS (LZ) is 10% of output amplitude and tODIS (HZ) is 90% of that for decision). The load capacitance CL includes the floating capacitance of connection and the input capacitance of probe. tODIS and tOEN Measurement Condition VIH RCK 1/2 VccIO 1/2 VccIO VIL VIH RE VIL tODIS(HZ) tOEN(ZH) VOH 90% Qn 1/2 VccIO tODIS(LZ) Qn REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 14 of 23 tOEN(ZL) 1/2 VccIO 10% VOL M66288FP Operating Timing z Write Cycle n cycle n+1 cycle n+2 cycle Disable cycle n+4 cycle n+3 cycle WCK tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES WE tDS tDH Dn (n) tDS tDH (n+1) (n+2) (n+3) (n+4) WRES = "H" z Write Reset Cycle n-1 cycle n cycle 0 cycle Reset cycle 1 cycle WCK tWCK tNRESH tRESS tRESH tNRESS WRES Dn tDS tDH tDS tDH (n-1) (n) (0) (1) In case of WE = "L" REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 15 of 23 M66288FP z Combination Cycle of Write Reset and Write Enable n+1 cycle n cycle n+2 cycle Disable cycle 0 cycle 1 cycle WCK tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES WE tNRESH tRESS tRESH tNRESS WRES tDS tDH Dn (n) tDS tDH (n+1) (n+2) Note: There are no restrictions of WE to WRES. REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 16 of 23 (0) (1) M66288FP z Read Cycle n cycle n+1 cycle n+2 cycle Disable cycle n+3 cycle n+4 cycle RCK tRCK tRCKH tRCKL tREH tNREH tRES tNRES RE tODIS tAC (n) Qn (n+1) HIGH-Z (n+2) tOH tOEN (n+3) (n+4) tOH RRES = "H" z Read Reset Cycle n-1 cycle n cycle tRCK tNRESH tRESS Reset cycle 0 cycle 1 cycle RCK tRESH tNRESS RRES tAC Qn tAC (n-1) tOH tAC (n) tOH (0) (1) tOH In case of RE = "L" REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 17 of 23 M66288FP z Combination Cycle of Read Reset and Read Enable n cycle n+1 cycle tRCK tRCKH tRCKL n+2 cycle 0 cycle Disable cycle 1 cycle RCK tREH tNRES tNREH tRES RE tNRESH tRESS tRESH tNRESS RRES tAC Qn tAC (n) (n+1) (n+2) tOH Note: There are no restrictions of RE to RRES. REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 18 of 23 tOEN tODIS tOH HIGH-Z tAC (0) tOH (1) M66288FP Attentions when Write Cycle and Read Cycle Approach Each Other The interval m of 16 cycles or more between a write cycle and a read cycle should be secured, when the write cycle goes ahead of the read cycle on the following conditions, that is to say the interval less than 15 cycles is forbidden. WRES, RRES="H"; WE, RE="L", and ●Both write side and read side are activated continuously ●Either write side or read side is temporarily stopped owing to the stop of WCK or RCK When this restriction to the interval is broken on these conditions, writing data is guaranteed, but reading data isn’t guaranteed not only during breaking it but also during the following 16 cycles after it is applied. In this 16 cycles, read disable and read reset cycles are not counted. But the following condition is an exception to restrict to forbid the intervals less than 15 cycles. ●Either write side or read side is temporarily stopped owing to reset cycles (WRES or RRES="L") or disable cycles (WE or RE ="H") Note: Also, when the address counter is incremented up to the last cycle of 1-line and then returned to 0 cycle, the interval m of 16 cycles or more between a write and read cycles should be secured, taking account that they are cyclic and serial lines. n+16 cycle n+17 cycle Write disable cycle n+18 cycle n+19 cycle n+20 cycle n+21 cycle n+22 cycle n+23 cycle WCK WE ( n+18 ) ( n+17 ) ( n+16 ) Dn ( n+19 ) ( n+21 ) ( n+20 ) ( n+22 ) ( n+23 ) m≦15; WRES,RRES=H; "m", the interval between a write cycle and a read cycle WE,RE=L ⑯ ⑯ ⑮ ⑭ ⑭ ⑭ n cycle n+1 cycle n+2 cycle n+3 cycle n+4 cycle n+5 cycle ⑮ ⑯ Read disable cycle ⑯ ⑯ n+6 cycle n+7 cycle RCK RE Qn ( n ) ( n+1 ) ( n+2 ) ( n+3 ) read data are defined owing to write disable cycle. HIGH-Z invalid read data of forbidden cycles are undefined. invalid read data of 16 cycles after forbidden cycles are undefined. The conditions that the read cycle goes ahead of the write cycle or that write cycle and read cycle are accordant, are exceptions to the restriction to forbid the intervals less than 15cycles. REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 19 of 23 M66288FP Variable Length Delay Bits The 1-line length (cycle number) of each mode is shown in the table. Operation MODE 1-line length MODE 1 - MODE 5 262144-cycle MODE 6 786432-cycle MODE 7 524288-cycle (A-system), 262144-cycle (C-system) MODE 8 524288-cycle The following, the case of the MODE 1 - MODE 5 (1-line length = 262144-cycle) is explained to an example. 1-line (262144-bit) Delay In read cycles, an output data is read at the (first) rising edge of RCK (i.e. the start of the cycle ) . In write cycles, an input data is written at the (second) rising edge of WCK (i.e. the end of the cycle ) . So 1-line delay can be made easily according to the control method of the following figure. Reset cycle 0 cycle 1 cycle 262142 cycle 2 cycle 262144 cycle (0’) 262143 cycle 262145 cycle (1’) 262146 cycle (2’) WCK RCK tRESS tRESH WRES RRES tDS tDH Dn (0) tDS tDH (1) (2) (262141) (262142) (262143) (0’) tAC 262144 cycle Qn (1’) (2’) (1) (2) tOH (0) WE, RE = "L" N-bit Delay 1 (Reset at a cycle corresponding to delay length) Reset cycle 0 cycle 1 cycle 2 cycle n cycle Reset cycle 0 cycle (0’) 1 cycle (1’) 2 cycle (2’) WCK RCK tRESS tRESH tRESS tRESH WRES RRES tDS tDH Dn (0) tDS tDH (1) (2) (n-1) Delay length n Qn (n) (0’) tAC (1’) (2’) (1) (2) tOH (0) 262144 ≥ n ≥ 16 WE, RE = "L" Note: The interval of 16 cycles or more between a write cycle and a read cycle should be secured to read data written in a certain cycle. REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 20 of 23 M66288FP N-bit Delay 2 (Sliding timings of WRES and RRES at a cycle corresponding to delay length) Reset cycle 0 cycle 1 cycle n-1 cycle Reset cycle 2 cycle n+1 cycle 1 cycle n cycle 0 cycle n+2 cycle 2 cycle n+3 cycle 3 cycle ·····Write side ·····Read side WCK RCK tRESS tRESH WRES tRESS tRESH tDS tDH tDS tDH RRES (0) Dn (1) (2) (n-2) (n-1) (n) tAC Delay length n (n+1) (n+2) (n+3) (1) (2) (3) tOH Qn (0) 262144 ≥ n ≥ 16 WE, RE = "L" N-bit Delay 3 (Sliding address by disabling RE at a cycle corresponding to delay length) Reset cycle 0 cycle 1 cycle n cycle 0 cycle n-1 cycle 2 cycle n+1 cycle 1 cycle n+2 cycle 2 cycle n+3 cycle 3 cycle ·····Write side ·····Read side WCK RCK tRESS tRESH WRES RRES tNREH tRES RE tDS tDH Dn (0) tDS tDH (1) (2) Delay length n Qn HIGH-Z (n-2) (n-1) (n) tAC (n+1) (n+2) (n+3) (1) (2) (3) tOH (0) 262144 ≥ n ≥ 16 WE = "L" REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 21 of 23 M66288FP Shortest Reading of Written Data in N Cycle when Write and Read Operated Asynchronously The interval of 16 cycles or more between a write cycle and a read cycle should be secured and WCK and RCK should be inputted for 16 cycles or more based on beginning of write n cycle at any timing to read written data (data fetched at the rising edge of WCK shown *1 in the following figure) with n cycles on write side. On read side, n cycles should be started after the completion of n+15 cycles on write side (Δt ≥ 0 in the following figure). Output data becomes undefined when these restrictions are not filled. Reference 16 cycles or more are required in WCK. n-1 cycle n cycle n+14 cycle n+15 cycle n+16 cycle n+17 cycle n+18 cycle n+19 cycle *1 WCK Dn n+1 cycle (n-1) (n) (n+1) (n+14) 16 cycles or more are required in RCK. n-1 cycle (n+15) (n+16) (n+17) (n+18) (n+19) Δt≥0 n cycle n+1 cycle RCK Qn invalid (n) (n+1) Longest Reading of Written Data in N Cycle: 1-line Delay Data output Qn of n cycle <1>* can be read immediately before until the start of n cycle <1>* on read side and the start of n cycle <2>* on write side over lap each other. REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 22 of 23 M66288FP PACKAGE OUTLINE All trademarks and registered trademarks are the property of their respective owners. REJ03F0156-0310 Rev.3.10 Apr.04.2008 Page 23 of 23