DATA SHEET MOS INTEGRATED CIRCUIT µPD705102 V832TM 32-BIT MICROPROCESSOR DESCRIPTION The µPD705102 (V832) is a 32-bit RISC microprocessor for embedded control applications, with a highperformance 32-bit V830TM processor core and many peripheral functions such as a SDRAM/ROM controller, 4channel DMA controller, real-time pulse unit, serial interface, interrupt controller, and power management. In addition to high interrupt response speed and optimized pipeline structure, the V832 offers sum-of-products operation instructions, concatenated shift instructions, and high-speed branch instructions to realize multimedia functions, and therefore can provide high performance in multimedia systems such as Internet/intra-net systems, car navigation systems, digital still cameras, and color faxes. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. V832 User’s Manual — Hardware: U13577E V830 FamilyTM User’s Manual — Architecture: U12496E FEATURES • DMA controller: 4 channels • CPU function • Serial interface function • V830-compatible instructions • Instruction cache: 4 Kbytes • Asynchronous serial interface (UART): 1 channel • Instruction RAM: 4 Kbytes • Clocked serial interface (CSI): • Data cache: 4 Kbytes • Data RAM: 4 Kbytes • Dedicated baud rate generator (BRG): 1 channel • Timer/counter function • 16-bit timer/event counter: 1 channel • Minimum number of instruction execution cycles: • 16-bit interval timer: 1 cycle 32 bits × 32 • Clock generation function: PLL clock synthesizer (6× or • Memory space and I/O space: 4 Gbytes each ment modes • Non-maskable: External input: 1 External input: 8 (of which 4 are multiplexed with internal sources) Internal source: 11 types 8× multiplication) • Standby function: HALT, STOP, and power manage- • Interrupt/exception processing function • Maskable: 1 channel • Port function: 21 I/O ports • Number of general purpose registers: 1 channel • Debug function • Debug-dedicated synchronous serial interface: 1 channel • Trace-dedicated interface: 1 channel • Bus control function • Wait control function • Memory access control function The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U13675EJ2V1DS00 (2nd edition) Date Published July 1999 N CP(K) Printed in Japan The mark shows major revised points. © 1999 µPD705102 ORDERING INFORMATION Part Number Package µPD705102GM-143-8ED 160-pin plastic LQFP (fine pitch) (24 × 24 mm) µPD705102GM-133-8ED 160-pin plastic LQFP (fine pitch) (24 × 24 mm) PIN CONFIGURATION (TOP VIEW) • 160-pin plastic LQFP (fine pitch) (24 × 24 mm) µPD705102GM-143-8ED 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND_O A20 A21 A22 A23 CLKOUT TRCDATA0 TRCDATA1 TRCDATA2 TRCDATA3 DDI DCK DMS DDO VDD_PLL X1 X2 GND_PLL VDD_I GND_I IC1 BT16B RESET NMI DRST CMODE PORT3/RXD PORT4/TXD PORT2/SI PORT1/SO PORT0/SCLK VDD_O GND_O INTP10/TO10 INTP12/TO11 PORTB5/INTP11 PORTB3/INTP13 PORTB0/TI PORTB1/TCLR VDD_I 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 GND_O CS1 CS0 WE RAS UUDQM ULDQM LUDQM LLDQM VDD_O GND_O SDCLKOUT CKE CAS A1 A2 A3 A4 VDD_I GND_I VDD_O GND_O A5 A6 A7 A8 A9 A10 A11 VDD_O GND_O A12 A13 A14 A15 A16 A17 A18 A19 VDD_O 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 VDD_O D31 D30 D29 D28 D27 D26 D25 D24 GND_I VDD_I GND_O VDD_O D23 D22 D21 D20 D19 D18 D17 D16 GND_O VDD_O D15 D14 D13 D12 D11 D10 D9 D8 GND_O VDD_O D7 D6 D5 D4 D3 D2 GND_I µPD705102GM-133-8ED Caution 2 Directly connect the IC1 (Internally connected 1) pin to GND_O. Data Sheet U13675EJ2V1DS00 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VDD_I D1 D0 GND_O VDD_O MRD MWR LLBEN LUBEN ULBEN UUBEN IOWR IORD BCYST READY R/W HLDRQ HLDAK GND_O VDD_O CS2 CS3 CS4 CS5 CS6 CS7 TC/STOPAK PORTA1/DMAAK0 PORTA3/DMAAK1 PORTA5/DMAAK2 PORTA7/DMAAK3 PORTA0/DMARQ0 PORTA2/DMARQ1 PORTA4/DMARQ2 PORTA6/DMARQ3 PORTB7/INTP03 PORTB6/INTP02 PORTB4/INTP01 PORTB2/INTP00 GND_I µPD705102 PIN NAMES A1 to A23: Address Bus NMI: BCYST: Bus Cycle Start PORT0 to PORT4, BT16B: Boot Bus Size 16-bit PORTA0 to PORTA7, CAS: Column Address Strobe PORTB0 to PORTB7: Port CKE: Clock Enable R/W: CLKOUT: Clock Out RAS: Row Address Strobe CMODE: Clock Mode READY: Ready CS0 to CS7: Chip Select RESET: Reset D0 to D31: Data Bus RXD: Receive Data DCK: Debug Clock SCLK: Serial Clock DDI: Debug Data Input SDCLKOUT: SDRAM Clock Out DDO: Debug Data Output SI: Serial Input SO: Serial Output DMAAK0 to DMAAK3: DMA Acknowledge DMARQ0 to DMARQ3: Non-Maskable Interrupt Request Bus Read or Write Status STOPAK: Stop Acknowledge TC: Terminal Count DMA Request TCLR: Timer Clear Debug Mode Select TI: Timer Input DRST: Debug Reset TO10, TO11: Timer Output GND_I: Ground TRCDATA0 to TRCDATA3: Trace Data GND_O: Ground TXD: Transmit Data GND_PLL: PLL Ground ULBEN: Upper Lower Byte Enable HLDAK: Hold Acknowledge ULDQM: Upper Lower DQ Mask enable HLDRQ: Hold Request UUBEN: Upper Upper Byte Enable IC1: Internally Connected UUDQM: Upper Upper DQ Mask enable VDD_I: Power Supply (2.5 V) Interrupt Request From Peripheral VDD_O: Power Supply (3.3 V) I/O Read VDD_PLL: PLL Power Supply (2.5 V) IOWR: I/O Write WE: Write Enable LLBEN: Lower Lower Byte Enable X1, X2: Crystal Oscillator LLDQM: Lower Lower DQ Mask enable LUBEN: Lower Upper Byte Enable LUDQM: Lower Upper DQ Mask enable MRD: Memory Read MWR: Memory Write DMS: INTP00 to INTP03, INTP10 to INTP13: IORD: Data Sheet U13675EJ2V1DS00 3 µPD705102 INTERNAL BLOCK DIAGRAM DCK DMS DDI DDO TRCDATA3 to TRCDATA0 DRST X1 X2 CLKOUT SDCLKOUT RESET NMI TI, TCLR INTP10/TO10, INTP12/TO11 INTP11, INTP13 INTP00 to INTP03 DCU CG BCU V830 core SYU RPU ICU R/W IOWR IORD MWR MRD UUBEN, ULBEN, LUBEN, LLBEN READY BT16B BCYST CS7 to CS0 A23 to A1 D31 to D0 HLDRQ HLDAK RAS CAS UUDQM, ULDQM, LUDQM, LLDQM CKE WE STOPAK CMODE PIO SCLK SO SI BRG CSI UART DMAC TXD RXD 4 Data Sheet U13675EJ2V1DS00 TC DMARQ3 to DMARQ0 DMAAK3 to DMAAK0 µPD705102 CONTENTS 1. PIN FUNCTIONS .................................................................................................................................. 6 1.1 Port Pins ....................................................................................................................................................... 6 1.2 Non-Port Pins ............................................................................................................................................... 7 2. INTERNAL UNITS ................................................................................................................................ 9 3. CPU FUNCTION ................................................................................................................................. 11 4. INTERRUPT/EXCEPTION PROCESSING FUNCTION ..................................................................... 12 5. BUS CONTROL FUNCTION .............................................................................................................. 14 6. WAIT CONTROL FUNCTION ............................................................................................................. 14 7. MEMORY ACCESS CONTROL FUNCTION ...................................................................................... 15 7.1 SDRAM Control Function .......................................................................................................................... 15 7.2 Page-ROM Control Function ..................................................................................................................... 17 8. DMA FUNCTION ................................................................................................................................ 18 9. SERIAL INTERFACE FUNCTION ...................................................................................................... 20 9.1 Asynchronous Serial Interface (UART) .................................................................................................... 20 9.2 Clocked Serial Interface (CSI) ................................................................................................................... 22 9.3 Baud Rate Generator (BRG) ...................................................................................................................... 23 10. TIMER/COUNTER FUNCTION .......................................................................................................... 24 11. PORT FUNCTION .............................................................................................................................. 27 12. CLOCK GENERATION FUNCTION ................................................................................................... 32 13. STANDBY FUNCTION ....................................................................................................................... 33 14. RESET/NMI CONTROL FUNCTION .................................................................................................. 35 15. INSTRUCTIONS ................................................................................................................................. 36 15.1 Instruction Format ..................................................................................................................................... 36 15.2 Instructions (Listed Alphabetically) ......................................................................................................... 38 16. ELECTRICAL SPECIFICATIONS ...................................................................................................... 48 17. PACKAGE DRAWING ........................................................................................................................ 75 18. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 76 Data Sheet U13675EJ2V1DS00 5 µPD705102 1. PIN FUNCTIONS 1.1 Port Pins Pin Name PORT0 I/O Schmitt I/O PORT1 I/O PORT2 Schmitt I/O Function PORT 5-bit input/output port. Input/output can be specified in 1-bit units. PORT3 SCLK SO SI RXD PORT4 I/O PORTA0 I/O PORTA1 PORTA2 TXD PORTA 8-bit input/output port. Input/output can be specified in 1-bit units. DMARQ0 DMAAK0 DMARQ1 PORTA3 DMAAK1 PORTA4 DMARQ2 PORTA5 DMAAK2 PORTA6 DMARQ3 PORTA7 DMAAK3 PORTB0 PORTB1 PORTB2 6 Alternate Function I/O PORTB 8-bit input/output port. Input/output can be specified in 1-bit units. TI TCLR INTP00 PORTB3 INTP13 PORTB4 INTP01 PORTB5 INTP11 PORTB6 INTP02 PORTB7 INTP03 Data Sheet U13675EJ2V1DS00 µPD705102 1.2 Non-Port Pins (1/2) Pin Name I/O Function Alternate Function D0 to D31 3-state I/O Data bus — A1 to A23 3-state output Address bus — READY Input End of bus cycle enable — HLDRQ Input Bus hold request — HLDAK Output Bus hold enable — MRD 3-state output Memory read strobe — UUBEN Byte enable output (most significant byte: D31 to D24) — ULBEN Byte enable output (enables second byte: D23 to D16) — LUBEN Byte enable output (enables third byte: D15 to D8) — LLBEN Byte enable output (enables least significant byte: D7 to D0) — IORD I/O read strobe — IOWR I/O write strobe — MWR Memory write strobe — BT16B Input CS7 space bus size setting — BCYST 3-state output Bus cycle start output — R/W output — Input Reset input — Crystal resonator connection (open when external clock input) — R/W RESET X1 — X2 Schmitt input Crystal resonator connection/external clock input — CLKOUT Output Bus clock output — CMODE Input PLL multiplication factor setting (×6, ×8) — CS2, CS7 3-state output Memory chip select output — Memory I/O chip select output — CS3 to CS6 STOPAK Output STOP mode report output TC INTP10 Input Maskable interrupts TO10 INTP11 PORTB5 INTP12 TO11 INTP13 PORTB3 INTP00 PORTB2 INTP01 PORTB4 INTP02 PORTB6 INTP03 PORTB7 NMI Non-maskable interrupt — SDRAM RAS strobe — UUDQM DQ mask enable (most significant byte: D31 to D24) — ULDQM DQ mask enable (second byte: D23 to D16) — LUDQM DQ mask enable (third byte: D15 to D8) — LLDQM DQ mask enable (least significant byte: D7 to D0) — RAS 3-state output Data Sheet U13675EJ2V1DS00 7 µPD705102 (2/2) Pin Name WE I/O 3-state output Function SDRAM write strobe — CAS SDRAM CAS strobe — CS0 SDRAM chip select — CS1 SDRAM/SRAM (ROM) chip select — CKE SDRAM clock enable — SDCLKOUT Output SDRAM clock output — DMARQ0 Input DMA requests (CH0 to CH3) PORTA1 DMARQ1 PORTA3 DMARQ2 PORTA5 DMARQ3 PORTA7 DMAAK0 Output DMA enable (CH0 to CH3) PORTA0 DMAAK1 PORTA2 DMAAK2 PORTA4 DMAAK3 PORTA6 TC DMA transfer end output STOPAK TO10 Timer 1 output INTP10 TO11 TCLR INTP12 Input Timer 1 clear, start input Timer 1 count clock input PORTB0 RXD Schmitt input UART data input PORT3 TXD Output UART data output PORT4 SCLK Schmitt I/O CSI clock I/O PORT0 SI Schmitt input CSI data input PORT2 SO Output CSI data output PORT1 DCK Schmitt input Debug clock input — DDI Input Debug data input — DDO Output Debug data output — DMS Input Debug mode select — DCU reset input — Trace data output — Positive power supply (2.5 V) — VDD_O Positive power supply (3.3 V) — GND_I Ground (2.5 V) — GND_O Ground (3.3 V) — VDD_PLL PLL (internal clock generator) positive power supply (2.5 V) — GND_PLL PLL (internal clock generator) ground potential (2.5 V) — TI DRST TRCDATA0 to TRCDATA3 VDD_I 8 Alternate Function Output — Data Sheet U13675EJ2V1DS00 PORTB1 µPD705102 2. INTERNAL UNITS (1) Bus control unit (BCU) Controls the address bus, data bus, and control bus pins. The major functions of BCU are as follows: (a) Bus arbitration Arbitrates the bus mastership among bus masters (CPU, SDRAMC, DMAC, and external bus masters). The bus mastership can be changed after completion of the bus cycle under execution, and in an idle state. (b) Wait control Controls eight areas in the 16-Mbyte space corresponding to eight chip select signals (CS0 through CS7). Generates chip select signals, controls wait states, and selects the type of bus cycle. (c) SDRAM controller Generates commands and controls access to SDRAM. CAS latency is 2 only. (d) ROM controller Accessing ROM with page access function is supported. The bus cycle immediately before and addresses are compared, and wait states are controlled in the normal access (off-page) or page access (on-page) modes. A page width of 8 bytes to 16 bytes can be supported. (2) Interrupt controller (ICU) Services maskable interrupt requests (INTP00 through INTP03, and INTP10 through INTP13) from internal peripheral hardware and external sources. The priorities of these interrupt requests can be specified in units of four groups, and edge-triggered or level-triggered interrupts can be nested. (3) DMA controller (DMAC) Transfers data between memory and I/O in place of CPU. The transfer type is 2-cycle transfer. Two transfer modes, single transfer and demand transfer, are available. (4) Serial interface (UART/CSI/BRG) One asynchronous serial interface (UART) channel and one clocked serial interface (CSI) channel is provided. As the serial clock source, the output of the baud rate generator (BRG) and the bus clock can be selected. (5) Real-time pulse unit (RPU) Provides timer/counter functions. The on-chip 16-bit timer/event counter and 16-bit interval timer can be used to calculate pulse intervals and frequencies, and to output programmable pulses. (6) Clock generator (CG) A frequency six or eight times higher than that of the resonator connected to the X1 and X2 pins is supplied as the operating clock of the CPU. In addition, both a bus clock, which functions as the operating clock of the peripheral units, and SDCLKOUT, which functions as an operating clock, are supplied from the CLKOUT pin. An external clock can be also input instead of connecting a resonator. For reducing the power consumption, the function switching the frequencies of the CPU clock and bus clock with power management control (PMC) is provided. Data Sheet U13675EJ2V1DS00 9 µPD705102 (7) Port (PIO) Provides port functions. Twenty-one I/O ports are available. The pins of these ports can be used as port pins or other function pins. (8) System control unit (SYU) A circuit that eliminates noise on the RESET signal (input)/NMI signal (input) is provided. (9) Debug control unit (DCU) A circuit to realize mapping and trace functions is provided to implement basic debugging functions. 10 Data Sheet U13675EJ2V1DS00 µPD705102 3. CPU FUNCTION The features of the CPU function are as follows: • High-performance 32-bit architecture for embedded control applications • Cache memory Instruction cache: 4 Kbytes Data cache: 4 Kbytes • Internal RAM Instruction RAM: 4 Kbytes Data RAM: 4 Kbytes • 1-clock pitch pipeline structure • 16-/32-bit length instruction format • Address/data separated type bus • 4-Gbyte linear address • Thirty-two 32-bit general registers • Register/flag hazard interlock is handled by hardware • 16 levels of interrupt response • 16-bit bus fixed function • 16-bit bus system can be constructed • Ideal instructions for any application field: • Sum-of-products operation • Saturation operation • Branch prediction • Concatenation shift • Block transfer instruction Data Sheet U13675EJ2V1DS00 11 µPD705102 4. INTERRUPT/EXCEPTION PROCESSING FUNCTION The features of the interrupt/exception processing function are as follows: • Interrupt • Non-maskable interrupt: 1 source • Maskable interrupt: 15 sources • Priority of the programmable interrupt can be specified in four levels • Nesting interrupt can be controlled according to the priority • Mask can be specified for each maskable interrupt request • Valid edge of an external interrupt request can be specified • Noise elimination circuit provided for the non-maskable interrupt pin (NMI) • Exception • Software exception: 32 sources • Exception trap: 4 sources The interrupt/exception sources are shown in Tables 4-1 and 4-2. Table 4-1. Reset/Non-maskable Interrupt/Exception Source List Type Classification Source of Interrupt/Exception NameNote 1 Cause Exception Code (ECR) Handler Address Restore PCNote 2 Reset Interrupt RESET Reset input FFF0H FFFFFFF0H Non-maskable Interrupt NMI NMI input FFD0H FFFFFFD0H next PCNote 3 Software exception Exception Exception trap Exception Undefined TRAP 1nH TRAP instruction FFBnH FFFFFFB0H TRAP 0nH TRAP instruction FFAnH FFFFFFA0H next PC NMI Dual exception Note 4 FFFFFFD0H current PC FAULT Fatal exception Not affected FFFFFFE0H I-OPC Illegal instruction code FF90H FFFFFF90H DIV0 Zero division FF80H FFFFFF80H Notes 1. Handler names used in development tools or software. 2. The PC value saved to EIPC/FEPC/DPC when interrupt/exception processing is started. 3. Execution of all instructions cannot be stopped by an interrupt. 4. The exception code of an exception causing a dual exception. Remark n = 0H to FH 12 Data Sheet U13675EJ2V1DS00 µPD705102 Table 4-2. Maskable Interrupt List Type Classifi- Group In-Group cation Priority Mask- Interrupt GR3 able GR2 GR1 GR0 Interrupt Source Name Cause Exception Unit — Code Handler AddressNote 3 Restore Note 1 HCCW.IHA=0 HCCW.IHA=1 PC 3 RESERVED Reserved 2 INTOV1 Timer 1 overflow RPU FEF0H FFFFFEF0H FE0000F0H next Note 2 FEE0H FFFFFEE0H FE0000E0H PC 1 INTSER UART receive error UART FED0H FFFFFED0H FE0000D0H 0 INTP03 INTP03 pin input External FEC0H FFFFFEC0H FE0000C0H 3 INTSR UART receive end UART FEB0H FFFFFEB0H FE0000B0H 2 INTST UART transmit end UART FEA0H FFFFFEA0H FE0000A0H 1 INTCSI CSI transmit/receive end CSI 0 INTP02 3 INTDMA 2 FE90H FFFFFE90H FE000090H INTP02 pin input External FE80H FFFFFE80H FE000080H DMA transfer end DMAC FE70H FFFFFE70H FE000070H INTP10/ INTCC10 INTP10 pin input/ coincidence of CC10 External/ FE60H RPU FFFFFE60H FE000060H 1 INTP11/ INTCC11 INTP11 pin input/ coincidence of CC11 External/ FE50H RPU FFFFFE50H FE000050H 0 INTP01 INTP01 pin input External FE40H FFFFFE40H FE000040H 3 INTCM4 Coincidence of CM4 RPU FE30H FFFFFE30H FE000030H 2 INTP12/ INTCC12 INTP12 pin input/ coincidence of CC12 External/ FE20H RPU FFFFFE20H FE000020H 1 INTP13/ INTCC13 INTP13 pin input/ coincidence of CC13 External/ FE10H RPU FFFFFE10H FE000010H 0 INTP00 INTP00 pin input External FE00H FFFFFE00H FE000000H Notes 1. The PC value saved to EIPC when interrupt processing is started. 2. Execution of all instructions cannot be stopped by an interrupt. 3. FFFFFEn0H can be selected as a handler address when HCCW.IHA = 0, and FE0000n0H can be selected when HCCW.IHA = 1 (n = 0H to FH). Caution The exception codes and handler addresses of the maskable interrupts shown above are the values if the default priority (IGP = E4H) is used. The correspondence between the interrupt source and the handler address is changed from Table 4-2 if the priority of the group (GR0 to GR3) is changed according to the value of the interrupt group priority register (IGP). Data Sheet U13675EJ2V1DS00 13 µPD705102 5. BUS CONTROL FUNCTION The features of the bus control function are as follows: • SDRAM, Page-ROM, SRAM (ROM) or I/O can be directly connected • SDRAM read/write access with 1 bus clock minimum • SDRAM byte access control with four ××DQM signals • Wait control with READY signal • RAM, ROM or I/O byte access control with four ××BEN signals • 32-/16-bit bus width can be set every CS space • When the 16-bit memory or I/O are accessed by data bus, the external data bus width can be set by the data bus width control register (DBC). Remarks 1. ××BEN: LLBEN, LUBEN, ULBEN, UUBEN 2. ××DQM: LLDQM, LUDQM, ULDQM, UUDQM 6. WAIT CONTROL FUNCTION The features of the wait control function are as follows: • Controls 8 blocks in accordance with I/O and memory spaces • Linear address space of each block: 16 Mbytes • Bus cycle select function Block 0: SDRAM Block 1: SDRAM, SRAM (ROM) selectable Block 2: SRAM (ROM) Blocks 3 through 6: I/O or SRAM (ROM) selectable Block 7: Page-ROM or SRAM (ROM) selectable • Data bus width select function Data bus width selectable between 32 bits and 16 bits for each block • Wait control function Blocks 0 and 1: SDRAM wait control function is not provided Blocks 1 through 4 and 7: 0 to 7 wait states Blocks 5 and 6: 0 to 15 wait states • Idle state insertion function 0 to 7 states for each block (bus clock) 14 Data Sheet U13675EJ2V1DS00 µPD705102 7. MEMORY ACCESS CONTROL FUNCTION The features of the memory access control function are as follows: • SDRAM control function • Generates RAS, CAS, WE, CKE, LLDQM, LUDQM, ULDQM, and UUDQM signals • Address multiplex: 8 or 9 bits • Timing control of SDRAM access Command interval from REF to REF/ACT: 3 to 6 bus clocks selectable Command interval from ACT to PRE: 3 or 4 bus clocks selectable Command interval from PRE to ACT: 1 or 2 bus clocks selectable Command interval from ACT to READ/WRITE: 1 or 2 bus clocks selectable CAS latency: 2 bus clocks fixed • Auto refresh and self-refresh functions • 8-bank control (4 banks × 2 blocks) • Page-ROM control function • Page size: 8 or 16 bytes • Wait control during page access: 0 to 7 wait states 7.1 SDRAM Control Function The BCU generates RAS, CAS, WE, CS0, CS1, CKE, LLDQM, LUDQM, ULDQM, and UUDQM signals and controls access to the SDRAM. Addresses are output to the SDRAM from the address pins by multiplexing row and column addresses. The connected SDRAM must be of ×8 bits or more. The refresh mode is a CAS-before-RAS (CBR) mode, and the refresh cycle can be arbitrarily set. Self refresh is performed in the STOP mode. (1) Address multiplex function An address is multiplexed as shown in Tables 7-1 and 7-2 when row and column addresses are output in the SDRAM cycle, depending on the values of the RAW and CAW bits of the SDRAM configuration register (SDC). In the tables, a1 through a23 indicate the address output by the CPU, and A1 through A15 indicate the address pins of the V832. Data Sheet U13675EJ2V1DS00 15 µPD705102 Table 7-1. Output of Row Address and Column Address (32-bit data width) External Address Pin BAW RAW CAW 0 00 00 Output Timing A15 A14 A13 A12 A11 A10 (a15) (a14) a23 a22 a21* AP (a11) (a10) a9 to a2 a21* a20 a19 a18 a17 to a10 Column address (a15) (a14) a22* AP (a11) a10 a9 to a2 Row address Column address (a15) a23 a22* a21 a20 a19 a18 to a11 (a15) a22* a21* AP (a11) (a10) a9 to a2 a23 a22* a21* a20 a19 a18 a17 to a10 Column address (a15) a23* a22* AP (a11) a10 a9 to a2 Row address (a15) a23* a22* a21 a20 a19 a18 to a11 Column address a23* a22* (a13) AP (a11) (a10) a9 to a2 Row address a23* a22* a21 a20 a19 a18 a17 to a10 Column address Row address 0 00 01 1 00 00 Row address 1 00 01 1 01 00 A9 to A2 Remarks 1. * indicates bank address specification. 2. AP is a bit used to specify a command and is fixed to low level. 3. Addresses in parentheses (a××) and A1 and A16 through A23 pins do not multiplex addresses and always output the original values. Table 7-2. Output of Row Address and Column Address (16-bit data width) External Address Pin BAW RAW CAW Output Timing 0 00 00 Column address A15 A14 A13 (a15) (a14) (a13) a23 a22 a21 Column address (a15) (a14) (a13) Row address (a15) a23 a22 Column address (a15) (a14) a21* a23 a22 a21* Column address (a15) (a14) a22* Row address (a15) a23 Column address (a15) a22* a23 a22* Row address 0 1 00 00 01 00 Row address 1 00 01 1 01 00 Row address A12 A11 A10 A9 A8 to A1 a20* AP (a10) (a9) a8 to a1 a20* a19 a18 a17 a16 to a9 a21* AP (a10) a9 a8 to a1 a21* a20 a19 a18 a17 to a10 a20* AP (a10) (a9) a8 to a1 a20* a19 a18 a17 a16 to a9 a21* AP (a10) a9 a8 to a1 a22* a21* a20 a19 a18 a17 to a10 a21* (a12) AP (a10) (a9) a8 to a1 a21* a20 a19 a18 a17 a16 to a9 Remarks 1. * indicates bank address specification. 2. AP is a bit used to specify a command and is fixed to low level. 3. Addresses in parentheses (a××) and A16 through A23 pins do not multiplex addresses and always output the original values. 16 Data Sheet U13675EJ2V1DS00 µPD705102 (2) On-page/off-page decision When the PAE bit of the SDRAM configuration register (SDC) is 1 (page access enabled), whether the SDRAM access to be started is in the same page as the previous SDRAM access is decided. When the PAE bit is 0, the off-page cycle is always started. Table 7-3 shows the relation between an address to be compared and address shift. Table 7-3. Address Compared by on-page/off-page Decision Address Shift Data Bus Width 16 bits 32 bits 8 a23 to a9 a23 to a10 9 a23 to a10 a23 to a11 (3) Refresh function The BCU can automatically generate the distributed auto refresh cycle necessary for refreshing the SDRAM. Whether refreshing is enabled or disabled and the refresh interval are set by the refresh control register (RFC). The BCU has a refresh request queue that can store refresh requests up to seven times. 7.2 Page-ROM Control Function The BCU controls page access to the Page-ROM. Page access to the Page-ROM is valid during burst access. The page size (8 bytes/16 bytes) and the number of wait states (0 wait/1 wait) during page access can be set by using the Page-ROM configuration register (PRC). Data Sheet U13675EJ2V1DS00 17 µPD705102 8. DMA FUNCTION The features of the DMA function are as follows: • Four independent DMA channels • Transfer unit: bytes, half words (2 bytes), words (4 bytes) • Maximum number of transfers: 16,777,216 (224) times • Transfer type: 2-cycle transfer • Two transfer modes • Single transfer mode • Demand transfer mode • Transfer request • External DMARQ pin (×4) • Request from internal peripheral hardware (serial interface (×3 channels) and timer) • Request from software • Transfer source and destination • Between memory and I/O • Between memory and memory • Programmable wait function • DMA transfer end signal output (TC) 18 Data Sheet U13675EJ2V1DS00 µPD705102 The configuration of the DMA controller (DMAC) is shown below. Figure 8-1. Block Diagram of DMAC DMAC Internal I/O BCU Internal peripheral I/O bus RAM External bus ROM Bus interface DMA source address register (DSA) DMAAK0 to 3 DMA control register (DCHC, DC) TC Channel control block DMARQ0 to 3 I/O INTST DMA transfer count register (DBC) INTCSI Counter control block INTSR I/O INTCM4 DMA destination address register (DDA) INTDMA Address control block Data Sheet U13675EJ2V1DS00 19 µPD705102 9. SERIAL INTERFACE FUNCTION The following channels are provided for the serial interface function. • Asynchronous serial interface (UART): 1 channel • Clocked serial interface (CSI): 1 channel • Baud rate generator (BRG): 1 channel 9.1 Asynchronous Serial Interface (UART) The features of the asynchronous serial interface (UART) are as follows: • Full duplex communication. Receive buffer (RXB) is provided (transmit buffer (TXB) is not provided). • Two-pin configuration (The UART of the V832 does not have the SCLK and CTS pins.) • TXD: Transmit data output pin • RXD: Receive data input pin • Transfer rate: 300 bps to 153600 bps (bus clock: 47.6 MHz, with BRG) : 150 bps to 76800 bps (bus clock: 35.7 MHz, with BRG) • Baud rate generator Serial clock source can be selected from baud rate generator output or bus clock (φ) • Receive error detection function • Parity error • Framing error • Overrun error • Three interrupt sources • Receive error interrupt (INTSER) The interrupt request is generated by ORing three types of receive errors. • Receive end interrupt (INTSR) The receive end interrupt request is generated after completion of receive data transfer from the shift register to the receive buffer in the reception enabled status. • Transmit end interrupt (INTST) The transmit end interrupt request is generated after completion of serial transfer of transmit data (9, 8, or 7 bits) from the shift register. The character length of the transmit/receive data is specified by the ASIM00 and ASIM01 registers. • Character length: 7 or 8 bits : 9 bits (with extension bit appended) • Parity function: Odd, even, 0, or none • Transmit stop bit: 1 or 2 bits 20 Data Sheet U13675EJ2V1DS00 µPD705102 The configuration of the asynchronous serial interface (UART) is shown below. Figure 9-1. Block Diagram of UART Internal peripheral I/O bus 16/8 8 RXB0 Receive buffer RXB0L RXD Receive shift register 8 16/8 Mode register Status register ASIS0 Transmit shift register TXD Receive control parity check ASIM00 ASIM01 TXS0 TXS0L INTSER Transmit control parity append INTST INTSR 1/16 1/16 φ 1/2 SEL Baud rate generator Remark φ = bus clock : 48 M to 1.3 MHz: @input clock 6× : 36 M to 0.73 MHz: @input clock 8× Data Sheet U13675EJ2V1DS00 21 µPD705102 9.2 Clocked Serial Interface (CSI) The features of the clocked serial interface (CSI) are as follows: • High-speed transfer: 12.0 Mbps Max. (bus clock: 48.0 MHz) • Half duplex communication for transmission/reception (buffer is not provided) • Character length: 8 bits • External or internal serial clock selectable The configuration of the clocked serial interface (CSI) is shown below. Figure 9-2. Block Diagram of CSI Internal peripheral I/O bus 8 8 CSIM0 Mode register SO latch SIO0 Shift register SI D Q SO SCLK Serial clock control circuit Serial clock counter SEL 1/2 Interrupt control circuit Remark φ = bus clock : 48 M to 1.3 MHz: @input clock 6× : 36 M to 0.73 MHz: @input clock 8× 22 Baud rate generator SEL Data Sheet U13675EJ2V1DS00 1/2, 1/4, 1/8, 1/16, 1/32 prescaler φ INTCSI µPD705102 9.3 Baud Rate Generator (BRG) The features of the baud rate generator (BRG) are as follows: • The serial clock can be used as the baud rate generator output or the divided value of φ (bus clock) can be used as a baud rate. • The serial clock source is specified by the following registers. • In the case of UART: Specified by the SCLS0 bit of the ASIM00 register. • In the case of CSI: Specified by the CLS02 through CLS00 bits of the CSIM0 register. • The baud rate generator is shared by the UART and CSI. The configuration of the baud rate generator (BRG) is shown below. Figure 9-3. Block Configuration of Baud Rate Generator (BRG) Internal peripheral I/O bus BRG0 Compare register BRCE0 BPR00 to 02 BPRM0 Serial interface (UART/CSI) TMBRG0 Internal timer Prescaler 1/2 φ Remark φ = bus clock : 48 M to 1.3 MHz: @input clock 6× : 36 M to 0.73 MHz: @input clock 8× Data Sheet U13675EJ2V1DS00 23 µPD705102 10. TIMER/COUNTER FUNCTION The features of the timer/counter function are as follows: • Measures pulse interval and frequency and outputs programmable pulse • 16-bit measurement • Can generate pulses of various shapes (interval pulse, one-shot pulse) • Timer 1 • 16-bit timer/event counter • Source of count clock: 2 types (selected by dividing system clock, external pulse input) • Capture/compare register: × 4 • Count clear pin: TCLR • Interrupt source: 5 types • External pulse output: 2 pins • Timer 4 • 16-bit interval timer • Count clock selected by dividing system clock • Compare register: × 1 • Interrupt source: 24 1 type Data Sheet U13675EJ2V1DS00 µPD705102 The configurations of timer 1 and timer 4 are shown below. Figure 10-1. Block Configuration of Timer 1 Edge detection TCLR1 Clear & start φ /2 φ /4 φ φm φ m φ m/4 φ m/16 Note 1 TM1 (16 bits) TI Note 2 INTOV1 Edge detection INTCC10 INTCC11 INTP10 Edge detection CC10 S Q INTP11 Edge detection CC11 R Q INTP12 Edge detection CC12 S Q INTP13 Edge detection CC13 R TO10 Note 3 TO11 Note 3 Q INTCC12 INTCC13 Notes 1. Internal count clock 2. When the external count clock is TI: 6.0 MHz or lower: @input clock 6× : 4.5 MHz or lower: @input clock 8× 3. Reset priority Remarks 1. φ = bus clock: 48 M to 1.3 MHz: @input clock 6× : 36 M to 0.73 MHz: @input clock 8× 2. φm = intermediate clock Data Sheet U13675EJ2V1DS00 25 µPD705102 Figure 10-2. Block Configuration of Timer 4 φ φ /2 φ /8 φ m φ m/16 φ m/32 Note TM4 (16 bits) Clear & start CM4 Note Internal count clock Remarks 1. φ = bus clock: 48 M to 1.3 MHz: @input clock 6× : 36 M to 0.73 MHz: @input clock 8× 2. φm = intermediate clock 26 Data Sheet U13675EJ2V1DS00 INTCM4 µPD705102 11. PORT FUNCTION The port function features are listed in Table 11-1. Table 11-1. Port Functions Port Control Mode Remark PORT0 SCLK PORT1 SO PORT2 SI PORT3 RXD PORT4 TXD PORTA0 DMARQ0 PORTA PORTA1 DMAAK0 PORTA2 DMARQ1 8-bit input/output port. Input/output can be specified in 1-bit units. PORTA3 DMAAK1 PORTA4 DMARQ2 PORTA5 DMAAK2 PORTA6 DMARQ3 PORTA7 DMAAK3 PORTB0 TI PORTB1 TCLR PORTB2 INTP00 PORTB3 INTP13 PORTB4 INTP01 PORTB5 INTP11 PORTB6 INTP02 PORTB7 INTP03 PORT 5-bit input/output port. Input/output can be specified in 1-bit units. PORTB 8-bit input/output port. Input/output can be specified in 1-bit units. Port configurations are shown in Figures 11-1 to 11-6. Data Sheet U13675EJ2V1DS00 27 µPD705102 Figure 11-1. Block Diagram of PORT0 Alternate function pin I/O control Mode register PM SCLK PORT0 Selector Port register PORT Selector Selector Internal peripheral I/O bus Control mode register PC Port read enable SCLK Figure 11-2. Block Diagram of PORT1 and PORT4 Alternate function pin I/O control Mode register PM SO (PORT1), TXD (PORT4) PORT1, PORT4 Selector Port register PORT Selector Selector Internal peripheral I/O bus Control mode register PC Port read enable 28 Data Sheet U13675EJ2V1DS00 µPD705102 Figure 11-3. Block Diagram of PORT2 and PORT3 Control mode register PC Port register PORT PORT3, PORT2 Selector Internal peripheral I/O bus Mode register PM Port read enable RXD (PORT3), SI (PORT2) Figure 11-4. Block Diagram of PORTAn (n = 0, 2, 4, or 6) Control mode register PAC PORTA6, PORTA4, PORTA2, PORTA0 Port register PORTA Selector Internal peripheral I/O bus Mode register PAM Port read enable DMARQ3 to DMARQ0 Data Sheet U13675EJ2V1DS00 29 µPD705102 Figure 11-5. Block Diagram of PORTAn (n = 1, 3, 5, or 7) Aiternate function pin I/O control Mode register PAM DMAAK3 to DMAAK0 PORTA7, PORTA5, PORTA3, PORTA1 Selector Port register PORTA Selector Selector Internal peripheral I/O bus Control mode register PAC Port read enable 30 Data Sheet U13675EJ2V1DS00 µPD705102 Figure 11-6. Block Diagram of PORTB0 through PORTB7 Control mode register PBC Port register PORTB PORTB7 to PORTB0 Selector Internal peripheral I/O bus Mode register PBM Port read enable Note Note INTP03 (PORTB7), INTP02 (PORTB6), INTP11 (PORTB5), INTP01 (PORTB4), INTP13 (PORTB3), INTP00 (PORTB2), TCLR (PORTB1), TI (PORTB0) Remark ( ) indicates the corresponding port. Data Sheet U13675EJ2V1DS00 31 µPD705102 12. CLOCK GENERATION FUNCTION The clock generator generates and controls the CPU clock and bus clock that are supplied to the internal hardware units. PMC and frequencies in PLL/direct modes are shown in Table 12-1 and Table 12-2. Table 12-1. PMC and Frequency in PLL/Direct Modes Example (µPD705102-143) PLL Mode Input clock 23.8 MHz (6 times) 17.85 MHz (8 times) PMC CPU Direct Mode Bus clock CPU Bus clock ×1 142.8 MHz 47.6 MHz 11.9 MHz 3.96 MHz ×1/2 71.4 MHz 23.8 MHz 5.95 MHz 1.98 MHz ×1/4 35.7 MHz 11.9 MHz — — ×1 142.8 MHz 35.7 MHz 8.925 MHz 2.231 MHz ×1/2 71.4 MHz 17.85 MHz 4.463 MHz 1.116 MHz ×1/4 35.7 MHz 8.925 MHz — — Table 12-2. PMC and Frequency in PLL/Direct Modes Example (µPD705102-133) PLL Mode Input clock 22.2 MHz (6 times) 16.7 MHz (8 times) PMC CPU Direct Mode Bus clock CPU Bus clock ×1 133.3 MHz 44.4 MHz 11.1 MHz 3.70 MHz ×1/2 66.7 MHz 22.2 MHz 5.56 MHz 1.85 MHz ×1/4 33.3 MHz 11.1 MHz ×1 133.3 MHz 33.3 MHz 8.33 MHz 2.08 MHz ×1/2 66.7 MHz 16.7 MHz 4.17 MHz 1.04 MHz ×1/4 33.3 MHz 8.33 MHz — — — — The configuration of the clock generator is shown below. CMODE PLL synthesizer 1/2 X1 OSC X2 fB 1/6 PMC ×1 ×1/2 ×1/4 PFD VCO φ Bus clock 1/8 Phase comparator 1/2 Direct clock PMR.DPM fB: Oscillation frequency or external clock frequency φ : Bus clock OSC: Oscillator PFD: Phase Frequency Detector VCO: Voltage Controlled Oscillator PMC: Power Management Controller 32 Data Sheet U13675EJ2V1DS00 CPU clock 142.8 MHz µPD705102 13. STANDBY FUNCTION The V832 has the following two modes as standby functions: • Power management mode • Standby mode (1) Power management mode The following two power management modes can be used. According to the combination of these modes, the operating frequency is actively changed. • PLL mode This is the mode normally used. In this mode, the oscillation clock of the external input clock/OSC, which is expanded 6 or 8 times by the PLL synthesizer, is employed as the CPU clock. • Direct mode In this mode, the oscillation clock of the external input clock/OSC is employed as the CPU clock without passing through the PLL synthesizer. (2) Standby mode The following two standby modes can be used. • HALT mode In this mode, the clock generator (oscillator and PLL synthesizer) operates, but the operating clock of the CPU is stopped. The other internal peripheral functions are supplied with the clock and continue operation. By using this mode in combination with the normal mode, the power consumption of the entire system can be reduced. • STOP mode This mode stops supply of the clock to the CPU and peripheral I/O. It can reduce the power consumption much more than the HALT mode. Clock output of PLL synthesizer • In PLL mode: Operation of the PLL can be started or stopped by the PLLSS bit of the power management register (PMR). • In direct mode: The PLL always stops. Table 13-1 shows the operation of the clock generator in each mode. Data Sheet U13675EJ2V1DS00 33 µPD705102 Table 13-1. Operation of Clock Generator by Standby Control Modes Oscillator (OSC) PLL Synthesizer Power Management Mode PLL mode Standby Mode Clock Supply Clock Supply to Peripheral I/O to CPU Normal × HALT Direct mode Remark STOP ∆ Normal × HALT × STOP × × × × × × : Operates ×: Stops ∆: Operates or stops depending on setting Table 13-2. Operating Status in HALT/STOP Mode HALT ModeNote 1 Function STOP Mode Oscillator Operates PLL synthesizer OperatesNote 2 StopsNote 3 Bus clock Operates Stops CPU Stops Port output Retained Peripheral function Operates Internal data Internal data such as registers of CPU retain status before HALT mode is set. A1 to A23 Undefined High impedance when HLDAK = 0 D0 to D31 High impedance BCYST 1 CS0 to CS7 Stops High impedance when HLDAK = 0 Undefined 1 IORD, IOWR MRD, MWR, LLBEN, LUBEN, ULBEN, UUBEN LLDQM, LUDQM, ULDQM, UUDQM 0Note 4 Self refreshNote 7 RAS, CAS, WE 1Note 5 CKE 1Note 6 R/W Retained Retained HLDRQ Operates Not accepted CLKOUT, SDCLKOUT Clock output (if clock output is not disabled) 0 STOPAK 1 0 Notes 1. Each pin is in the operating status during DMA transfer. 2 Stops in the direct mode. 3. Occasionally operates in PLL mode. 4. After reset, 1 till first SDRAM access. 5. When auto refresh is not executed. 6. 0 in the power down mode. 7. When refresh is prohibited, self refresh cannot be performed. In that case, this pin retains the status before the STOP mode. 34 Data Sheet U13675EJ2V1DS00 µPD705102 14. RESET/NMI CONTROL FUNCTION The features of the reset/NMI control function are as follows: • RESET and NMI pins have a noise rejection circuit that samples the clock. • Performs forced reset, reset mask, and NMI mask processing from debug control unit Table 14-1 shows the status of the output pins during the system reset period and immediately after reset. This status is retained during the reset period. Table 14-1. Status of Output Pin Immediately after Reset Function Operating Status A1 to A23 Undefined D0 to D31 High impedance CS0 to CS7 1 BCYST 1 IORD, IOWR 1 WE, RAS, CAS, CKE 1 LLBEN, LUBEN, ULBEN, UUBEN 1 LLDQM, LUDQM, ULDQM, UUDQM 1 R/W 1 MRD, MWR 1 CLKOUT, SDCLKOUT Clock output HLDAK 1 PORT0 to PORT4Note, PORTA0 to PORTA7Note, PORTB0 to PORTB7Note High impedance DDO Undefined TRCDATA0 to TRCDATA3 Undefined STOPAK/TC 1 Note Pins with alternate functions as ports serve as port pins immediately after reset. Data Sheet U13675EJ2V1DS00 35 µPD705102 15. INSTRUCTIONS 15.1 Instruction Format The V832 uses two instruction formats: 16-bit and 32-bit. The 16-bit instructions include binary operation, control, and conditional branch instructions, while the 32-bit instructions include load/store and I/O operation instructions, instructions for handling 16 bits of immediate data, and jump-and-link instructions. Some instructions contain unused fields, which must be fixed to 0, which are provided for future use. When an instruction is actually loaded into memory, its configuration is as follows: • Low-order part of each instruction format (including bit 0) → Low-order address • High-order part of each instruction format (including bit 15 or 31) → High-order address (1) reg-reg instruction format [FORMAT I] This instruction format has a 6-bit operation code field and two general-purpose register designation fields for operand specification, giving a total length of 16 bits. 15 10 9 5 4 reg 2 opcode 0 reg 1 (2) imm-reg instruction format [FORMAT II] This instruction format has a 6-bit operation code field, a 5-bit immediate data field, and a general-purpose register designation field, giving a total length of 16 bits. 15 5 4 10 9 opcode reg 2 0 imm 5 (3) Conditional branch instruction format [FORMAT III] This instruction format has a 3-bit operation code field, a 4-bit condition code field, a 9-bit branch displacement field (bit 0 is handled as 0 and need not be specified), and a 1-bit sub-operation code, giving a total length of 16 bits. 15 9 8 13 12 opcode cond 1 0 disp 9 s: sub-opcode 36 Data Sheet U13675EJ2V1DS00 s s = 0: Bcond s = 1: ABcond µPD705102 (4) Medium-distance jump instruction format [FORMAT IV] This instruction format has a 6-bit operation code field and a 26-bit displacement field (the lowest-order bit must be 0), giving a total length of 32 bits. 15 10 9 16 0 31 opcode 0 disp 26 (5) Three-operand instruction format [FORMAT V] This instruction format has a 6-bit operation code field, two general-purpose register designation fields, and a 16-bit immediate data field, giving a total length of 32 bits. 15 5 4 10 9 opcode reg 2 16 0 31 reg 1 imm 16 (6) Load/store instruction format [FORMAT VI] This instruction format has a 6-bit operation code field, two general-purpose register designation fields, and a 16-bit displacement field, giving a total length of 32 bits. 15 5 4 10 9 opcode reg 2 16 0 31 reg 1 disp 16 (7) Extended instruction format [FORMAT VII] This instruction format has a 6-bit operation code field, two general-purpose register designation fields, and a 6-bit sub-operation code field, giving a total length of 32 bits. 15 5 4 10 9 opcode reg 2 reg 1 16 26 25 0 31 sub-opcode RFU (8) Three-register operand instruction format [FORMAT VIII] This instruction format has a 6-bit operation code field, three general-purpose register designation fields, and a 6-bit sub-operation code field, giving a total length of 32 bits. 15 5 4 10 9 opcode reg 2 reg 1 16 21 20 26 25 0 31 sub-opcode RFU reg 3 (9) No-operand instruction format [FORMAT IX] This instruction format has a 6-bit operation code field and a 1-bit sub-operation code field, giving a total length of 16 bits. 15 1 0 10 9 opcode RFU s s: sub-opcode Data Sheet U13675EJ2V1DS00 37 µPD705102 15.2 Instructions (Listed Alphabetically) The instructions are listed below in alphabetic order of their mnemonics. Explanation of list format Operand(s) Instruction ADD Format CY OV reg1, reg2 Instruction mnemonic I * * S Z * * Function Instruction Indicates how each flag changes. format —: Does not change. (See 15.1 Instruction Format) *: Changes. 0: Becomes 0. 1: Becomes 1. Abbreviations of operands Meaning Abbreviation 38 reg1 General-purpose register (used as a source register) reg2 General-purpose register (used mainly as a destination register, but in some instructions, used as a source register) reg3 General-purpose register (used mainly as a destination register, but in some instructions, used as a source register) imm× × bits of immediate data disp× ×-bit displacement regID System register number vector adr Trap handler address corresponding to trap vector Data Sheet U13675EJ2V1DS00 µPD705102 Instruction Operand(s) Format CY OV S Z Function ABC disp9 III — — — — High-speed conditional branch (if Carry) relative to PC. ABE disp9 III — — — — High-speed conditional branch (if Equal) relative to PC. ABGE disp9 III — — — — High-speed conditional branch (if Greater than or Equal) relative to PC. ABGT disp9 III — — — — High-speed conditional branch (if Greater than) relative to PC. ABH disp9 III — — — — High-speed conditional branch (if Higher) relative to PC. ABL disp9 III — — — — High-speed conditional branch (if Lower) relative to PC. ABLE disp9 III — — — — High-speed conditional branch (if Less than or Equal) relative to PC. ABLT disp9 III — — — — High-speed conditional branch (if Less than) relative to PC. ABN disp9 III — — — — High-speed conditional branch (if Negative) relative to PC. ABNC disp9 III — — — — High-speed conditional branch (if Not Carry) relative to PC. ABNE disp9 III — — — — High-speed conditional branch (if Not Equal) relative to PC. ABNH disp9 III — — — — High-speed conditional branch (if Not Higher) relative to PC. ABNL disp9 III — — — — High-speed conditional branch (if Not Lower) relative to PC. ABNV disp9 III — — — — High-speed conditional branch (if Not Overflow) relative to PC. ABNZ disp9 III — — — — High-speed conditional branch (if Not Zero) relative to PC. ABP disp9 III — — — — High-speed conditional branch (if Positive) relative to PC. ABR disp9 III — — — — High-speed unconditional branch (Always) relative to PC. ABV disp9 III — — — — High-speed conditional branch (if Overflow) relative to PC. ABZ disp9 III — — — — High-speed conditional branch (if Zero) relative to PC. ADD reg1, reg2 I * * * * Addition. reg1 is added to reg2 and the sum is written into reg2. imm5, reg2 II * * * * Addition. imm5, sign-extended to a word, is added to reg2 and the sum is written into reg2. imm16, reg1, reg2 V * * * * Addition. imm16, sign-extended to a word, is added to reg1, and the sum is written into reg2. ADDI Data Sheet U13675EJ2V1DS00 39 µPD705102 Instruction Operand(s) Format CY OV S Z Function AND reg1, reg2 I — 0 * * AND. reg2 and reg1 are ANDed and the result is written into reg2. ANDI imm16, reg1, reg2 V — 0 0 * AND. reg1 is ANDed with imm16, zero-extended to a word, and result is written into reg2. BC disp9 III — — — — Conditional branch (if Carry) relative to PC. BDLD [reg1], [reg2] VII — — — — Block transfer. 4 words of data are transferred from external memory to on-chip data RAM. BDST [reg2], [reg1] VII — — — — Block transfer. 4 words of data are transferred from on-chip data RAM to external memory. BE disp9 III — — — — Conditional branch (if Equal) relative to PC. BGE disp9 III — — — — Conditional branch (if Greater than or Equal) relative to PC. BGT disp9 III — — — — Conditional branch (if Greater than) relative to PC. BH disp9 III — — — — Conditional branch (if Higher) relative to PC. BILD [reg1], [reg2] VII — — — — Block transfer. 4 words of data are transferred from external memory to on-chip instruction RAM. BIST [reg2], [reg1] VII — — — — Block transfer. 4 words of data are transferred from on-chip instruction RAM to external memory. BL disp9 III — — — — Conditional branch (if Lower) relative to PC. BLE disp9 III — — — — Conditional branch (if Less than or Equal) relative to PC. BLT disp9 III — — — — Conditional branch (if Less than) relative to PC. BN disp9 III — — — — Conditional branch (if Negative) relative to PC. BNC disp9 III — — — — Conditional branch (if Not Carry) relative to PC. BNE disp9 III — — — — Conditional branch (if Not Equal) relative to PC. BNH disp9 III — — — — Conditional branch (if Not Higher) relative to PC. BNL disp9 III — — — — Conditional branch (if Not Lower) relative to PC. BNV disp9 III — — — — Conditional branch (if Not Overflow) relative to PC. BNZ disp9 III — — — — Conditional branch (if Not Zero) relative to PC. BP disp9 III — — — — Conditional branch (if Positive) relative to PC. BR disp9 BRKRET III — — — — Unconditional branch (Always) relative to PC. IX — — — — Return from fatal exception handling. III — — — — Conditional branch (if Overflow) relative to PC. Conditional branch (if Zero) relative to PC. BV disp9 BZ disp9 III — — — — CAXI disp16[reg1], reg2 VI * * * * 40 Inter-processor synchronization in multiprocessor system. Data Sheet U13675EJ2V1DS00 µPD705102 Instruction CMP Operand(s) Format CY OV S Z Function reg1, reg2 I * * * * Comparison. reg2 is compared with reg1 sign-extended to a word and the condition flag is set according to the result. The comparison involves subtracting reg1 from reg2. imm5, reg2 II * * * * Comparison. reg2 is compared with imm5 sign-extended to a word and the condition flag is set according to the result. The comparison involves subtracting imm5, sign-extended to a word, from reg2. II — — — — DI Disable interrupt. Maskable interrupts are disabled. DI instruction cannot disable non-maskable interrupts. DIV reg1, reg2 I — * * * Division of signed operands. reg2 is divided by reg1 (signed operands). The quotient is stored in reg2 and the remainder in r30. The division is performed so that the sign of the remainder will match that of the dividend. DIVU reg1, reg2 I — 0 * * Division of unsigned operands. reg2 is divided by reg1 (unsigned operands). The quotient is stored in reg2 and the remainder in r30. The division is performed so that the sign of the remainder will match that of the dividend. II — — — — EI Enable interrupt. Maskable interrupts are enabled. EI instruction cannot enable non-maskable interrupts. HALT IX — — — — Processor halt. The processor is placed in sleep mode. IN.B disp16[reg1], reg2 VI — — — — Port input. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit port address. A byte of data is read from the resulting port address, zero-extended to a word, then stored in reg2. IN.H disp16[reg1], reg2 VI — — — — Port input. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit port address. A halfword of data is read from the generated port address, zero-extended to a word, and stored in reg2. Bit 0 of the unsigned 32-bit port address is masked to 0. IN.W disp16[reg1], reg2 VI — — — — Port input. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit port address. A word of data is read from the resulting port address, then written into reg2. Bits 0 and 1 of the unsigned 32-bit port address are masked to 0. Data Sheet U13675EJ2V1DS00 41 µPD705102 Instruction Operand(s) Format CY OV S Z Function JAL disp26 IV — — — — Jump and link. The sum of the current PC and 4 is written into r31. disp26, sign-extended to a word, is added to the PC and the sum is set to the PC for control transfer. Bit 0 of disp26 is masked. JMP [reg1] I — — — — Indirect unconditional branch via register. Control is passed to the address designated by reg1. Bit 0 of the address is masked to 0. JR disp26 IV — — — — Unconditional branch. disp26, sign-extended to a word, is added to the current PC and control is passed to the address specified by that sum. Bit 0 of disp26 is masked to 0. LD.B disp16[reg1], reg2 VI — — — — Byte load. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit address. A byte of data is read from the generated address, sign-extended to a word, then written into reg2. LD.H disp16[reg1], reg2 VI — — — — Halfword load. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit address. A halfword of data is read from the generated address, sign-extended to a word, then written into reg2. Bit 0 of the unsigned 32-bit address is masked to 0. LD.W disp16[reg1], reg2 VI — — — — Word load. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit address. A word of data is read from the generated address, then written into reg2. Bits 0 and 1 of the unsigned 32-bit address are masked to 0. LDSR reg2, regID II MAC3 reg1, reg2, reg3 VIII * * * * Load into system register. The contents of reg2 are set in the system register identified by the system register number (regID). — — — — Saturation operation on signed 32-bit operands. reg1 and reg2 are multiplied together as signed integers and the product is added to reg3. [If no overflow has occurred:] The result is stored in reg3. [If an overflow has occurred:] The SAT bit is set. If the result is positive, the positive maximum is written into reg3; if the result is negative, the negative maximum is written into reg3. 42 Data Sheet U13675EJ2V1DS00 µPD705102 Instruction MACI Operand(s) imm16, reg1, reg2 Format V CY OV S Z — — — — Function Saturation operation on signed 32-bit operands. reg1 and imm16, sign-extended to 32 bits, are multiplied together as signed integers and the product is added to reg2 as a signed integer. [If no overflow has occurred:] The result is written into reg2. [If an overflow has occurred:] The SAT flag is set. If the result is positive, the positive maximum is written into reg2; if the result is negative, the negative maximum is written into reg2. MACT3 reg1, reg2, reg3 VIII — — — — Sum-of-products operation on signed 32-bit operands. reg1 and reg2 are multiplied together as signed integers and the high-order 32 bits of the product are added to reg3 as signed integers. [If no overflow has occurred:] The result is written into reg3. [If an overflow has occurred:] The SAT flag is set. If the result is positive, the positive maximum is written into reg3; if the result is negative, the negative maximum is written into reg3. MAX3 reg1, reg2, reg3 VIII — — — — Maximum. reg2 and reg1 are compared as signed integers. The larger value is written into reg3. MIN3 reg1, reg2, reg3 VIII — — — — Minimum. reg2 and reg1 are compared as signed integers. The smaller value is written into reg3. MOV reg1, reg2, I — — — — Data transfer. reg1 is copied to reg2 for imm5, reg2 II — — — — Data transfer. imm5, sign-extended to a word, is copied into reg2 for data transfer. MOVEA imm16, reg1, reg2 V — — — — Addition. The high-order 16 bits (imm16), sign-extended to a word, are added to reg1 and the sum is written into reg2. MOVHI imm16, reg1, reg2 V — — — — Addition. A word of data consisting of the highorder 16 bits (imm16) and low-order 16 bits (0) is added to reg1 and the sum is written into reg2. MUL reg1, reg2 I — * * * Multiplication of signed operands. reg2 and reg1 are multiplied together as signed values. The high-order 32 bits of the product (double word) are written into r30 and low-order 32 bits are written into reg2. MUL3 reg1, reg2, reg3 VIII — — — — Multiplication of signed 32-bit operands. reg2 and reg1 are multiplied together as signed integers. The high-order 32 bits of the product are written into reg3. data transfer. Data Sheet U13675EJ2V1DS00 43 µPD705102 Instruction MULI Operand(s) imm16, reg1, reg2 Format V CY OV S Z — — — — Function Saturation multiplication of signed 32-bit operands. reg1 and imm16, sign-extended to 32 bits, are multiplied together as signed integers. [If no overflow has occurred:] The result is written into reg2. [If an overflow has occurred:] The SAT flag is set. If the result is positive, the positive maximum is written into reg2; if the result is negative, the negative maximum is written into reg2. MULT3 reg1, reg2, reg3 VIII — — — — MULU reg1, reg2 I — * * * III — — — — NOP Saturation multiplication of signed 32-bit operands. reg1 and reg2 are multiplied together as signed integers. The high-order 32 bits of the product are written into reg3. Multiplication of unsigned operands. reg1 and reg2 are multiplied together as unsigned values. The high-order 32 bits of the product (double word) are written into r30 and the low-order 32 bits are written into reg2. No operation. NOT reg1, reg2 I — 0 * * NOT. The NOT (one’s complement) of reg1 is taken and written into reg2. OR reg1, reg2 I — 0 * * OR. The OR of reg2 and reg1 is taken and written into reg2. ORI imm16, reg1, reg2 V — 0 * * OR. The OR of reg1 and imm16, zeroextended to a word, is taken and written into OUT.B reg2, disp16[reg1] VI — — — — Port output. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit port address. The low-order one byte of the data in reg2 is output to the resulting port address. OUT.H reg2, disp16[reg1] VI — — — — Port output. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit port address. The low-order two bytes of the data in reg2 are output to the resulting port address. Bit 0 of the unsigned 32-bit port address is masked to 0. OUT.W reg2, disp16[reg1] VI — — — — Port output. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit port address. The word of data in reg2 is output to the produced port address. Bits 0 and 1 of the unsigned 32-bit port address are masked to 0. IX * * * * Return from trap/interrupt handling routine. The return PC and PSW are read from the system registers so that program execution will return from the trap or interrupt handling routine. reg2. RETI 44 Data Sheet U13675EJ2V1DS00 µPD705102 Instruction SAR SATADD3 Operand(s) Format CY OV S Z Function reg1, reg2 I * 0 * * Arithmetic right shift. reg2 is arithmetically shifted to the right by the displacement specified by the low-order five bits of reg1 (MSB value is copied to the MSB in sequence). The result is written into reg2. imm5, reg2 II * 0 * * Arithmetic right shift. reg2 is arithmetically shifted to the right by the displacement specified by imm5, zero-extended to a word. The result is written into reg2. reg1, reg2, reg3 VIII * * * * Saturation addition. reg1 and reg2 are added together as signed integers. [If no overflow has occurred:] The result is written into reg3. [If an overflow has occurred:] The SAT flag is set. If the result is positive, the positive maximum is written into reg3; if the result is negative, the negative maximum is written into reg3. SATSUB3 reg1, reg2, reg3 VIII * * * * Saturation subtraction. reg1 is subtracted from reg2 as signed integers. [If no overflow has occurred:] The result is written into reg3. [If an overflow has occurred:] The SAT flag is set. If the result is positive, the positive maximum is written into reg3; if the result is negative, the negative maximum is written into reg3. SETF imm5, reg2 II — — — — Set flag condition. reg2 is set to 1 if the condition specified by the low-order four bits of imm5 matches the condition flag; otherwise it is SHL reg1, reg2 I * 0 * * Logical left shift. reg2 is logically shifted to the left (0 is put on the LSB) by the displacement specified by the low-order five bits of reg1. The result is written into reg2. imm5, reg2 II * 0 * * Logical left shift. reg2 is logically shifted to the left by the displacement specified by imm5, zero-extended to a word. The result is written into reg2. reg1, reg2, reg3 VIII — — — — Left shift of concatenation. The 64 bits consisting of reg3 (high order) and reg2 (low order) are logically shifted to the left by the displacement specified by the low-order five bits of reg1. The high-order 32 bits of the result are written into reg3. set to 0. SHLD3 Data Sheet U13675EJ2V1DS00 45 µPD705102 Instruction SHR Operand(s) Format CY OV S Z Function reg1, reg2 I * 0 * * Logical right shift. reg2 is logically shifted to the right by the displacement specified by the low-order five bits of reg1 (0 is put on the MSB). The result is written into reg2. imm5, reg2 II * 0 * * Logical right shift. reg2 is logically shifted to the right by the displacement specified by imm5, zero-extended to a word. The result is written into reg2. SHRD3 reg1, reg2, reg3 VIII — — — — Right shift of concatenation. The 64 bits consisting of reg3 (high order) and reg2 (low order) are logically shifted to the right by the displacement specified by the low-order five bits of reg1. The low-order 32 bits of the result are written into reg3. ST.B reg2, disp16[reg1] VI — — — — Byte store. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit address. The low-order one byte of data in reg2 is stored at the resulting address. ST.H reg2, disp16[reg1] VI — — — — Halfword store. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit address. The low-order two bytes of the data in reg2 are stored at the resulting address. Bit 0 of the unsigned 32-bit address is masked to 0. ST.W reg2, disp16[reg1] VI — — — — Word store. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit address. The word of data in reg2 is stored at the resulting address. Bits 0 and 1 of the unsigned 32-bit address are masked to 0. STBY IX — — — — Processor stop. The processor is placed in stop mode. STSR regID, reg2 II — — — — System register store. The contents of the system register identified by the system register number (regID) are set in reg2. SUB reg1, reg2 I * * * * Subtraction. reg1 is subtracted from reg2. The difference is written into reg2. TRAP vector II — — — — 46 Software trap. The return PC and PSW are saved in the system registers: PSW.EP = 1 → Save in FEPC, FEPSW PSW.EP = 0 → Save in EIPC, EIPSW The exception code is set in the ECR: PSW.EP = 1 → Set in FECC PSW.EP = 0 → Set in EICC PSW flags are set: PSW.EP = 1 → Set NP and ID PSW.EP = 0 → Set EP and ID Program execution jumps to the trap handler address corresponding to the trap vector (0-31) specified by vector and begins exception handling. Data Sheet U13675EJ2V1DS00 µPD705102 Instruction Operand(s) Format CY OV S Z Function XOR reg1, reg2 I — 0 * * Exclusive OR. The exclusive OR of reg2 and reg1 is taken and written into reg2. XORI imm16, reg1, reg2 V — 0 * * Exclusive OR. The exclusive OR of reg1 and imm16, zero-extended to a word, is taken and written into reg2. Data Sheet U13675EJ2V1DS00 47 µPD705102 16. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Ratings Unit 3.3-V operation supply voltage Parameter VDDO Symbol Conditions –0.5 to +4.0 V 2.5-V operation supply voltage VDDI –0.5 to +3.6 V VDDPLL Input voltageNote VI Clock input voltage VK Operating ambient temperature TA Storage temperature –0.5 to +3.6 V VDDO ≥ 3.7 V –0.5 to +4.0 V VDDO < 3.7 V –0.5 to VDDO + 0.3 –0.5 to VDDO + 0.3 V µPD705102-143 CPU core frequency ≤ 143 MHz –40 to +85 °C CPU core frequency ≤ 144 MHz –40 to +70 °C µPD705102-133 CPU core frequency ≤ 133 MHz –40 to +85 °C –65 to +150 °C Tstg Note Includes output pins. Cautions 1. Do not directly connect the output (or input/output) pins of an IC device to each other, and do not connect them directly to the VDD, VCC or GND. However, these restrictions do not apply to the high-impedance pins of an external circuit, whose timing has been specifically designed to avoid output collision. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. For IC products, normal operation and quality are guaranteed only when the ratings and conditions described under the DC and AC characteristics are satisfied. Operating Conditions Parameter Symbol Conditions MIN. MAX. Unit 3.3-V operation supply voltage VDDO 3.0 3.6 V 2.5-V operation supply voltage VDDI 2.3 2.7 V Operating ambient temperature TA µPD705102-143 CPU core frequency ≤ 143 MHz –40 +85 °C CPU core frequency ≤ 144 MHz –40 +70 °C µPD705102-133 CPU core frequency ≤ 133 MHz –40 +85 °C Caution V832 has two types of power supply, and there are no restrictions on the order that the voltage is to be applied. However, be sure not to keep a status whereby only one power supply is applied voltage for 1 second or more. 48 Data Sheet U13675EJ2V1DS00 µPD705102 DC Characteristics (VDDO = 3.0 to 3.6 V, VDDI = 2.3 to 2.7 V) µPD705102-143 (CPU core frequency ≤ 143 MHz): TA = –40 to +85°C µPD705102-143 (CPU core frequency ≤ 144 MHz): TA = –40 to +70°C TA = –40 to +85°C µPD705102-133: Parameter Symbol Clock input voltage, low Conditions MIN. TYP. MAX. Unit V VKL Note 1 –0.5 +0.2 VDDO Clock input voltage, high VKH Note 1 0.8 VDDO VDDO + 0.3 V Input voltage, low VIL –0.5 +0.6 V Input voltage, high VIH 2.0 VDDO + 0.3 V Schmitt input voltage, low VSL Note 2 –0.5 +0.2 VDDO V Schmitt input voltage, high VSH Note 2 0.8 VDDO VDDO + 0.3 V Output voltage, low VOL IOL = 3.2 mA 0.4 V Output voltage, high VOH IOH = –400 µA Input leakage current, low ILIL VIN = 0 V –10 µA Input leakage current, high ILIH VIN = VDDO 10 µA Output leakage current, low ILOL VO = 0 V –10 µA Output leakage current, high ILOH VO = VDDO Supply currentNote 3 IDDI In normal operation Clock division ratio 1/1 115 (PLL mode) Clock division ratio 1/2 60 mA Clock division ratio 1/4 33 mA In normal operation Clock division ratio 1/1 15 mA (Direct mode) 7.5 2.5 V 3.3 V IDDO 0.85 VDDO Clock division ratio 1/2 V 10 µA 160 mA mA In HALT mode 20 29 mA In STOP modeNote 4 25 450 µA In normal operation Clock division ratio 1/1 19 28 mA (PLL mode) Clock division ratio 1/2 10 mA Clock division ratio 1/4 6 mA In normal operation Clock division ratio 1/1 4 mA (Direct mode) Clock division ratio 1/2 3 mA In HALT mode 12 20 mA In STOP modeNote 4 5 10 µA Notes 1. X2 pin, DCK pin, and SCLK pin at external clock input 2. PORT0/SCLK, PORT2/SI, PORT3/RXD 3. Supply current at input clock: 17.85 MHz with output pins open, PLL 8× 4. External clock mode when clock input is stopped. Capacitance Parameter Symbol Input capacitance CI I/O capacitance CIO Conditions MIN. fC = 1 MHz MAX. Unit 10 pF 10 pF Remark These parameters are sample values, not the value actually measured. Data Sheet U13675EJ2V1DS00 49 µPD705102 AC Characteristics (VDDO = 3.0 to 3.6 V, VDDI = 2.3 to 2.7 V, CL = 50 pF) µPD705102-143 (CPU core frequency ≤ 143 MHz): TA = –40 to +85°C µPD705102-143 (CPU core frequency ≤ 144 MHz): TA = –40 to +70°C TA = –40 to +85°C µPD705102-133 : AC test input waveform VDDO 2.0 V 0.5 VDDO Test point 0.6 V 0V 4 ns AC test output waveform (a) CS0, CS1, WE, RAS, UUDQM, ULDQM, LUDQM, LLDQM, CKE, CAS, SDCLKOUT, CLKOUT, A1 to A23, D0 to D31 VDDO 0.85 VDDO 0.5 VDDO Test point 0.4 V 0V (b) Other than above (a) VDDO 0.85 VDDO 1.4 V Test point 0.4 V 0V Test load V832 output pin CL = 50 pF 50 Data Sheet U13675EJ2V1DS00 µPD705102 (1) Clock input (X2) timing (when external clock input used) • µPD705102-143 Parameter Symbol Conditions PLL Magnification ×6 mode External clock cycle <1> tCYX MAX. MIN. MAX. 42 60 56 80 ns 60 ns 80 ns 60 ns 45 Note 3 41.6 60 Note 4 <2> tXXH External clock low-level time <3> tXXL ×8 mode MIN. Note 1 Note 2 External clock high-level time Unit 55.5 45 Note 1 16 23 ns Note 3 15.8 22.75 ns Note 1 16 23 ns Note 3 15.8 22.75 ns External clock rise time <4> tXR 5 5 ns External clock fall time <5> tXF 5 5 ns Notes 1. TA = –40 to +85°C, when other than 1/4 is selected as the division ratio of the input clock (CPU core frequency (when defaulted) = 100 to 143 MHz) 2. TA = –40 to +85°C, when 1/4 is selected as the division ratio of the input clock (CPU core frequency = 33.3 to 35.8 MHz) 3. TA = –40 to +70°C, when other than 1/4 is selected as the division ratio of the input clock (CPU core frequency (when defaulted) = 100 to 144 MHz) 4. TA = –40 to +70°C, when 1/4 is selected as the division ratio of the input clock (CPU core frequency = 33.3 to 36 MHz) Remark The stability of the input clock is 0.1% of tCYX or lower. • µPD705102-133 Parameter Symbol Conditions PLL Magnification ×6 mode External clock cycle <1> tCYX Unit ×8 mode MIN. MAX. MIN. MAX. 45 60 60 80 ns 60 ns Note 1 Note 2 45 External clock high-level time <2> tXXH 17.5 25 ns External clock low-level time <3> tXXL 17.5 External clock rise time <4> tXR 5 5 ns External clock fall time <5> tXF 5 5 ns 25 ns Notes 1. TA = –40 to +85°C, when other than 1/4 is selected as the division ratio of the input clock (CPU core frequency (when defaulted) = 100 to 133 MHz) 2. TA = –40 to +85°C, when 1/4 is selected as the division ratio of the input clock (CPU core frequency = 33.3 MHz) Remark The stability of the input clock is 0.1% of tCYX or lower. <1> <5> <2> <4> 0.8 VDDO X2 (input) 1.4 V 0.2 VDDO <3> Data Sheet U13675EJ2V1DS00 51 µPD705102 (2) Clock output timing (CLKOUT, SDCLKOUT) Parameter Symbol Conditions PLL Magnification ×6 mode MIN. External clock cycle <6> tCYK Unit ×8 mode MAX. MIN. MAX. Note 1 21 28 ns Note 2 20.8 27.75 ns Note 3 22.5 30 ns tCYK/2 – 5 ns External clock high-level time <7> tKKH tCYK/2 – 5 External clock low-level time <8> tKKL tCYK/2 – 5 External clock rise time <9> tKR 5 5 ns External clock fall time <10> tKF 5 5 ns tCYK/2 – 5 ns Notes 1. µPD705102-143, TA = –40 to +85°C 2. µPD705102-143, TA = –40 to +70°C 3. µPD705102-133, TA = –40 to +85°C <6> <10> <7> 0.8 VDDO 1.4 V CLKOUT (output) SDCLKOUT (output) 0.2 VDDO <8> 52 Data Sheet U13675EJ2V1DS00 <9> µPD705102 (3) Reset timing Parameter Symbol Conditions RESET hold time (from VDDI VALID) <11> tHVR RESET setup time (to CLKOUT↑) MIN. MAX. Unit 2 µs <12> tSRK 7 ns RESET hold time (from CLKOUT↑) <13> tHKR 7 ns RESET pulse low-level width tWRL 20 ms Note 2 10 ms Note 3 15 × tCYX ns <14> Note 1 Notes 1. At power on or when returned from STOP mode, and the internal clock is generated. 2. At power on or when returned from STOP mode, and the external clock is generated, after clock has stabilized. 3. When clock has stabilized under conditions other than Notes 1 and 2. Remark It is not necessary to satisfy tSRK and tHKR if reset during the period of tHVR. In such a case, however, the reset acknowledge timing may be shifted. VDDI 0.9 VDDI <11> <12> CLKOUT (output) <13> <12> RESET (input) <14> Data Sheet U13675EJ2V1DS00 53 µPD705102 (4) SDRAM access timing MIN. MAX. Unit BCYST delay time (from SDCLKOUT↑) Parameter <15> Symbol tDKBC Conditions 2 12.5 ns Address delay time (from SDCLKOUT↑) <16> tDKA 2 12.5 ns RAS delay time (from SDCLKOUT↑) <17> tDKRAS 2 12.5 ns CAS delay time (from SDCLKOUT↑) <18> tDKCAS 2 12.5 ns CS0, CS1 delay time (from SDCLKOUT↑) <19> tDKCS 2 12.5 ns WE delay time (from SDCLKOUT↑) <20> tDKWE 2 12.5 ns R/W delay time (from SDCLKOUT↑) <21> tDKRW 2 12.5 ns ××DQM delay time (from SDCLKOUT↑) <22> tDKDQM 2 12.5 ns 12.5 ns CKE delay time (from SDCLKOUT↑) <23> tDKCKE 2 Data input setup time (SDRAM read, to SDCLKOUT↑) <24> tSDRMK 5 ns Data input hold time (SDRAM read, from SDCLKOUT↑) <25> tHKDRM 2 ns Data output delay time <26> tDKDT 2 12.5 ns Data output delay time (from float, from SDCLKOUT↑) <27> tLZKDT 2 12.5 ns Data float delay time (from SDCLKOUT↑) <28> tHZKDT 3 20 ns (from active, from SDCLKOUT↑) Remark ××DQM: LLDQM, LUDQM, ULDQM, UUDQM 54 Data Sheet U13675EJ2V1DS00 µPD705102 SDRAM single read cycle (off-page) (TRP = 0, TRCD = 0): with 32-bit data bus Tpr Tac Tr1 Tra2 Tra3 Tri Ti SDCLKOUT (output) Command PRE ACT <15> RD <15> <15> <15> BCYST (output) CKE (output) H <19> <19> <19> CS0, CS1 (output) <17> <17> <18> <18> <17> RAS (output) <18> <18> CAS (output) <20> <20> <20> WE (output) <16> <16> <16> <16> <16> <16> <16> <16> <16> BA Bank address (output) <16> <16> <16> <16> A12 (output) RA RA Address (output) CA <24> <25> D0 to D31 (input) <21> <21> R/W (output) <22> <22> ××DQM (output) Remarks 1. The broken lines indicate high impedance. 2. ××DQM: LLDQM, LUDQM, ULDQM, UUDQM Data Sheet U13675EJ2V1DS00 55 µPD705102 SDRAM single read cycle (on-page): with 32-bit data bus Tr1s Tra2 Tra3 Tri Ti SDCLKOUT (output) Command RD <15> <15> <15> BCYST (output) CKE (output) H <19> <19> <19> CS0, CS1 (output) <17> RAS (output) <18> <18> <18> CAS (output) <20> <20> WE (output) <16> <16> <16> BA Bank address (output) <16> <16> <16> A12 (output) <16> <16> <16> CA Address (output) <24> <25> D0 to D31 (input) <21> <21> R/W (output) <22> <22> ××DQM (output) Remarks 1. The broken lines indicate high impedance. 2. ××DQM: LLDQM, LUDQM, ULDQM, UUDQM 56 Data Sheet U13675EJ2V1DS00 µPD705102 SDRAM burst read cycle (off-page) (TRP = 0, TRCD = 0): with 32-bit data bus Tpr Tac Tr1 Trb2 Trb3 Trb4 Trb5 Trb6 Tri Ti SDCLKOUT (output) PRE Command ACT <15> RD RD RD RD <15> <15> <15> BCYST (output) CKE (output) H <19> <19> <19> CS0, CS1 (output) <17> <17> <18> <18> <17> RAS (output) <18> <18> CAS (output) <20> <20> <20> WE (output) <16> <16> <16> <16> <16> <16> <16> BA Bank address (output) <16> <16> A12 (output) <16> RA <16> <16> <16> RA A1 to A23 (output) <16> CA <16> CA <16> CA CA <24> <25> 1 D0 to D31 (input) <21> <24> <25> 2 <24> <25> 3 4 <24> <25> <21> R/W (output) ××DQM (output) L Remarks 1. The broken lines indicate high impedance. 2. ××DQM: LLDQM, LUDQM, ULDQM, UUDQM Data Sheet U13675EJ2V1DS00 57 µPD705102 SDRAM burst read cycle (on-page): with 32-bit data bus Tr1s Trb2 Trb3 Trb4 Trb5 Trb6 Tri Ti SDCLKOUT (output) Command RD RD RD RD <15> <15> <15> BCYST (output) CKE (output) H <19> <19> <19> CS0, CS1 (output) <17> RAS (output) <18> <18> <18> CAS (output) <20> <20> WE (output) <16> <16> Bank address (output) <16> BA <16> <16> <16> A12 (output) <16> Address (output) <16> CA <16> CA <16> CA <16> <16> CA <24> <25> <24> <25> D0 to D31 (input) <21> <24> <25> R/W (output) ××DQM (output) L Remarks 1. The broken lines indicate high impedance. 2. ××DQM: LLDQM, LUDQM, ULDQM, UUDQM 58 Data Sheet U13675EJ2V1DS00 <24> <25> <21> µPD705102 SDRAM single write cycle (off-page) (TRP = 0, TRCD = 0): with 32-bit data bus Tpr Tac Tw1 Twi SDCLKOUT (output) Command PRE ACT WR <15> <15> <15> <15> BCYST (output) CKE (output) H <19> <19> CS0, CS1 (output) <17> <17> <17> RAS (output) <18> <18> <18> <18> CAS (output) <20> <20> <20> <20> <20> WE (output) <16> <16> <16> BA Bank address (output) <16> <16> <16> <16> <16> A12 (output) RA <16> <16> <16> RA Address (output) <16> <16> CA <27> <28> D0 to D31 (output) <21> <21> R/W (output) <22> <22> ××DQM (output) Remarks 1. The broken lines indicate high impedance. 2. ××DQM: LLDQM, LUDQM, ULDQM, UUDQM Data Sheet U13675EJ2V1DS00 59 µPD705102 SDRAM single write cycle (on-page): with 32-bit data bus Tw1s Twi SDCLKOUT (output) WR Command <15> <15> <15> BCYST (output) CKE (output) H <19> <19> CS0, CS1 (output) <17> RAS (output) <18> <18> <20> <20> <16> <16> <18> CAS (output) <20> WE (output) <16> BA Bank address (output) <16> <16> <16> <16> <16> A12 (output) <16> CA Address (output) <28> <27> D0 to D31 (output) <21> <21> R/W (output) <22> <22> ××DQM (output) Remarks 1. The broken lines indicate high impedance. 2. ××DQM: LLDQM, LUDQM, ULDQM, UUDQM 60 Data Sheet U13675EJ2V1DS00 µPD705102 SDRAM burst write cycle (off-page) (TRP = 0, TRCD = 0): with 32-bit data bus Tpr Tac Tw1 Tw3 Tw2 Tw4 SDCLKOUT (output) PRE Command ACT WR <15> WR WR WR <15> <15> BCYST (output) CKE (output) H <19> <19> CS0, CS1 (output) <17> <17> <17> <18> <18> <18> <20> <20> RAS (output) CAS (output) <20> <20> WE (output) <16> <16> Bank address (output) BA <16> <16> A12 (output) <16> <16> RA <16> <16> <16> <16> <16> <16> <16> Address (output) RA CA CA <27> D0 to D31 (output) CA <26> 1 <21> CA <26> 2 <28> <26> 3 4 <21> R/W (output) ××DQM (output) L Remarks 1. The broken lines indicate high impedance. 2. ××DQM: LLDQM, LUDQM, ULDQM, UUDQM Data Sheet U13675EJ2V1DS00 61 µPD705102 SDRAM burst write cycle (on-page): with 32-bit data bus Tw1s Twr2 Tw3 Tw4 SDCLKOUT (output) Command WR WR WR WR <15> <15> <19> <19> BCYST (output) CKE (output) H CS0, CS1 (output) <17> RAS (output) <18> <18> CAS (output) <20> <20> <16> <16> WE (output) BA Bank address (output) <16> <16> A12 (output) <16> <16> CA Address (output) <27> <16> CA <26> <16> CA <26> <16> CA <26> <28> D0 to D31 (output) <21> R/W (output) ××DQM (output) L Remarks 1. The broken lines indicate high impedance. 2. ××DQM: LLDQM, LUDQM, ULDQM, UUDQM 62 Data Sheet U13675EJ2V1DS00 <21> µPD705102 Auto refresh cycle (TRP = 0): with 32-bit data bus Tap Trf SDCLKOUT (output) PALL Command REF <15> BCYST (output) CKE (output) H <19> <19> <17> <17> CS0, CS1 (output) RAS (output) <18> <18> <18> <20> <20> <20> CAS (output) WE (output) <16> <16> Bank address (output) <16> <16> <16> A12 (output) <16> <16> Address (output) ××DQM (output) L Remark ××DQM: LLDQM, LUDQM, ULDQM, UUDQM Data Sheet U13675EJ2V1DS00 63 µPD705102 Self refresh cycle (TRP = 0): with 32-bit data bus Tap Tsr Tsri Tsri SDCLKOUT (output) Command PALL SELF <15> <15> BCYST (output) <23> <23> CKE (output) <19> <19> <19> CS0, CS1 (output) <17> <17> <17> RAS (output) <18> <18> <18> <18> CAS (output) <20> <20> <20> WE (output) <16> <16> Bank address (output) <16> BA <16> <16> <16> A12 (output) <16> <16> Address (output) ××DQM (output) L Remark ××DQM: LLDQM, LUDQM, ULDQM, UUDQM 64 Data Sheet U13675EJ2V1DS00 <16> µPD705102 (5) Access timing of SRAM, Page-ROM and I/O MIN. MAX. Unit BCYST delay time (from CLKOUT↑) Parameter <15> tDKBC Symbol Condition 2 12.5 ns Address delay time (from CLKOUT↑) <16> tDKA 2 12.5 ns CSnNote delay time (from CLKOUT↑) <19> tDKCS 2 12.5 ns R/W delay time (from CLKOUT↑) <21> tDKRW 2 12.5 ns Data output delay time <26> tDKDT 2 12.5 ns Data output delay time (from float, from CLKOUT↑) <27> tLZKDT 2 12.5 ns Data float delay time (from CLKOUT↑) <28> tHZKDT 3 20 ns IORD output delay time (from CLKOUT↓) <29> tDKRD 2 12.5 ns MRD output delay time (from CLKOUT↓) <30> tDKMRD 2 12.5 ns IOWR output delay time (from CLKOUT↓) <31> tDKWR 2 12.5 ns MWR output delay time (from CLKOUT↓) <32> tDKMWR 2 12.5 ns ××BEN delay time (from CLKOUT↓) <33> tDKBEN 2 12.5 ns Data input setup time (to CLKOUT↓) <34> tSDTK 5 ns Data input hold time (from CLKOUT↓) <35> tHKDT 2 ns READY setup time (to CLKOUT↑) <36> tSRYK 7 ns READY hold time (from CLKOUT↑) <37> tHKRY 3 ns (from active, from CLKOUT↑) Note CSn indicates CS1 through CS7. Depending on the n value, a different area is used. n = 1 to 7: When SRAM (ROM) is selected n = 7: When Page-ROM is selected n = 3 to 6: When I/O is selected Remark ××BEN: LLBEN, LUBEN, ULBEN, UUBEN Data Sheet U13675EJ2V1DS00 65 µPD705102 SRAM (ROM), Page-ROM single read cycle I/O read timing Ta Ts Ts Ti CLKOUT (output) <15> <15> <15> BCYST (output) <16> <16> A1 to A23 (output) <19> <19> CSn (output) <33> <33> ××BEN (output) <29> <29> IORD (output) <30> <30> MRD (output) <34> <35> D0 to D31 (input) <21> <21> R/W (output) <36> <37> <36> <37> READY (input) Remarks 1. The broken lines indicate high impedance. 2. n = 1 to 7 3. ××BEN: LLBEN, LUBEN, ULBEN, UUBEN 66 Data Sheet U13675EJ2V1DS00 µPD705102 SRAM (ROM) single write cycle I/O write timing Ta Ts Ts CLKOUT (output) <15> <15> <15> BCYST (output) <16> <16> <19> <19> A1 to A23 (output) CSn (output) <33> <33> <31> <31> <32> <32> ××BEN (output) IOWR (output) MWR (output) <26> <26> D0 to D31 (output) <27> <28> D0 to D31 (output) <21> <21> R/W (output) <36> <37> <36> <37> READY (input) Remarks 1. The broken lines indicate high impedance. 2. n = 1 to 7 3. ××BEN: LLBEN, LUBEN, ULBEN, UUBEN Data Sheet U13675EJ2V1DS00 67 µPD705102 Page-ROM burst read cycle (with 32-bit data bus) Ta Tb1 Tb1 Ta2 Tb2 Ta3 Tb3 Ta4 Ts Ti CLKOUT (output) <15> <15> <15> <15> <15> <15> <15> <15> <15> BCYST (output) <16> <16> <16> <16> <16> A1 to A23 (output) <19> <19> <19> CS7 (output) ××BEN (output) H <30> <30> <30> MRD (output) <34><35> <34><35> <34><35> <34> <35> D0 to D31 (input) <21> <21> R/W (output) <36> <37><36> <37> <36> <37> <36> <37> READY (input) Remarks 1. The broken lines indicate high impedance. 2. ××BEN: LLBEN, LUBEN, ULBEN, UUBEN 68 Data Sheet U13675EJ2V1DS00 <36> <37> µPD705102 (6) Interrupt timing Parameter NMI setup time (to CLKOUT↑) Symbol Conditions MIN. MAX. Unit <38> tSNK 5 ns NMI hold time (from CLKOUT↑) <39> tHKN 7 ns INTP×× setup time (to CLKOUT↓) <40> tSIK 7 ns INTP×× hold time (from CLKOUT↓) <41> tHKI 3 ns NMI high-level time <42> tNMH 5T + 12 ns NMI low-level time <43> tNML 5T + 12 ns Remarks 1. T = tCYK (external clock cycle) 2. Even if tSNK and tHKN are set to other than the above range, the NMI interrupt can be acknowledged, however, in this case NMI acknowledge timing may be delayed. CLKOUT (output) <38> <39> <39> <38> 2.0 V NMI (input) 0.5 VDDO 0.6 V <43> <42> <40> <41> INTP00 to INTP03, INTP10 to INTP13 (input) Data Sheet U13675EJ2V1DS00 69 µPD705102 (7) Bus hold timing MIN. MAX. Unit Data active delay time (from CLKOUT↑) Parameter <27> tLZKDT Symbol 2 12.5 ns Data float delay time (from CLKOUT↑) <28> tHZKDT 3 20 ns HLDRQ input setup time (to CLKOUT↑) <44> tSHQK 7 ns HLDRQ hold time (from CLKOUT↑) <45> tHKHQ 3 ns HLDAK output delay time (from CLKOUT↑) <46> tDKHA 2 12.5 ns Address float delay time (from CLKOUT↑) <47> tHZKA 3 20 ns Address active delay time (from CLKOUT↑) <48> tLZKA 2 12.5 ns Ti Tih Conditions Th Th Th Th Ti CLKOUT (output) <44> <44> <45> HLDRQ (input) <46> <46> <47> <48> <47> <48> <47> <48> <47> <48> HLDAK (output) Note 1 (output) Note 2 (output) Note 3 (output) A1 to A23 (output) <27> <28> D0 to D31 (output) Notes 1. BCYST, WE, CS0 to CS7, RAS, CAS, MRD, MWR, CKE 2. R/W, LLBEN, LUBEN, ULBEN, UUBEN 3. LLDQM, LUDQM, ULDQM, UUDQM Remark The broken lines indicate high impedance. 70 Data Sheet U13675EJ2V1DS00 µPD705102 (8) DMA timing Parameter Symbol Conditions MIN. MAX. Unit DMARQ input setup time (to CLKOUT↑) <49> tSDQK 7 ns DMARQ hold time (from CLKOUT↑) <50> tHKDQ 3 DMAAK output delay time <51> tDKDAK 2 12.5 ns TC output delay time <52> tDKTC 2 12.5 ns ns CLKOUT (output) <49> <50> <49> DMARQ0 to DMARQ3 (input) <51> <51> DMAAK0 to DMAAK3 (output) <52> <52> TC (output) Data Sheet U13675EJ2V1DS00 71 µPD705102 (9) CSI timing (a) SCLK input mode Parameter Symbol SCLK cycle Conditions MIN. MAX. Unit <53> tCYSI 4T ns SCLK high-level time <54> tSIH tCYSI/2 – 10 ns SCLK low-level time <55> tSIL tCYSI/2 – 10 ns SCLK rise time <56> tSIR 10 ns 10 ns SCLK fall time <57> tSIF SI input setup time (to SCLK↑) <58> tSDTS 21 ns SI input hold time (from SCLK↑) <59> tHSDT 21 ns SO output delay time (from SCLK↓) <60> tDSDT 2 21 Remark T = tCYK (external clock cycle) <53> <54> <56> <55> 0.8 VDDO SCLK (input) 0.5 VDDO 0.2 VDDO <58> SI (input) <60> SO (output) 72 Data Sheet U13675EJ2V1DS00 <59> <57> ns µPD705102 (b) SCLK output mode Parameter SCLK cycle Symbol Conditions MIN. MAX. Unit <61> tCYSO 4T ns SCLK high-level time <62> tSOH tCYSO/2 – 10 ns SCLK low-level time <63> tSOL tCYSO/2 – 10 ns SCLK rise time <64> tSOR 10 ns 10 ns SCLK fall time <65> tSOF SI input setup time (to SCLK↑) <66> tSDTS 21 ns SI input hold time (from SCLK↑) <67> tHSDT 21 ns SO output delay time (from SCLK↓) <68> tDSDT 2 21 ns Remark T = tCYK (external clock cycle) <61> <62> SCLK (output) <64> <63> <65> 0.8 VDDO 0.5 VDDO 0.2 VDDO <66> <67> SI (input) <68> SO (output) Data Sheet U13675EJ2V1DS00 73 µPD705102 (10) Timer timing Parameter Symbol TI clock cycle Conditions MIN. MAX. Unit <69> tCYT 8T ns TI clock high-level time <70> tTIH 4T + 10 ns TI clock low-level time <71> tTIL 4T + 10 ns TI clock rise time <72> tTR 10 10 ns TI clock fall time <73> tTF TCLR clock high-level time <74> tCLH 4T + 10 ns TCLR clock low-level time <75> tCLL 4T + 10 ns Remark T = tCYK (external clock cycle) <69> <70> <71> 2.0 V TI (input) 0.5 VDDO 0.6 V <74> <75> 2.0 V TCLR (input) 0.6 V 74 Data Sheet U13675EJ2V1DS00 <72> <73> ns µPD705102 17. PACKAGE DRAWING 160 PIN PLASTIC LQFP (FINE PITCH) ( 24) A B 81 80 120 121 detail of lead end C D S Q 41 40 160 1 F G R H I M J P K N M L NOTE ITEM Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. A MILLIMETERS INCHES 26.0±0.2 1.024 +0.008 –0.009 B 24.0±0.2 0.945±0.008 C 24.0±0.2 0.945±0.008 D 26.0±0.2 1.024 +0.008 –0.009 F 2.25 0.089 G 2.25 0.089 H 0.22 +0.05 –0.04 0.009±0.002 I 0.10 0.004 J 0.5 (T.P.) K 1.0±0.2 0.020 (T.P.) 0.039 +0.009 –0.008 L 0.5±0.2 0.020 +0.008 –0.009 M 0.145+0.055 –0.045 0.006±0.002 N 0.10 0.004 P 1.4±0.1 0.055±0.004 Q 0.125±0.075 0.005±0.003 R 3° +7° –3° 3° +7° –3° S 1.7 MAX. 0.067 MAX. S160GM-50-8ED-2 Data Sheet U13675EJ2V1DS00 75 µPD705102 18. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 18-1. Surface Mounting Type Soldering Conditions µPD705102GM-143-8ED: 160-pin plastic LQFP (fine pitch) (24 × 24 mm) µPD705102GM-133-8ED: 160-pin plastic LQFP (fine pitch) (24 × 24 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher), Count: two times or less, Exposure limit: 3 daysNote (after that, prebake 125°C for 10 hours) IR35-103-2 VPS Package peak temperature: 215°C, Time: 40 sec. Max. (at 200°C or higher), Count: two times or less, Exposure limit: 3 daysNote (after that, prebake 125°C for 10 hours) VP15-103-2 Partial heating Pin temperature: 300°C Max., Time: 3 sec. Max. (per pin row) — Note After opening dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). 76 Data Sheet U13675EJ2V1DS00 µPD705102 [MEMO] Data Sheet U13675EJ2V1DS00 77 µPD705102 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 78 Data Sheet U13675EJ2V1DS00 µPD705102 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U13675EJ2V1DS00 79 µPD705102 The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. V830, V832, and V830 Family are trademarks of NEC Corporation. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98.8