DATA SHEET MOS INTEGRATED CIRCUIT µPD75048 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The µPD75408 is a 4-bit single-chip microcomputer whose data processing capability is comparative to that of an 8-bit microcomputer. The µPD75048 employs a CPU whose minimum instruction execution time is 0.95 µs, and contains the EEPROM, A/D converter, multi-function timer, and high performance hardware to provide high cost to performance ratio. Detailed functions are described in the following user's manual. Read this manual when designing your system. µPD75048 User's Manual: IEU-704 FEATURES • Built-in EEPROM: 1024 x 4 bits (data memory area) • Built-in 8-bit resolution A/D converter (successive • I/O ports: 48 pins • Middle voltage N-ch open drain input/output approximation): 8 channels ports: 12 pins • Capable of operating at low voltage: VDD = 2.7 to • 43 I/O lines can be provided with internal pull- 6.0 V down resistors • Reference voltage can be arbitrarily specified • PROM version is available: µ PD75P048 between AVREF+ and AVREF-. (One-time PROM) • Built-in multi-function timer which can provide the following functions: • 8-bit timer • PWM output • 16-bit free running timer • 16-bit integration type A/D converter counter APPLICATIONS • Consumer electronics products, telephones, cameras, automobile audio equipment, electronics measurement equipment, etc. ORDERING INFORMATION Part Number Package µPD75048CW-xxx 64-pin plastic shrink DIP (750 mil) µ PD75048GC-xxx-AB8 64-pin plastic QFP ( Quality grade 14mm) Standard Standard Remarks: xxx is ROM code number. Please refer to “Quality Grade on NEC Semiconductor Devices” (Document Number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. The information in this document is subject to change without notice. Document No. IC - 2518C (O. D. No. IC - 7931C) Date Published February 1994 P Printed in Japan The mark ★ shows major revised points. NEC Corporation 1990 µPD75048 FUNCTIONAL OUTLINE Item Function Instructions 41 Instruction Execution Time • With main system clock: 0.95, 1.91, 15.3 µs (at 4.19 MHz) • With subsystem clock: 122 µs (at 32.768 kHz) Program memory (ROM) : 8064 x 8 bits Internal Memory Data memory (RAM) : 512 x 4 bits Data memory (EEPROM) : 1024 x 4 bits EEPROM • • • • General-Purpose Register • 4-bit manipulation: 8 (X, A, B, C, D, E, H, L) • 8-bit manipulation: 4 (XA, BC, DE, HL) Accumulator • Bit accumulator (CY) • 4-bit accumulator (A) • 8-bit accumulator (XA) Instruction Set • • • • I/O Line Retains data in case of power failure Number of writes: 100,000 times Write time: 10 ms Write end, overwrite interrupt functions Abundant bit manipulation instructions Efficient 4-bit data manipulation instructions 8-bit data manipulation instructions GETI instruction executing 2-/3-byte instruction with a single byte 48 12 Input pin 24 CMOS I/O pin (direct LED drive: 4) Via software, w/pull-up resistor: 27 w/pull-down resistor: 4 12 Medium-voltage N-ch open-drain I/O (direct LED drive) By mask option, w/pull-up resistor: 12 • 8-bit timer/event counter • Clock source: 4 steps • Can count events • 8-bit basic interval timer • Reference time generation: 1.95, 7.82, 31.3, 250 ms (at 4.19 MHz) • Can be used as watchdog timer Timer 4 chs • Clock timer • Generates 0.5-second time intervals • Count clock source: main system clock or subsystem clock (selectable) • Clock fast forward mode (generates 3.9-ms time intervals) • Buzzer output (2, 4, 32 kHz) • Multi-function timer Can be used as: • 8-bit timer • PWM output • 16-bit free-running timer • Counter for 16-bit integral A/D converter 8-bit Serial Interface • Three modes: • 3-line serial I/O mode ... MSB/LSB first (selectable) • 2-line serial I/O mode • SBI mode Bit Sequential Buffer Special bit manipulation memory: 16 bits • Ideal for remote controller Timer/event counter output (PTO0): output of square wave at specified frequency Clock Output Function Clock output (PCL): Φ/, fx/23 , fx/24 , fx/26 Buzzer output (BUZ): 2, 4, 32 kHz (with main system clock or subsystem clock) 2 µPD75048 (cont'd) Item Function A/D Converter 8-bit resolution A/D converter (successive approximation type): 8 channels • Low-voltage operation: V DD = 2.7 – 6.0 V • Reference voltage setting range: AVREF+ – AV REF– 2.5 V ≤ (AV REF+) – (AVREF–) ≤ 6.0 V Vector Interrupt External: 3, Internal: 6 Test Input External: 1, Internal: 1 System Clock Oscillator Circuit • Ceramic/crystal oscillator circuit for main system clock oscillation • Crystal oscillator circuit for subsystem clock oscillation Standby Function • STOP mode: main system clock oscillation stops • HALT mode: system clock oscillation continues (clock supply to CPU stops) Package • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP ( 14 mm) 3 µPD75048 CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ........................................................................................ 5 2. BLOCK DIAGRAM ......................................................................................................................8 3. PIN FUNCTIONS ........................................................................................................................9 3.1 PORT PINS ........................................................................................................................................9 3.2 NON PORT PINS ............................................................................................................................ 11 3.3 PIN INPUT/OUTPUT CIRCUIT ...................................................................................................... 13 3.4 SELECTION OF MASK OPTIONS ................................................................................................. 16 3.5 PROCESSING OF UNUSED PINS ................................................................................................ 17 4. MEMORY CONFIGURATION ................................................................................................. 18 5. EEPROM ....................................................................................................................................21 6. PERIPHERAL HARDWARE FUNCTIONS ............................................................................... 22 6.1 PORT ............................................................................................................................................... 22 6.2 CLOCK GENERATOR CIRCUIT ..................................................................................................... 23 6.3 CLOCK OUTPUT CIRCUIT ............................................................................................................. 24 6.4 BASIC INTERVAL TIMER .............................................................................................................. 25 6.5 WATCH TIMER ............................................................................................................................... 26 6.6 TIMER/EVENT COUNTER ............................................................................................................. 27 6.7 SERIAL INTERFACE ....................................................................................................................... 29 6.8 A/D CONVERTER .......................................................................................................................... 31 6.9 MULTI-FUNCTION TIMER (MFT) ................................................................................................. 32 6.10 BIT SEQUENTIAL BUFFER ........................................................................................................... 34 7. INTERRUPT FUNCTIONS ....................................................................................................... 34 8. STANDBY FUNCTIONS .......................................................................................................... 36 9. RESET FUNCTION .................................................................................................................. 37 10. INSTRUCTION SET ................................................................................................................. 39 11. ELECTRICAL SPECIFICATIONS ............................................................................................. 45 12. PERFORMANCE CURVE ......................................................................................................... 59 13. PACKAGE DRAWINGS ........................................................................................................... 61 14. RECOMMENDED SOLDERING CONDITIONS ...................................................................... 63 APPENDIX A. COMPARISON BETWEEN µPD75048 AND 75028/75008 FUNCTIONS .......... 64 APPENDIX B. DEVELOPMENT TOOLS ....................................................................................... 65 4 µPD75048 1. PIN CONFIGURATION (TOP VIEW) • 64-PIN PLASTIC SHRINK DIP (750 mil) SB1/SI/P03 1 64 VSS SB0/SO/P02 2 63 P30 SCK/P01 3 62 P31 INT4/P00 4 61 P32 BUZ/P23 5 60 P33 PCL/P22 6 59 P40 PCO/P21 7 58 P41 PTO0/P20 8 57 P42 MAT/P103 9 56 P43 MAZ/P102 10 55 P50 11 54 P51 12 53 P52 RESET 13 52 P53 X1 14 51 P60/KR0 µPD75048CW–· MAI/P101 MAR/P100 50 P61/KR1 49 P62/KR2 48 P63/KR3 15 IC 16 XT1 17 XT2 18 47 P70/KR4 VDD 19 46 P71/KR5 AVDD 20 45 P72/KR6 AVREF+ 21 44 P73/KR7 AVREF– 22 43 P80 AN7 23 42 P81 AN6 24 41 P82 AN5 25 40 P83 ·· XXX X2 AN4 26 39 P90 AN3/P113 27 38 P91 AN2/P112 28 37 P92 AN1/P111 29 36 P93 AN0/P110 30 35 P10/INT0 AVSS 31 34 P11/INT1 TI0/P13 32 33 P12/INT2 IC : Internally Connected (Connect directly to VDD) 5 µPD75048 P83 P82 P81 P80 P73/KR7 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 P53 P52 P51 14 mm) P50 • 64-PIN PLASTIC QFP ( 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 P90 P42 2 47 P91 P41 3 46 P92 P40 4 45 P93 P33 5 44 P10/INT0 P32 6 43 P11/INT1 P31 7 42 P12/INT2 P30 8 41 TI0/P13 VSS 9 40 AVSS 39 AN0/P110 38 AN1/P111 AB8 µPD75048GC–·XXX · ·–AB8 P43 SB1/SI/P03 10 SB0/SO/P02 11 SCK/P01 12 37 AN2/P112 INT4/P00 13 36 AN3/P113 BUZ/P23 14 35 AN4 PCL/P22 15 34 AN5 PPO/P21 16 33 AN6 IC : Internally Connected (Connect directly to VDD ) 6 AN7 AVREF– AVREF+ VDD AVDD XT2 IC XT1 X2 X1 RESET MAR/P100 MAI/P101 MAZ/P102 MAT/P103 PTO0/P20 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 µPD75048 PIN IDENTIFICATION P00-03 : Port0 : Port 0 P10-13 : Port1 : Port 1 P20-23 : Port2 : Port 2 P30-33 : Port3 : Port 3 P40-43 : Port4 : Port 4 P50-53 : Port5 : Port 5 P60-63 : Port6 : Port 6 P70-73 : Port7 : Port 7 P80-83 : Port8 : Port 8 P90-93 : Port9 : Port 9 P100-103 : Port10 : Port 10 P110-113 : Port11 : Port 11 KR0-7 : Key Return : Key interrupt input SCK : Serial Clock : Serial clock input/output SI : Serial Input : Serial data input SO : Serial Output : Serial data output SB0, 1 : Serial Bus 0, 1 : Serial bus input/output RESET : Reset Input : Reset input TI0 : Timer Input 0 : External event pulse input PTO0 : Programmable Timer Output 0 : Timer/event counter output BUZ : Buzzer Clock : Arbitrary frequency output PCL : Programmable Clock : Clock output INT0,1,4 : External Vectored Interrupt 0, 1, 4 : External vector interrupt input INT2 : External Test Input 2 : External test input X1, 2 : Main System Clock Oscillation 1, 2 : Main system clock oscillation pin XT1, 2 : Subsystem Clock Oscillation 1, 2 : Subsystem clock oscillation pin MAR : Reference Integration Control : Reference integration signal output MAI : Integration Control MAZ : Autozero Control MAT : External Comparate Timing Input : External comparator signal input PPO : Programmable Pulse Output ... : Pulse output ... MFT timer mode AN0-7 : Analog Input 0-7 : Analog input AVREF+ : Analog Reference (+) : Analog reference voltage (+) input (AVDD ) AVREF- : Analog Reference (-) : Analog reference voltage (-) input (AVSS ) MFT A/D mode MFT A/D mode : Integration signal output : Autozero signal output : MFT timer mode AVDD : Analog VDD : A/D converter positive power supply AVSS : Analog VSS : A/D converter GND VDD : Positive Power Supply : Positive power supply VSS : Ground : GND Remarks : MFT: Multi-function timer 7 8 INTBT TIMER /COUNTER #0 TI0/P13 PTO0/P20 PROGRAM COUNTER PORT 0 4 P00–P03 PORT 1 4 P10–P13 PORT 2 4 P20–P23 DATA MEMORY PORT 3 4 P30–P33 GENERAL REG. PORT 4 4 P40–P43 PORT 5 4 P50–P53 PORT 6 4 P60–P63 PORT 7 4 P70–P73 PORT 8 4 P80–P83 PORT 9 4 P90–P93 PORT 10 4 P100–P103 PORT 11 4 P110–P113 SP CY ALU INTT0 BANK SI/SB1/P03 SERIAL INTERFACE SO/SB0/P02 2. BLOCK DIAGRAM BIT SEQ. BUFFER BASIC INTERVAL TIMER SCK/P01 INTCSI INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0–KR3/P60–P63 KR4–KR7/P70–P73 INTERRUPT CONTROL ROM PROGRAM MEMORY 8064×8 BITS 8 DECODE AND CONTROL RAM 512 × 4 BITS WATCH TIMER BUZ/P23 INTW EEPROM 1024 × 4 BITS AVDD AVREF+ AVREF– AVSS AN0–AN3/P110–P113 AN4–AN7 A/D CONVERTER 8 fx/2N MAR/P100 MAI/P101 MAZ/P102 PPO/P21 PCL/P22 CLOCK DIVIDER CLOCK GENERATOR SUB XT1 XT2 MAIN X1 STAND BY CONTROL X2 INTMFT VDD VSS RESET µPD75048 MAT/P103 MULTI– FUNCTION TIMER CLOCK OUTPUT CONTROL CPU CLOCK Φ µPD75048 3. PIN FUNCTIONS 3.1 PORT PINS Also Served Pin Name Input/Output As P00 Input/ Output INT4 P01 Input/ Output SCK P02 Input/ Output SO/SB0 P03 Input/ Output SO/SB1 P10 INT0 P11 INT1 4-bit input/output port(PORT0) Pull up resistros can be specified in 3-bit units for the P01 to P03 pins by software. F -A X Input F -B M -C With noise elimination function 4-bit input port(PORT1) Internal pull-up resistors can be specified in 4-bit units by software. X Input E -B X Input E -B — N-ch open-drain 4-bit input/output port (PORT4) Internal pull-up resistors can be specified in 4-bit units (by mask option). Resistive voltage is 10V in the opendrain mode. High level (with internal pull-up register) or high impedance M — N-ch open-drain 4-bit input/output port (PORT5) Internal pull-up resistors can be specified in bit units (by mask option). Resistive voltage is 10V in the opendrain mode. High level (with internal pull-up register) or high impedance M P13 TI0 P20 PTO0 P23 B B -C INT2 P22 When Reset Input P12 Input/ Output 8-Bit I/O X Input P21 Function Input/ Output Circuit TYPE*1 PPO PCL 4-bit input/output port(PORT2) Internal pull-up resistors can be specified in 4-bit units by software. BUZ P30* 2 P31* 2 P32*2 — Input/ Output P33*2 P40-43*2 P50-53*2 — — — Input/ Output Input/ Output Programmable 4-bit input/output port (PORT3) This port can be specified for input/ output in bit units. Internal pull-up resistors can be specified in 4-bit units by software. *1: Circles indicate Schmitt trigger inputs. 2: Can directly drive LED. 9 µPD75048 (cont'd) When Reset Input/ Output Circuit TYPE*1 Input F -A 4-bit input/output port(PORT7) Internal pull-up resistors can be specified in 4-bit units by software. Input F -A — 4-bit input/output port(PORT8) Internal pull-up resistors can be specified in 4-bit units by software. Input E-B — 4-bit input/output port(PORT9) Internal pull-down resistors can be specified in 4-bit units by software. Input E-D High level (with internal pull-up resistor) or high impedance M Input Y-A Pin Name Input/Output Also Served As P60 P61 P62 KR0 Input/ Output KR1 KR2 P63 KR3 P70 KR4 P71 P72 Input/ Output KR6 8-Bit I/O Programmable 4-bit input/output port (PORT6) This port can be specified for input/ output in bit units. Internal pull-up resistors can be specified in 4-bit units by software. KR7 P73 P80-83 KR5 Function Input/ Output X P90-93 Input/ Output MAR P100 P101 P102 Input/ Output MAI MAZ P103 MAT P110 AN0 P111 N-ch open-drain 4-bit input/output port (PORT10) Internal pull-up resistors can be specified in bit units (by mask option). Resistive voltage is 10V in the opendrain mode. X Input AN1 4-bit input port(PORT11) P112 AN2 P113 AN3 *1: Circles indicate Schmitt trigger inputs. 10 µPD75048 3.2 NON PORT PINS Also Served Pin Name Input/Output As Functon When Reset Input/ Output Circuit TYPE*1 Input P13 Timer/event counter external event pulse input Input B-C PTO0 Input/ Output P20 Timer/event counter output Input E-B PCL Input/ Output P22 Clock output Input E-B BUZ Input/ Output P23 Arbitrary frequency output(for buzzer or for trimming the system clock) Input E-B SCK Input/ Output P01 Serial clock input/output Input F-A SO/SB0 Input/ Output P02 Serial data output Serial bus input/output Input F-B SI/SB1 Input/ Output P03 Serial data input Serial bus input/output Input M-C Input P00 Edge detection vector interrupt input (both rising and falling edge detection are effective) Input B Edge detection vector interrupt input (detection edge is selectable) Input B-C Asynchronous Input B-C TI0 INT4 INT0 P10 Input INT1 P11 INT2 Input P12 Clock synchronous Asynchronous Edge detection vector interrupt input (rising edge is detected.) KR0-KR3 Input/ Output P60-63 Parallel falling edge detection testable input Input F-A KR4-KR7 Input/ Output P70-73 Parallel falling edge detection testable input Input F-A MAR Input/ Output P100 MAI Input/ Output P101 *2 M MAZ Input/ Output P102 MAT Input/ Output P103 PPO Input/ Output P21 Input E-B Reference integration signal output In the MFT integration type A/ D converter mode Integration signal output Auto zero signal output Comparator input In the MFT timer mode Timer pulse output *1: Circles indicate Schmitt trigger inputs. 2: High level (with internal pull-up resistor) or high impedence Remarks: MFT: Multi-function timer 11 µPD75048 (cont'd) Pin Name Input/Output Also Served As AN0-AN3 Function Y-A — Input AN4-AN7 8-bit analog input Input Y — — Z-A — Z-A — Reference voltage input (AVDD side) Reference voltage input (AVSS side) Positive power supply — — — GND — — — A crystal/ceramic resonator for the main system clock is connected across these pins. When using the external clock, the X1 pin inputs the external clock, and the X2 pin inputs the reverse phase of the external clock signal. — — — — AVREF+ Input — AVREF- Input — AVDD — AVSS — X1, X2 When Reset Input Input/ Output Circuit TYPE*1 Pins only for A/D converter XT1, XT2 Input — A crystal resonator for the subsystem clock is connected across these pins. When using the external clock, the XT1 pin inputs the external clock, and the XT2 pin inputs the reverse phase of the external clock signal. The XT1 pin can be used as a 1-bit input(test) pin. RESET Input — System reset input — B — — — — — — IC — — VDD — — Internally Connected. Should be connected directly to VDD. Positive power supply VSS — — GND *1: Circles indicate Schmitt trigger inputs. 12 µPD75048 3.3 PIN INPUT/OUTPUT CIRCUITS The following shows a simplified input/output circuit diagram for each pin of the µPD75048. TYPE D (for TYPE E–B, F-A) TYPE A (for TYPE E–B) VDD VDD data P–ch P–ch OUT IN N–ch Input buffer of CMOS standard output disable N–ch Push–pull output that can be set in the output high–impedance state (both P–ch and N–ch are off) TYPE E–B TYPE B VDD P.U.R. P.U.R. enable P–ch IN data IN/OUT Type D output disable Type A Schmitt trigger input with hysteresis characteristics P.U.R. : Pull–Up Resistor 13 µPD75048 TYPE E–D TYPE B–C data VDD P.U.R. P–ch IN/OUT Type D output disable P.U.R. enable Type A P.U.R. enable IN N–ch P.D.R. P.U.R. : Pull–Up Resistor P.D.R. : Pull–Down Resistor TYPE M–C TYPE F–A VDD VDD P.U.R. P.U.R. P.U.R. enable P.U.R. enable P–ch IN/OUT data IN/OUT Type D output disable data output disable Type B P.U.R. : Pull–Up Resistor 14 P–ch P.U.R. : Pull–Up Resistor N-ch µPD75048 TYPE Y TYPE F–B VDD P.U.R. P.U.R. enable output disable (P) P–ch VDD AVDD IN P-ch + AVDD IN/OUT data output disable P–ch N–ch Sampling C N-ch AVSS Reference voltage (from a voltage tap of series resistor string) AVSS output disable (N) – input enable P.U.R. : Pull–Up Resistor TYPE Y–A TYPE M VDD IN instruction P.U.R. enable (Mask Option) IN/OUT Input buffer data N-ch (resistive voltage: +10 V) output disable AVDD IN P–ch N–ch + AVDD Sampling C Middle voltage input buffer (resistive voltage: +10 V) AVSS – AVSS Reference voltage (from a voltage tap of series resistor string) P.U.R. : Pull–Up Resistor 15 µPD75048 TYPE Z–A AVREF+ Reference voltage AVREF– 3.4 SELECTION OF MASK OPTIONS The following mask options are available: Pin P40 - P43, P50 - P53, P100 - P103 XT1, XT2 16 Mask Option 1 w/pull-up resistor (can be specified bitwise) 2 w/o pull-up resistor (can be specified bitwise) 1 w/feedback resistor (with subsystem clock used) 2 w/o feedback resistor (without subsystem clock used) µPD75048 3.5 ★ PROCESSING OF UNUSED PINS Pin P00/INT4 Recommended Condition Connect to V ss P01/SCK P02/SO/SB0 Connect to VSS or VDD P03/SI/SB1 P10/INT0-P12/INT2 P13/TI0 Connect to VSS P20/PTO0 P21/PPO P22/PCL P23/BUZ P30-P33 P40-P43 P50-P53 P60/KR0-P63/KR3 Input: Connect to VSS or VDD P70/KR4-P73/KR7 Output: Open P80-P83 P90-P93 P100/MAR P101/MAI P102/MAZ P103/MAT P110/AN0-P113/AN3 AN4-AN7 Connect to VSS or VDD AVREF+ AVREF- Connect to VSS AVSS AVDD Connect to VDD XT1 Connect to VSS or VDD XT2 Open IC Connect directly to VDD 17 µPD75048 4. MEMORY CONFIGURATION • Program memory (ROM)...8064 x 8 bits (0000H-1F7FH) • 0000H, 0001H: Vector table to which address from which program is started is written after reset • 0002H-000FH: Vector table to which address from which program is started is written after interrupt • 0020H-007FH: Table area referenced by GETI instruction • Data memory • Data area Static RAM....512 x 4 bits (000H-1FFH) EEPROM....1024 x 4 bits (400H-7FFH) • Peripheral hardware area....128 x 4 bits (F80H-FFFH) 18 µPD75048 Address 0000H 7 6 5 MBE 0 0 0 Internal reset start address (upper 5 bits) Internal reset start address (lower 8 bits) 0002H MBE 0 0 INTBT/INT4 start address (upper 5 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE 0 0 INT0 start address (upper 5 bits) INT0 start address (lower 8 bits) 0006H MBE 0 0 INT1 start address (upper 5 bits) INT1 start address (lower 8 bits) 0008H MBE 0 0 INTCSI start address (upper 5 bits) INTCSI start address (lower 8 bits) 000AH MBE 0 0 CALLF ! faddr instruction entry address INTT0 start address (upper 5 bits) INTT0 start address (lower 8 bits) 000CH MBE 0 0 INTMFT start address (upper 5 bits) INTMFT start address (lower 8 bits) 000EH MBE 0 0 INTEE/INTOW start address (upper 5 bits) BRCB ! caddr instruction branch address CALL ! addr instruction subroutine entry address BR ! addr instruction branch address INTEE/INTOW start address (lower 8 bits) BR $addr instruction relational branch address (–15 to –1, +2 to +16) 0020H GETI instruction reference table 007FH 0080H 07FFH 0800H Branch destination address and subroutine entry address for GETI instruction 0FFFH 1000H BRCB ! caddr instruction branch address 1F7FH Fig. 4-1 Program Memory Map 19 µPD75048 Data memory Memory bank 000H General-purpose register area Stack area (8 × 4) 007H Data area Static RAM (512 × 4) 0 256 × 4 (248 × 4) 0FFH 100H 256 × 4 1 1FFH Unmapped 400H 256 × 4 4 256 × 4 5 256 × 4 6 256 × 4 7 4FFH 500H Data area EEPROM (1024 × 4) 5FFH 600H 6FFH 700H 7FFH Unmapped F80H 128 × 4 Peripheral hardware area FFFH Fig. 4-2 Data Memory Map 20 15 µPD75048 5. EEPROM The µPD75048 contains the 1024-word x 4-bit EEPROM (Electrically Erasable PROM). The EEPROM of the µPD75048 has the following characteristics. • The EEPROM can retain its contents even if the power is turned off. • In the same manner as the static RAM, data can be manipulated (auto-erase/write/read) in 4-bit or 8-bit units by using a memory manipulation instruction • The contens of EEPROM are automatically erased or written by hardware, so that the overhead of the software is alleviated. • • • Write time .... 10 ms. • Number of write operation100,000 times (guaranteed). Write operation can be controlled by interrupt. • When write operation is completed an interrupt occurs. • When overwrite is executed. (Write operation is executed during write operation) Whether or not the EEPROM is possible to be written can be checked by individually checking the write status flag. 21 µPD75048 6. PERIPHERAL HARDWARE FUNCTIONS 6.1 PORT I/O ports are classified into the following three inds: • CMOS input (PORT0, 1, 11) : 12 • CMOS I/O (PORT2, 3, 6, 7, 8, 9) : 24 • N-ch open-drain I/O (PORT4, 5, 10) : Total 12 48 Table 6-1 Port Function Port (Symbol) PORT0 PORT1 Function 4-bit input PORT3* PORT6 4-bit input/output PORT2 PORT7 PORT4* PORT5* PORT10* PORT8 PORT9 PORT11 4-bit input/output 4-bit input Remarks Also serves as the SO/SB0, SI/SB1, SCK, INT0 to 2, INT4, and TI0 pins Can be specified for input/output in 1-bit units. Port 6 can also serve as the KR0 to KR3 pins. Can be specified for input/output in 4-bit units. Ports 6 and 7 can be paired to input/ output data in 8-bit units. Port 2 can also serve as the PTO0, PPO, PCL, and BUZ pins. Can be specified for input/output 4-bit input/output in 4-bit units. Ports 4 and 5 can (N-ch open-drain, be paired to input/output data in can sustain with 10V) 8-bit units. *: Can directly drive LED. 22 Operation/Feature Can be read or tested regardless of the operation mode of the shared pin. Also serves as the KR4 to KR7 pins. Whether or not the internal pull-up resistor is provided can be specified for each bit by mask option. Port 10 can also serve as the MAR, MAI, MAZ, and MAT pins. Can be specified for input/output in 4-bit units. 4-bit input-only port. Port 11 can also serve as the AN0 to AN3 pins. µPD75048 6.2 CLOCK GENERATOR CIRCUIT The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and system clock control register (SCC). This circuit can generate two types of clocks: main system clock and subsystem clock. In addition, it can also change the instruction execution time. • 0.95 µs, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz) • 122µ s (subsystem clock: 32.768 kHz) . . . . . . Multi-function timer Basic interval timer (BT) Timer/event counter Serial interface Watch timer A/D converter (successive approximation) . INT0 noise rejecter circuit . Clock output circuit XT1 VDD XT2 Subsystem clock oscillator fXT Main system clock oscillator fX Watch timer X1 VDD X2 1/2 to 1/4096 Frequency divider Oscillator disable signal Frequency divider Selector WM.3 SCC Selector 1/2 1/16 SCC3 1/4 Internal bus SCC0 PCC Φ . CPU . INT0 noise rejecter circuit . Clock output circuit PCC0 PCC1 4 HALT F/F PCC2 S HALT* PCC3 STOP* R PCC2, PCC3 clear signal STOP F/F Q Q Wait release signal from BT S RESET signal R Remarks1: 2: 3: 4: 5: 6: 7: Standby release signal from interrupt control circuit fX = Main system clock frequency fXT = Subsystem clock frequency Φ = CPU clock PCC: Processor clock control register SCC: System clock control register * indicates instruction execution. One clock cysle (tCY) of Φ is one machine cycle of an instruction. For tCY, refer to AC characteristics in 11. ELECTRICAL SPECIFICATIONS. Fig. 6-1 Clock Generator Block Diagram 23 µPD75048 6.3 CLOCK OUTPUT CIRCUIT The clock output circuit outputs clock pulse from the P22/PCL pin. This clock pulse is used for supplying clock pulses to the remote control output, peripheral LSIs, etc. • Clock output (PCL): Φ, 524 kHz, 65.5 kHz (at 4.19 MHz) From the clock generator F Output buffer fX/23 Selector fX/24 PCL/P22 fX/26 PORT2.2 P22 output latch CLOM3 CLOM2 CLOM1 CLOM0 CLOM Bit 2 of PMGB Port 2 input/ output mode specification bit 4 Internal bus Fig. 6-2 Clock Output Circuit Configuration Remarks: A measures to prevent outputting narrow width pulse when selecting clock output enable/disable is taken. 24 µPD75048 6.4 BASIC INTERVAL TIMER The basic interval timer has these functions: • Interval timer operation which generates a reference time interrupt • Watchdog timer application which detects a program runaway • Selects the wait time for releasing the standby mode and counts the wait time • Reads out the count value From the clock generator Clear Clear fX/25 fX/27 Set signal Basic interval timer (8-bit frequency divider circuit) MPX fX/29 BT fX/212 3 BTM3 *SET1 BTM2 BT interrupt request flag Vector interrupt request IRQBT signal Wait release signal for standby release BTM1 BTM0 BTM 4 8 Internal bus Remarks : *: Instruction execution Fig. 6-3 Basic Interval Timer Configuration 25 µPD75048 6.5 WATCH TIMER The µ PD75048 has a built-in 1-ch watch timer. The clock timer has the following functions. • Sets the test flag (IRQW) with 0.5sec interval. The standby mode can be released by IRQW. • 0.5 second interval can be generated either from the main system clock or subsystem clock. • Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is convenient for program debugging, test, etc. • Arbitrary frequency (2.048kHz/4.096kHz/32.768kHz) can be output to the P23/BUZ pin. This can be used for beep and system clock frequency trimming. • The frequency divider circuit can be cleared so that zero second clock start is possible. fW (256 Hz:3.91 ms) 27 From the clock generator fX 128 (32.768 kHz) Selector fW (32.768 kHz) fXT (32.768 kHz) Frequency divider ( INTW IRQW set signal Selector fw 214 ( ) 2 Hz 0.5 sec 4 kHz 2 kHz Clear Selector Output buffer P23/BUZ WM WM7 PORT2.3 0 WM5 WM4 WM3 8 WM2 WM1 WM0 P23 output latch Bit test instruction Internal bus ( ) is for fX = 4.194304 MHz, fXT = 32.768 KHz. Fig. 6-4 Clock Timer Block Diagram 26 Bit 2 of PMGB Port 2 input/output mode ) µPD75048 6.6 TIMER/EVENT COUNTER The µ PD75048 has a built-in 1-ch timer/event counter. The timer/event counter has the following functions. • Programmable interval timer operation • Outputs square-wave signal of an arbitrary frequency to the PTO0 pin. • Event counter operation • Divides the TI0 pin input in N and outputs to the PTO0 pin (frequency divider operation). • Supplies serial shift clock to the serial interface circuit. • Count condition read out function 27 28 Internal bus 8 SET1* TM0 8 8 TMOD0 TOE0 TO enable flag Modulo register (8) TM07 TM06 TM05 TM04 TM03 TM02 TM01 TM00 Coincidence Comparator (8) Input buffer P20 output latch Bit 2 of PGMB Port 2 input/ output mode To serial interface 8 PORT1.3 PORT2.0 8 TOUT F/F Reset P20/PTO0 Output buffer T0 P13/TI0 From the clock generator Count register (8) MPX CP Clear ( INTT0 IRQT0 set signal ) Timer operation start signal RESET IRQT0 clear signal *:Instruction execution Fig. 6-5 Timer/Event Counter Block Diagram µPD75048 µPD75048 6.7 SERIAL INTERFACE The µPD75048 is equipped with an 8-bit clocked serial interface that operates in the following four modes: • Operation stop mode • Three-line serial I/O mode • Two-line serial I/O mode • SBI mode (serial bus interface mode) 29 30 Internal bus 8/4 CSIM 8 Bit test 8 8 Slave address register (SVA) (8) SBIC Coincidence signal Address comparator RELT CMDT (8) P03/SI/SB1 SET CLR Shift register (SIO) (8) D SO latch Q ACKT ACKE BSYE Selector Bit test Bit manipulation Selector P02/SO/SB0 Busy/ acknowledge output circuit Bus release/ command/ acknowledge detector circuit P01/SCK RELD CMDD ACKD Serial clock counter P01 output latch Serial clock control circuit ( Serial clock selector INTCSI IRQCSI set signal ) fX/23 fX/24 fX/26 TOUT F/F (from timer/ event counter) External SCK µPD75048 Fig. 6-6 Serial Interface Block Diagram INTCSI control circuit µPD75048 6.8 A/D CONVERTER The µ PD75048 has an 8-bit precision successive approximation A/D converter with 8 analog input channels (AN0 to AN7). Internal bus 0 ADM6 ADM5 ADM4 SOC EOC 0 0 ADM 8 AN0/P110 Control circuit AN1/P111 Sample hold circuit AN3/P113 AN4 Multiplexer AN2/P112 + SA register (8) – Comparator AN5 AN6 8 AN7 Tap decoder AVREF+ R/2 R R R R/2 Serial resister string AVREF- Fig. 6-7 A/D Converter Block Diagram 31 µPD75048 6.9 MULTI-FUNCTION TIMER (MFT) The µPD75048 contains 1 channel of multi-function timer (MFT). The MFT has the following four modes and functions: • 8-bit timer mode • Functions as programmable interval timer • Outputs square waves of arbitrary frequency to the PPO pin • PWM mode • Outputs 6/7/8-bit precision PWM signal to the PPO pin • 16-bit free running timer mode • Functions as interval timer which generates an interrupt with specified interval • Can be used as one-shot timer • Integration type A/D converter mode 32 • Outputs 16-bit integration type A/D converter control signal • 13/14/15/16-bit precision selectable Internal bus 8 Clear MAT/P103 Edge selector 8 Input/ output mode register Output latch P21 P100P101 P102 Selector Count register (MFTL) MAZ/P102 Integration type A/D converter controller Modulo latch MAI/P101 MAR/P100 fX/2 fX/23 fX/25 fX/27 fX/29 Comparator MPX PPO/P21 Coinci -dence MFT F/F 8 fX/211 Overflow Selector Count register (MFTH) Tap selector ( Interrupt selector INTMFT IRQMFT set signal ) RESET IRQMFT clear signal Selector MFTM7 MFTM6 MFTM5 MFTM4 MFTM3 MFTM2 MFTM1 MFTM0 MFTM 8 MFTC3 MFTC2 MFTC1 MFTC0 MFTC 1/4 Fig. 6-8 Multi-Function Timer Block Diagram 33 µPD75048 Internal bus µPD75048 6.10 BIT SEQUENTIAL BUFFER .... 16 BITS The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units. Address FC3H Bit 3 1 0 3 BSB3 Symbol L register 2 FC2H L=F 2 FC1H 1 0 3 BSB2 L=C L=B 2 FC0H 1 0 3 BSB1 L=8 L=7 2 1 0 BSB0 L=4 L=3 L=0 DECS L INCS L Remarks: For the pmem.@L addressing, the specification bit is shifted according to the L register. Fig. 6-9 Bit Sequential Buffer Format 7. INTERRUPT FUNCTIONS The µPD75048 has 9 different interrupt sources. In addition to that, multiple interrupt by software control is also possible. The µPD75048 is also provided with two types of test sources, of which INT2 was two types of edge detection testable inputs. The interrupt control circuit of the µPD75048 has these functions: • Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by using the interrupt flag (IExxx) and interrupt master enable flag (IME). • The interrupt start address can be arbitrarily set. • Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of software). • Standby mode release (Interrupts to be released can be selected by the interrupt enable flag). 34 Internal bus 2 1 3 IM2 IM1 IM0 IME IST0 Interrupt enable flag (IExxx) INT4 /P00 INT0 /P10 INT1 /P11 * INT BT Both edge detection circuit Edge detection circuit Edge detection circuit IRQ0 IRQ1 IRQCSI INTT0 IRQT0 IRQEE INTOW IRQOW INTW Falling edge detection circuit IRQW Selector KR0/P60 Priority control circuit Standby release signal IRQ2 IM2 * : Noise elimination circuit 35 Fig. 7-1 Interrupt Control Circuit Block Diagram µPD75048 Rising edge detection circuit Vector table address generator IRQMFT INTEE INT2 / P12 VRQn IRQ4 INTCSI INTMFT KR7/P73 Decoder IRQBT µPD75048 8. STANDBY FUNCTIONS The µ PD75048 has two different standby modes (STOP mode and HALT mode) to reduce the power consumption while waiting for program execution. Table 8-1 Each Status in Standby Mode STOP Mode HALT Mode Setting Instruction STOP instrtuction HALT Instruction System Clock for Setting Can be set only when operating on the main system clock Can be set either with the main system clock or the subsystem clock Operation Status Clock Generator Only the main system clock stops its operation Only the CPU clock Φ stops its operation (oscillation continues) Basic Interval Timer No operation Operates only when main system clock oscillates (Sets IRQBT at reference time interval) Serial Interface Can operate only when the external SCK input is selected for the serial clock Operates only when external SCK input is selected as serial clock, or when main system clock oscillates Timer/Event Counter Can operate only when the TI0 pin input is selected for the count clock Operates only when TI0 pin input is selected as count clock, or when main system clock oscillates Watch Timer Can operate when f XT is selected as the count clock Can operate A/D Convertor No operation Can operate * Multi Function Timer No operation Can operate * EEPROM No operation Can operate * External Interrupt INT1, INT2, and INT4 can operate. Only INT0 can not operate. CPU No operation Release Signal An interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the RESET input. An interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the RESET input. *: Operation is possible only when the main system clock is operating. 36 µPD75048 9. RESET FUNCTION When the RESET signal is input, the µPD75048 is reset and each hardware is initialized as indicated in Table 9-1. Fig. 9-1 shows the reset operation timing. Wait (31.3ms/4.19MHz) RESET input Operation mode or standby mode HALT mode Operation mode Internal reset operation Fig. 9-1 Reset Operation by RESET Input Table 9-1 Status of Each Hardware after Reset (1/2) Hardware RESET Input in Standby Mode RESET Input During Operation The contents of the lower 5 bits of address 0000H of the program memory are set to PC12-8, and the contents of address 0001H are set to PC7-0. The contents of the lower 5 bits of address 0000H of the program memory are set to PC12-8, and the contents of address 0001H are set to PC7-0. Retained Undefined Skip Flag (SK0-2) 0 0 Interrupt Status Flag (IST0) 0 0 The contents of bit 7 of address 0000H of the program memory is set to MBE. The contents of bit 7 of address 0000H of the program memory is set to MBE. Stack Pointer (SP) Undefined Undefined Data Memory (RAM) Retained * Undefined Program Counter (PC) PSW Carry Flag (CY) Bank Enable Flag (MBE) Data Memory EEPROM (EEPROM) EEPROM Write Control Register General-Purpose Register (X, A, H, L, D, E, B, C) Bank Selection Register (MBS) Basic Interval Counter (BT) Timer Mode Register (BTM) Timer/Event Counter Counter (T0) Modulo Register (TMOD0) Mode Register (TM0) TOE0, TOUT F/F Watch Timer Mode Register (WM) Contents of address being written is undefined. Contents of address being written is undefined. 0 0 Retained Undefined 0 0 Undefined Undefined 0 0 0 0 FFH FFH 0 0 0, 0 0, 0 0 0 *: The data at the addresses 0F8H-0FDH of data memory is undefined by RESET input. 37 µPD75048 Table 9-1 Status of Each Hardware after Reset (2/2) Hardware Serial Interface Clock Generator, Clock Output Circuit Shift Register (SIO) Interrupt Function Digital Port Retained Undefined 0 0 SBI Control Register (SBIC) 0 0 Slave Address Register (SVA) Retained Undefined Processor Clock Control Register (PCC) 0 0 System Clock Control Register (SCC) 0 0 Clock Output Mode Register (CLOM) 0 0 IRQ1, IRQ2, IRQ4 Undefined Undefined Other than above 0 0 Interrupt Enable Flag (IExxx) 0 0 Interrupt Master Enable Flag (IME) 0 0 INT0, INT1, INT2 Mode Registers (IM0, IM1, IM2) 0, 0, 0 0, 0, 0 Output Buffer Off Off Output Latch Clear (0) Clear (0) Input/Output Mode Register (PMGA, PMGB, PMGC) 0 0 Pull-up Resistor Specification Register (POGA, POGB) 0 0 Pull-down Resistor Specification Register (PDGB) 0 0 FFH FFH 0 0 Multi-Function Counter (MFTL) Timer Counter (MFTH) Mode Register (MFTM) 0 0 Control Register (MFTC) 0 0 04H 04H Retained Undefined Retained Undefined A/D Converter Mode Register (ADM) SA Register (SA) Bit sequential buffer (BSB0-3) 38 RESET Input During Operation Operation Mode Register (CSIM) Interrupt request flag (IRQxxx) ★ RESET Input in Standby Mode µPD75048 10. INSTRUCTION SET (1) Operand representation and description Describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to RA75X Assembler Package User's Manual - Language (EEU-730). With some instructions, only one operand should be selected from several operands. The uppercase characters, +, and - are keywords and must be described as is. Describe an appropriate numeric value or label as immediate data. The symbols of the register flags can be described in the places of mem, fmem, pmem, and bit. (For details, refer to µPD75048 User's Manual (IEU-704). However, fmem and pmem restricts the label that can be described. Representation Description reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 XA, BC, DE, HL BC, DE, HL BC, DE rpa rpa1 HL, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem* bit 8-bit immediate data or label 2-bit immediate data or label fmem pmem FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label addr caddr faddr 0000H to 1F7FH immediate data or label 12-bit immediate data or label 11-bit immediate data or label taddr 20H to 7FH immediate data (where bit0=0) or label PORTn IExxx PORT0 to PORT11 IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW, IEMFT, IEEE, IEOW MB0, MB1, MB4, MB5, MB6, MB7, MB15 MBn *: Only even addresses can be described as mem for 8-bit data processing. 39 µPD75048 (2) Legend of operation field A : A register; 4-bit accumulator B : B register; 4-bit accumulator C : C register; 4-bit accumulator D : D register; 4-bit accumulator E : E register; 4-bit accumulator H : H register; 4-bit accumulator L : L register; 4-bit accumulator X : X register; 4-bit accumulator XA : Register pair (XA); 8-bit accumulator BC : Register pair (BC); 8-bit accumulator DE : Register pair (DE); 8-bit accumulator HL : Register pair (HL); 8-bit accumulator PC : Program counter SP : Stack pointer CY : Carry flag; or bit accumulator PSW : Program status word MBE : Memory bank enable flag PORTn : Port n (n = 0 to 11) 40 IME : Interrupt master enable flag IExxx : Interrupt enable flag MBS : Memory bank selector register PCC . : Processor clock control register (xx) : Contents addressed by xx xxH : Hexadecimal data : Delimiter of address and bit µPD75048 (3) Symbols in addressing area field *1 MB = MBE . MBS (MBS = 0, 1, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) *4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 addr = 0000H-1F7FH *7 addr = (Current PC) -15 to (Current PC) - 1 (Current PC) +2 to (Current PC) + 16 *8 caddr = 0000H-0FFFH (PC12 = 0) or 1000H-1F7FH (PC12 = 1) *9 faddr = 0000H-07FFH *10 taddr = 0020H-007FH MB = MBE . MBS *11 (MBS = 0, 1, 4, 5, 6, 7, 15) *12 MBE = 0: MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1: MB = MBS (MBS = 0, 1, 4, 5, 6, 7, 15) Remarks 1: Data memory addressing Program memory addressing Data memory addressing MB indicates memory bank that can be accessed. 2: In *2, MB = 0 regardless of MBE and MBS. 3: In *4 and *5, MB = 15 regardless of MBE and MBS. 4: *6 to *10 indicate areas that can be addressed. 5: When MBS is 4, 5, 6 or 7, addressing area is in the EEPROM area. (4) Machine cycle field In this field, S indicates the number of machine cycles required when an instruction having a skip function skips. The value of S varies as follows: • When no instruction is skipped .................................................................................. S = 0 • When 1-byte or 2-byte instruction is skipped ........................................................... S = 1 • When 3-byte instruction (BR !addr or CALL !addr) is skipped .............................. S = 2 Note : The GETI instruction is skipped in one machine cycle. One machine cycle equals to one cycle of the CPU clock Φ, (=tCY), and can be changed in three steps depending on the setting of the processor clock control register (PCC). 41 µPD75048 Instructions Mnemonics Transfer MOV 1 1 A ← n4 reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String effect A HL, #n8 2 2 HL ← n8 String effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *11 A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *11 @HL, A 1 1 (HL) ← A *11 @HL, XA 2 2 (HL) ← XA *11 A,mem 2 2 A ← (mem) *12 XA, mem 2 2 XA ← (mem) *12 mem, A 2 2 (mem) ← A *12 *12 mem, XA 2 2 (mem) ← XA A, reg 2 2 A ← reg XA, rp 2 2 XA ← rp reg1, A 2 2 reg1 ← A rp1, XA 2 2 rp1 ← XA 1 1 A ↔ (HL) 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *11 A, mem 2 2 A ↔ (mem) *12 XA, mem 2 2 XA ↔ (mem) *12 A, reg1 1 1 A ↔ reg1 XA, rp 2 2 XA ↔ rp MOVT XA, @PCDE 1 3 XA ← (PC12-8+DE)ROM XA, @PCXA 1 3 ADDS A, #n4 1 1+S A ← A+n4 A, @HL 1 1+S A ← A+(HL) carry *11 *11 *11 1 A, CY ← A-(HL)-CY *11 2 A ← A ∧ n4 1 1 A ← A ∧ (HL) A, @HL 1 1 SUBS A, @HL 1 1+S SUBC A, @HL 1 AND A, #n4 2 A, @HL XOR XA ← (PC12-8+XA)ROM A ← A-(HL) ADDC tion OR *11 A, CY ← A+(HL)+CY Opera- A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) Accumu- RORC lator A 1 1 CY ← A0, A3 ← CY, An-1 ← An Manipu- NOT lation A 2 2 A←A 42 String effect A 1 metic Skip Conditions A, #n4 A, @HL Reference Arith- Operation Addressing Area A, @rpa1 XCH Table Operand Machine Bytes Cycles *11 *11 *11 carry borrow µPD75048 Instructions Mnemonics Incre- INCS ment/ Decrement DECS Compare SKE Operand Machine Bytes Cycles Operation Addressing Area Skip Conditions reg 1 1+S reg ← reg+1 @HL 2 2+S (HL) ← (HL)+1 *11 mem 2 2+S (mem) ← (mem)+1 *12 reg 1 1+S reg reg, #n4 2 2+S Skip if reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 *11 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *11 A = (HL) Skip if A = reg reg = 0 ← reg-1 (HL) = 0 (mem) = 0 reg = FH reg = n4 A, reg 2 2+S Carry SET1 CY 1 1 CY ← 1 flag CLR1 CY 1 1 CY ← 0 Manipu- SKT CY 1 1+S lation CY 1 1 CY ← CY mem.bit 2 2 (mem.bit) ← 1 Bit fmem.bit 2 2 (fmem.bit) ← 1 *4 Manipu- pmem.@L 2 2 (pmem7-2 + L3-2.bit(L 1-0)) ← 1 *5 @H+mem.bit 2 2 (H + mem 3-0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem.@L 2 2 (pmem 7-2 + L3-2 .bit(L1-0) ← 0 *5 @H+mem.bit 2 2 (H+mem3-0.bit) ← 0 *1 mem.bit 2 2+S Skip if(mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+S Skip if(fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if(pmem7-2 +L3-2.bit (L1-0 )) = 1 *5 (pmem.@L) = 1 NOT1 Memory/ SET1 lation CLR1 SKT SKF OR1 XOR1 Skip if CY = 1 CY = 1 *3 @H+mem.bit 2 2+S Skip if(H + mem3-0 .bit) = 1 *1 (@H+mem.bit) = 1 mem.bit 2 2+S Skip if(mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if(fmem.bit) = 0 *4 (fmem.bit) = 0 (pmem.@L) = 0 pmem.@L 2 2+S Skip if(pmem7-2 +L3-2 .bit (L1-0)) = 0 *5 @H+mem.bit 2 2+S Skip if (H + mem 3-0.bit) = 0 *1 (@H+mem.bit) = 0 2 2+S Skip if(fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if(pmem 7-2+L3-2.bit (L1-0)) = 1 and clear *5 (pmem.@L) = 1 (@H+mem.bit) = 1 SKTCLR fmem.bit AND1 A = reg @H+mem.bit 2 2+S Skip if (H+mem3-0.bit) = 1 and clear *1 CY,fmem.bit 2 2 CY ← CY ∧ (fmem.bit) *4 CY,pmem.@L 2 2 CY ← CY ∧ (pmem7-2+L 3-2.bit(L1-0)) *5 CY,@H+mem.bit 2 2 CY ← CY ∧ (H+mem 3-0.bit) *1 CY,fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY,pmem.@L 2 2 CY ← CY ∨ (pmem7-2+L 3-2.bit (L1-0)) *5 CY,@H+mem.bit 2 2 CY ← CY ∨ (H+mem 3-0.bit) *1 CY,fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY,pmem.@L 2 2 CY ← CY ∨ (pmem7-2+L 3-2.bit (L1-0)) *5 CY,@H+mem.bit 2 2 CY ← CY ∨ (H+mem 3-0.bit) *1 43 µPD75048 Instructions Mnemonics Branch BR — PC 12-0 ← addr (The most suitable instruction is selectable from among BR !addr, BRCB !caddr, and BR $addr depending on the assembler.) *6 !addr 3 3 PC 12-0 ← addr *6 $addr 1 2 PC 12-0 ← addr *7 !caddr 2 2 PC 12-0 ← PC12 + caddr11-0 *8 !addr 3 3 (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE,0, 0, PC12 PC 12-0 ← addr,SP ← SP-4 *6 !faddr 2 2 (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE,0, 0, PC12 PC 12-0 ← 00,faddr,SP ← SP-4 *9 RET 1 3 MBE,x,x,PC 12 ← (SP+1) PC 11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4 RETS 1 3+S MBE,x,x,PC 12 ← (SP+1) PC 11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4, then skip unconditionally RETI 1 3 MBE,x,x,PC 12 ← (SP+1) PC 11-0 ← (SP)(SP+3)(SP+2) PSW ← (SP+4)(SP+5), SP ← SP+6 rp 1 1 (SP-1)(SP-2) ← rp, SP ← SP-2 BS 2 2 (SP-1) ← MBS,(SP-2) ← 0,SP ← SP-2 rp 1 1 rp ← (SP+1)(SP),SP ← SP+2 BS 2 2 MBS ← (SP+1),SP ← SP+2 2 2 IME ← 1 IExxx 2 2 IExxx ← 1 IME ← 0 PUSH POP EI rupt I/O Operation — Subrou- CALL tine/ Stack Control CALLF Control Addressing Area addr BRCB Inter- Operand Machine Bytes Cycles DI IN OUT 2 2 IExxx 2 2 IExxx ← 0 A,PORTn 2 2 A ← PORTn (n = 0-11) XA,PORTn 2 2 XA ← PORTn+1,PORTn (n = 4, 6) PORTn,A 2 2 PORT n ← A (n = 2-10) PORTn,XA 2 2 PORT n+1,PORTn ← XA (n = 4, 6) CPU HALT 2 2 Set HALT Mode(PCC.2 ← 1) Control STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP Special 1 1 No Operation SEL MBn 2 2 GETI taddr 1 3 MBS ← n(n=0, 1, 4, 5, 6, 7, 15) . Where TBR instruction, PC12-0 ← (taddr)4-0+(taddr+1) . Where TCALL instruction, (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, 0, 0, PC12 PC12-0 ← (taddr)4-0+(taddr+1) SP ← SP-4 . Except for TBR and TCALL instructions, Instruction execution of (taddr)(taddr+1) Skip Conditions Unconditional *10 Depends on referenced instruction Note : When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15. ★ Remarks : TBR and TCALL instructions are assembler seudo-instructions for the table definition of GETI instruction. 44 µPD75048 11. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25°C) Parameter Symbol Conditions Supply Voltage VDD Input Voltage VI1 Other than ports 4, 5, 10 VI2 Ports 4, 5, 10 Ratings w/pull-up resistor -0.3 to +7.0 V -0.3 to VDD +0.3 V -0.3 to VDD +0.3 Open drain Output Voltage VO High-Level Output Current IOH Low-Level Output IOL* Current Unit -0.3 to +11 V V -0.3 to VDD +0.3 V 1 pin -10 mA All pins -30 mA Ports 0, 3, 4, 5 1 pin Peak 30 mA rms 15 mA Other than ports 0, 3, 4, 5 1 pin Peak 20 mA rms 5 mA Total of ports 0, 3 - 9, 11 Peak 170 mA rms 120 mA Total of ports 0, 2, 10 Peak 30 mA rms 20 mA Operating Temperature Topt -10 to +70 °C Storage Temperature T stg -65 to +150 °C *: rms = Peak value x √Duty Note: Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product. EEPROM RATINGS (T a = -10 to +70°C, VDD = 2.7 to 6.0 V) Parameter Symbol µ Conditions Write Times — 100,000 times Data Retention Time — 10 years CAPACITANCE (Ta = 25°C, VDD = 0 V) Parameter Symbol Input Capacitance CI Output Capacitance CO Input/Output CIO Conditions f = 1 MHz Pins other than thosemeasured are at 0 V MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF 45 ★ µPD75048 MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -10 to +70°C, VDD = 2.7 to 6.0 V) Oscillator Recommended Constants Ceramic Item Oscillation frequency(f X)* 1 X1 X2 C1 C2 Conditions VDD = oscillation voltage range MIN. TYP. 2.0 MAX. 5.0 Oscillation stabiliza- After VDD come to MIN. value of tion time* 2 oscillation voltage range *3 4 Unit MHz ms VDD Crystal X1 Oscillation frequency (f X)* 1 X2 2.0 4.19 Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time* 2 C1 5.0 *3 MHz 10 ms 30 ms C2 VDD External Clock X1 input frequency (f X)*1 X1 X2 X1 input high-, low-level widths (t XH , tXL) 2.0 100 5.0 *3 250 MHz ns mPD74HCU04 *1: Only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after VDD has reached the minimum volue of the oscillation voltage range or the STOP mode has been released. 3: When the oscillation frequency is 4.19 MHz < fx ≤ 5.0 MHz, do not select PCC = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 µ s, falling short of the rated minimum value of 0.95 µ s. ★ Note: When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: • Keep the wiring length as short as possible. • Do not cross the wiring over the other signal lines. • Do not route the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD . Do not connect the ground pattern through which a high curent flows. • Do not extract signals from the oscillation circuit. 46 µPD75048 SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -10 to +70°C, VDD = 2.7 to 6.0 V) Oscillator Recommended Constants Crystal XT1 Conditions Oscillation frequency (fXT)* 1 XT2 R C3 Item MIN. TYP. MAX. 32 32.768 35 kHz 1.0 2 ms 10 ms 32 100 kHz 5 15 µs Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*2 C4 Unit VDD External Clock XT1 input frequency (f XT)*1 XT1 XT2 XT1 input high-, low-level widths (t XTH, tXTL ) *1: Indicates only the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after VDD has reached the minimum value of the oscillation voltage range. Note: When using the oscillation circuit of the subsystem clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: • Keep the wiring length as short as possible. • Do not cross the wiring over the other signal lines. • Do not route the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD. Do not connect the ground pattern through which a high current flows. • Do not extract signals from the oscillation circuit. The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit. When using the subsystem clock, therefore, exercise utmost care in wiring the circuit. 47 ★ µPD75048 DC CHARACTERISTICS (Ta = -10 to +70°C, VDD = 2.7 to 6.0 V) Parameter High-Level Input Voltage Low-level Input Voltage Symbol 0.7VDD VDD V 0.8VDD VDD V VIH3 Ports 4,5,10 w/pull-up resistor 0.7VDD VDD V Open-drain 0.7V DD 10 V VDD-0.5 VDD V V VIH4 X1, X2, XT1, XT2 VIL1 Ports 2-5, 8-11 0 0.3V DD VIL2 Ports 0, 1, 6, 7, RESET 0 0.2VDD V VIL3 X1, X2, XT1, XT2 0 0.4 V ILIH1 VDD-1.0 V VDD-0.5 V Ports 3,4,5 VDD = 4.5 to 6.0V, IOL = 15mA 0.4 2.0 V VDD = 4.5 to 6.0V, IOL = 1.6 mA 0.4 V IOL = 400 µA 0.5 V 0.2V DD V SB0, 1 Open-drain pull-up resistor ≥ 1 kΩ VI = V DD Other than below 3 µA X1,X2,XT1 20 µA ILIH3 VI = 9V Ports 4,5,10 (open-drain) 20 µA ILIL1 VI = 0V Other than below -3 µA X1,X2,XT1 -20 µA ILOH1 VO = VDD Other than below 3 µA ILOH2 VO = 9V Ports 4,5,10 (open-drain) 20 µA ILOL VO = 0V -3 µA 80 kΩ ILIL2 RU2 48 VDD = 4.5 to 6.0V, IOH = -1 mA IOH = -100 µA ILIH2 Internal Pull-Up Resistor RU1 Internal Pull-Down Resistor Unit Ports 0,1,6,7, RESET VOL Low-Level Output Leakage Current MAX. Ports 2,3,8,9,11 Low-Level Output Voltage High-Level Output Leakage Current TYP. VIH1 VOH Low-Level Input Leakage Current MIN. VIH2 High-Level Output Voltage High-Level Input Leakage Current Conditions RD Ports 0,1,2,3,6,7,8 VDD = 5.0V±10% (except P00) VI = 0V VDD = 3.0V±10% 15 40 30 Ports 4,5,10 VO = VDD -2.0 V VDD = 5.0V±10% 15 VDD = 3.0V±10% 10 Port 9 VIN = VDD VDD = 5.0V±10% 15 VDD = 3.0V±10% 10 40 40 300 kΩ 70 kΩ 60 kΩ 70 kΩ 60 kΩ µPD75048 Parameter Symbol Supply Current *1 IDD1 IDD2 IDD3 TYP. MAX. Unit 4.19MHz crystal Conditions VDD = 5V±10%*2 3.5 10 mA oscillator VDD = 3V±10%*3 0.65 1.8 mA C1 = C2 = 22pF HALT mode VDD = 5V±10% 800 2400 µA VDD = 3V±10% 350 1000 µA 70 210 µA 20 60 µA 32.768kHz*4 crystal oscillator IDD4 IDD5 MIN. Operation mode VDD = 3V±10% HALT mode VDD = 3V±10% XT1 = 0V VDD = 5V±10% 0.5 20 µA STOP mode VDD = 3V±10% 0.3 10 µA 5 µA 20 µA Ta = 25°C IDD6 32.768kHz oscillator VDD = STOP mode 3V±10%*5 6 *1: Current flowing through internal pull-up resistor. Current flowing when EEPROM is accessed is not included. 2: When µPD75048 operates in high-speed mode with processor clock control register (PCC) set to 0011. 3: When µ PD75048 operates in low-speed mode with PCC set to 0000. 4: When the system clock control register (SCC) is set to 1001, the oscillation of the main system clock is stopped, and the subsystem clock is used. 5: When STOP instruction is executed with SCC set to 0000. Note: Supply current when EEPROM is accessed is shown in EEPROM Characteristics. 49 µPD75048 AC CHARACTERISTICS (T a = -10 to +70°C, VDD = 2.7 to 6.0 V) Parameter Symbol Conditions w/main system clock MIN. VDD = 4.5-6.0V TYP. MAX. Unit 0.95 32 µs 3.8 32 µs 125 µs CPU Clock Cycle Time (Minimum Instruction Execution Time = 1 Machine Cycle)*1 tCY TI0 Input Frequency fTI V DD = 4.5 to 6.0 V 0 1 MHz 0 275 kHz TI0 Input High-, LowLevel Widths tTIH , tTIL V DD = 4.5 to 6.0 V 0.48 µs 1.8 µs Interrupt Input High-, Low-Level Widths tINTH , tINTL INT0 *2 µs INT1, 2, 4 10 µs 10 µs RESET Low-Level Width tRSL 10 µs w/subsystem clock 114 KR0-7 122 *1: The CPU clock (Φ) cycle time is determined by the oscillation frequency of the tCY vs VDD connected oscillator, system clock control (with main system clock) register (SCC), and processor clock control register (PCC). 32 The figure on the right is cycle time tCY vs. supply voltage VDD characteristics at 6 the main system clock. 5 *2: 2tCY or 128/fX depending on the setting of 4 m Cycle time tCY [[µs] s] the interrupt mode register (IM0). Operation guaranteed range 3 2 1 0.5 0 1 2 3 4 Supply voltage VDD [V] 50 5 6 µPD75048 SERIAL TRANSFER OPERATION Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output) Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol tKCY1 tKL1 Conditions MIN. VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V TYP. MAX. Unit 1600 ns 3800 ns tKCY1/2-50 ns tKH1 tKCY1/2-150 ns SI Set-Up Time (vs. SCK ↑) tSIK1 150 ns SI Hold Time (vs. SCK ↑ ) tKSI1 SCK ↓→ SO Output Delay Time tKSO1 400 RL = 1kΩ, C L = 100pF* ns VDD = 4.5 to 6.0V 250 ns 1000 ns MAX. Unit TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input) Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol tKCY2 tKL2 Conditions VDD = 4.5 to 6.0V VDD = 4.5 to 6.0V MIN. TYP. 800 ns 3200 ns 400 ns tKH2 1600 ns SI Set-Up Time (vs. SCK ↑) tSIK2 100 ns SI Hold Time (vs. SCK ↑) tKSI2 SCK ↓→ SO Output Delay Time tKSO2 400 RL = 1kΩ, C L = 100 pF* VDD = 4.5 to 6.0V ns 300 ns 1000 ns *: RL and C L are load resistance and load capacitance of the SO output line. 51 µPD75048 SBI MODE (SCK: internal clock output (master)) Parameter SCK Cycle Time Symbol tKCY3 SCK High-, Low-Level Widths tKL3 tKH3 SB0, 1 Set-Up Time (vs. SCK ↑ ) tSIK3 SB0, 1 Hold Time (vs. SCK ↑ ) tKSI3 SCK ↓→ SB0, 1 Output Delay Time tKSO3 Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V RL = 1kΩ, C L = 100pF* VDD = 4.5 to 6.0V MIN. TYP. MAX. Unit 1600 ns 3800 ns tKCY3/2-50 ns tKCY3/2-150 ns 150 ns tKCY3/2 ns 0 250 ns 0 1000 ns SCK ↑→ SB0, 1 ↓ tKSB tKCY3 ns SB0,1 ↓→ SCK tSBK tKCY3 ns SB0, 1 Low-Level Width tSBL tKCY3 ns SB0, 1 High-Level Width tSBH tKCY3 ns SBI MODE (SCK: external clock input (slave)) Parameter Symbol Conditions SCK Cycle Time tKCY4 VDD = 4.5 to 6.0 V SCK Ligh-, Low-Level Widths tKL4 tKH4 VDD = 4.5 to 6.0 V SB0, 1 Set-Up Time (vs. SCK ↑ ) MIN. TYP. MAX. ns 3200 ns 400 ns 1600 ns tSIK4 100 ns SB0, 1 Hold Time (vs. SCK ↑ ) tKSI4 tKCY4/2 ns SCK ↓→ SB0, 1 Output Delay Time tKSO4 SCK ↑→ SB0, 1 ↓ tKSB tKCY4 ns SB0,1 ↓→ SCK ↓ tSBK tKCY4 ns SB0, 1 Low-Level Width tSBL tKCY4 ns SB0, 1 High-Level Width tSBH tKCY4 ns RL = 1kΩ, C L = 100pF* VDD = 4.5 to 6.0V 0 300 0 1000 *: RL and C L are load resistance and load capacitance of the SB0 and SB1 output lines. 52 Unit 800 ns ns µPD75048 A/D CONVERTER (Ta = -10 to +70°C, VDD = 2.7 to 6.0V, AVSS = VSS = 0V) Parameter Symbol Conditions Resolution MIN. TYP. 8 8 2.5V ≤ AVREF ≤ VDD Absolute Accuracy* 1 MAX. Unit 8 bit ±1.5 LSB Conversion Time*2 tCONV 168/fX µs Sampling Time*3 tSAMP 44/f X µs Analog Input Voltage VIAN AVREF+ V Analog Supply Voltage AVDD 2.5 VDD V Reference Input Voltage AVREF+ 2.5V ≤ (AVref+) – (AV ref-) 2.5 AVDD V Reference Input Voltage AVREF- 2.5V ≤ (AVref+) – (AV ref-) 0 1.0 V AVREF- Analog Input Impedance RAN 1000 AVREF Current AIREF 0.25 *1: Absolute accuracy excluding quantization error (± MΩ 2.0 mA 1 –2 LSB) 2: Time since execution of conversion start instruction until end of conversion (EOC = 1) (40.1 µs: fX = 4.19 MHz) 3: Time since execution of conversion start instruction until end of sampling (10.5 µ s: fX = 4.19 MHz) 53 µPD75048 AC TIMING TEST POINT (excluding X1 and XT1 inputs) 0.8 VDD 0.8 VDD Test points 0.2 VDD 0.2 VDD CLOCK TIMING 1/fX tXL tXH X1 input VDD –0.5V 0.4 V 1/fXT tXTL tXTH XT1 input VDD –0.5V 0.4 V TI0 TIMING 1/fTI tTIL TI0 54 tTIH µPD75048 SERIAL TRANSFER TIMING THREE-LINE SERIAL I/O MODE: tKCY1 tKL1 tKH1 SCK tSIK1 SI tKSI1 Input data tKS01 Output data SO TWO-LINE SERIAL I/O MODE: tKCY2 tKH2 tKL2 SCK tSIK2 tKSI2 SB0,1 tKSO2 55 µPD75048 SERIAL TRANSFER TIMING BUS RELEASE SIGNAL TRANSFER: t KCY3,4 tKL3,4 tKH3,4 SCK tKSB tSBL tSBH tSIK3,4 tSBK SB0,1 tKS03,4 COMMAND SIGNAL TRANSFER: tKCY3,4 tKL3,4 tKH3,4 SCK tKSB tSIK3,4 tSBK SB0,1 tKS03,4 INTERRUPT INPUT TIMING tINTL INT0, 1, 2, 4 KR0-7 RESET INPUT TIMING tRSL RESET 56 tINTH tKSI3,4 tKSI3,4 µPD75048 EEPROM CHARACTERISTICS Parameter Symbol Supply current for EEPROM access*1 IDD7 Conditions MIN. 5V+10%*2 4.19MHz crystal oscillator V DD = C1 = C = 22pF V DD = 3V+10%*3 TYP. MAX. Unit 6.5 20 mA 2 6 mA *1: Current flowing through the internal pull-up resistor is not included. 2: When the processor clock control register (PCC) is set to 0011 and the high-speed mode is used. 3: When PCC is set to 0000 and the low-speed mode is used. EEPROM WRITE TIME Select the write time of the EEPROM in accordance with the oscillation frequency of the main system clock as follows: Oscillation Frequency of Main System Clock (fX) Setting of EEPROM Control Register Write time EWTC1 EWTC0 fX = 2.0 to 5.0 MHz 0 0 212 x 18/fX (17.6 ms) fX = 2.0 to 4.2 MHz 0 1 211 x 18/fX (8.8 ms) fX = 2.0 MHz 1 0 210 x 18/fX Remarks: ( ): fX = 4.19 MHz LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (Ta = –10 to +70°C) Parameter Symbol Data Retention Supply Voltage VDDDR Data Retention Supply Current*1 IDDDR Release Signal Set Time tSREL Oscillation Stabilization Wait Time*2 tWAIT Conditions MIN. TYP. 2.0 VDDDR = 2.0 V 0.1 MAX. Unit 6.0 V 10 µA µs 0 Released by RESET Released by interrupt request 2 17/fX ms *3 ms *1: Does not include current flowing through internal pull-up resistor 2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3: Depends on the setting of the basic interval timer mode register (BTM) as follows: BTM3 BTM2 BTM1 BTM0 – 0 0 0 220/fX (approx. 250 ms) WAIT time ( ): fX = 4.19 MHz – 0 1 1 217/fX (approx. 31.3 ms) – 1 0 1 215/fX (approx. 7.82 ms) – 1 1 1 213/fX (approx. 1.95 ms) 57 µPD75048 DATA RETENTION TIMING (releasing STOP mode by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt) HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 58 µPD75048 12. PERFORMANCE CURVE IDD vs VDD (Crystal oscillation) (T a = 25 °C) 10 5.0 High-speed mode PCC = 0011 Medium-speed mode PCC = 0010 Low-speed mode PCC = 0000 Main system clock HALT mode 1.0 0.5 Supply current IDD (mA) Subsystem clock Operation mode 0.1 With main system clock stopped Subsystem clock HALT mode 0.05 Main system clock STOP mode Subsystem clock oscillation 0.01 X1 0.005 22 pF 0.001 0 1 2 3 4 5 X2 XT1 XT2 Crystal Crystal 4.19 MHz 32.768 kHz 22 pF 22 pF V DD V DD 6 330 kΩ 22 pF 7 Supply voltage VDD (V) 59 µPD75048 IDD vs VDD (Crystal oscillation) (T a = 25 °C) 10 5.0 High-speed mode PCC = 0011 Medium-speed mode PCC = 0010 Low-speed mode PCC = 0000 1.0 Main system clock HALT mode 0.5 Supply current IDD (mA) Subsystem clock Operation mode 0.1 With main system clock stopped Subsystem clock HALT mode 0.05 Main system clock STOP mode Subsystem clock oscillation 0.01 X1 0.005 22 pF 0.001 0 1 2 3 4 Supply voltage VDD (V) 60 5 X2 XT1 XT2 Crystal Crystal 2.0 MHz 32.768 kHz 22 pF 22 pF V DD V DD 6 330 kΩ 22 pF 7 µPD75048 13. PACKAGE DRAWINGS 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 32 A K H G J I L F D N M NOTE B C M ITEM MILLIMETERS R INCHES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. A 58.68 MAX. 2.311 MAX. B 1.78 MAX. 0.070 MAX. 2) Item "K" to center of leads when formed parallel. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K 19.05 (T.P.) 0.750 (T.P.) L 17.0 0.669 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15° 0~15° P64C-70-750A,C-1 61 µPD75048 64 PIN PLASTIC QFP ( 14) A B 33 32 48 49 F Q 5°±5° S C D detail of lead end 64 1 G 17 16 H I M J M P K N L P64GC-80-AB8-3 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. 62 ITEM MILLIMETERS INCHES A 17.6 ± 0.4 0.693 ± 0.016 B 14.0 ± 0.2 0.551+0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 1.0 0.039 G 1.0 0.039 H 0.35 ± 0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.8 ± 0.2 0.071 ± 0.008 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.10 0.004 P 2.55 0.100 Q 0.1 ± 0.1 0.004 ± 0.004 S 2.85 MAX. 0.112 MAX. µPD75048 14. RECOMMENDED SOLDERING CONDITIONS It is recommended that µPD75048 be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). For other soldering methods and conditions, consult NEC. Table 14-1 Soldering Conditions of Surface Mount Type µPD75048GC - xxx - AB8: 64-pin plastic QFP ( Soldering Method *: 14 mm) Soldering Conditions Symbol for Recommended Condition Ware Soldering Soldering bath temperature: 260°C max., time: 10 seconds max., number of times: 1, maximum number of days: 2 days*, (beyond this period, 16 hours of pre-baking is required at 125°C), Pre-heating temperature: 120°C max. WS60-162-1 Infrared Reflow Package peak temperature: 230°C, time: 30 seconds max. (210°C min.), number of times: 1, maximum number of days: 2 days* (beyond this period, 16 hours of pre-baking is required at 125°C) IR30-162-1 VPS Package peak temperature: 215°C, time: 40 seconds max. (200°C min.), number of times: 1, maximum number of days: 2 days* (beyond this period, 16 hours of pre-baking is required at 125°C) VP15-162-1 Pin Partial Heating Pin temperature: 300°C max., time: 3 seconds max. (per side) — Number of days after unpacking the dry pack. Storage conditions are 25°C and 65%RH max. Note: Do not use two or more soldering methods in combination (except the pin partial heating method). Table 14-2 Soldering Conditions of Through-Hole Type µPD75048CW - xxx: 64-pin plastic shrink DIP (750 mil) Soldering Method Soldering Conditions Wave soldering (lead parts only) Soldering bath temperature: 260°C max., time: 10 seconds max., Pin Partial Heating Pin temperature: 260oC max., time: 10 seconds max. Caution: The wave soldering must be performed at the lead part only. Note that the soldering must not be directly contacted to the board. Notice A model that can be soldered under the more stringent conditions (infrared reflow peak temperature: 235°C, numbver of times:2, and an extended number of days) is also available. For details, consult NEC. 63 µPD75048 APPENDIX A. DIFFERENCES BETWEEN µPD75048 AND 75028/75008 FUNCTIONS µPD75048 Item µPD75028 ROM (bytes) µPD75008 8064 RAM (x4 bits) 512 EEPROM (x4 bits) 1024 None Instruction Main System Clock 0.95 µs, 1.91 µs, 15.3 µs (4.19 MHz) Cycle Subsystem Clock I/O Port CMOS Input CMOS I/O N-ch OpenDrain I/O A/D Converter 122µs (32.768 kHz) 12 • Pull-up via software: 27 (except P00) 48 24 • Pull-down via software: 4 • 8-bit resolution x 8 channels • Low-voltage operation: VDD = 2.7 - 6.0 1 ch Vector Interrupt 34 18 (except P00) 12 (10 V, pull-up by mask option) 16-bit Multifunction Timer • • • • 8-bit timer mode PWM output mode 16-bit free running timer mode 16-bit integral A/D converter mode External: 3, Internal: 6 Test Input 8 Pull-up via software External: 3, Internal: 4 8 (10 V, pull-up by mask option) None None External: 3, Internal: 3 External: 1, Internal: 1 Buzzer Output (BUZ) 2 kHz, 4 kHz, 32 kHz (at 4.19 MHz, 32.768 kHz operation) 2 kHz (at 4.19 MHz, 32.768 kHz operation) Package • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP ( Supply Voltage • 42-pin plastic shrink DIP (600 mil) • 44-pin plastic QFP ( 10 mm) 14 mm) VDD = 2.7 - 6.0 V Operating Temperature -10 to +70°C -40 to +70°C -40 to +85°C PROM Model µPD75P048 µPD75P036 µPD75P008 64 ★ µPD75048 APPENDIX B. DEVELOPMENT TOOLS The following development tools are readily available to support development of systems using µPD75048: Hardware IE-75000-R*1 In-circuit emulator for 75X series IE-75001-R IE-75000-R-EM*2 Emulation board for IE-75000-R and IE-75001-R EP-75028CW-R Emulation prove for µPD75048 EP-75028GC-R EV-9200GC-64 Emulation prove for µPD75048, provided with EV-9200GC-64, 64-pin conversion socket PG-1500 PROM programmer PA-75P036GC PROM programmer adapter solely used for µPD75P048GC. It is connected to PG-1500. PA-75P036CW PROM programmer adapter solely used for µPD75P048CW. It is connected to PG-1500. Software IE Control Program Host machine PG-1500 Controller PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00A*3) RA75X Relocatable IBM PC/ATTM (PC DOS TM Ver. 3.1) Assembler *1: Maintenance product 2: Not provided with IE-75001-R. 3: Ver. 5.00/5.00A has a task swap function, but this function cannot be used with this software. Remarks : For development tools from other companies, refer to 75X Series Selection Guide (IF151). 65 µPD75048 [MEMO] 66 µPD75048 GENERAL NOTES ON CMOS DEVICES ➀ STATIC ELECTRICITY (ALL MOS DEVICES) Exercise care so that MOS devices are not adversely influenced by static electricity while being handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge. Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device. Handle boards on which MOS devices are mounted similarly . ➁ PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY) Fix the input level of CMOS devices. Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. Therefore, fix the input level of the device by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to VDD or GND through a resistor. Refer to “Processing of Unused Pins” in the documents of each devices. ➂ STATUS BEFORE INITIALIZATION (ALL MOS DEVICES) The initial status of MOS devices is undefined upon power application. Since the characteristics of an MOS device are determined by the quantity of injection at the molecular level, the initial status of the device is not controlled during the production process. The output status of pins, I/O setting, and register contents upon power application are not guaranteed. However, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. When using a device with a reset function, be sure to reset the device after power application. 67 µPD75048 [MEMO] NEC is manufacturing and selling the products under microcomputer (with on-chip EEPROM) patent license with the BULL CP8. This product should not be used for IC cards (SMART CARD). No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc. M4 92.6 MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation. 68