NEC UPD75336GC

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75336
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD75336 is one of the “75X-series” 4-bit single-chip microcomputers enabled to process data with
performance equivalent to that of 8-bit microcomputers.
The µPD75336 is a microcomputer with an expanded capacity of the ROM and RAM of conventional µPD75328
and an improved 8-bit data processing capacity. It can carry out A/D converter low-voltage operations.
For evaluation purposes for system development or small-quantity production, the µPD75P336 is available which
is a product with the on-chip mask ROM of µPD75336 replaced with a one-time PROM.
Functions are described in detail in the following User’s Manual, which should be read when carrying out design
work.
µPD75336 User’s Manual: IEU-725
FEATURES
• µPD75328 upward compatible
• Instruction execution time variable function useful for high-speed operations and power saving
• 0.95, 1.91, 3.81, 15.3 µs (Main system clock: When operated at 4.19 MHz)
• 122 µ s (Subsystem clock: When operated at 32.768 kHz)
• Memory capacity: µPD75336 ROM: 16256 × 8 bits
RAM:
768 × 4 bits
• On-chip 8-bit resolution A/D converter (successive approximation type): 8 channels
• Low-voltage operation possible: VDD = 2.7 to 6.0 V
• On-chip LCD controller/driver
• Maximum of 20 × 4 segments drive possible
• Improved timer functions: 4 channels
• Improved 8-bit data processing capability
• Transfer, add/subtract, increase/decrease and compare possible
• Ultra-compact package in use (80-pin plastic TQFP (fine pitch)( 12 mm))
• On-chip PROM (µPD75P336) operative at low voltages available
• VDD = 2.7 to 6.0 V
APPLICATIONS
Cameras, VCR integrated cameras, air conditioners, sphygmomanometers, etc.
The information in this document is subject to change without notice.
Document No. IC-2893C
(O.D. No. IC-7972C)
Date Published February 1994 P
Printed in Japan
The mark ★ shows major revised points.
© NEC Corporation 1991
µPD75336
ORDERING INFORMATION
Ordering Code
Package
µ PD75336GC-×××-3B9
µ PD75336GK-×××-BE9
80-pin plastic QFP ( 14 mm)
80-pin plastic TQFP (fine pitch)( 12 mm)
Remarks “×××” is a ROM code number.
QUALITY GRADE
Ordering Code
Package
Quality Grade
µ PD75336GC-×××-3B9
µPD75336GK-×××-BE9
80-pin plastic QFP ( 14 mm)
80-pin plastic TQFP (fine pitch)( 12 mm)
Standard
Standard
Remarks “×××” is a ROM code number.
Please refer to “Quality Grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
2
µPD75336
GENERAL DESCRIPTION OF FUNCTIONS
Item
Function
Instruction execution time
On-chip memory
When main system clock is selected: 0.95, 1.91, 3.81, 15.3 µs (when operated at 4.19 MHz)
When subsystem clock is selected: 122 µs (when operated at 32.768 kHz)
ROM
16256 × 8 bits
RAM
768 × 4 bits
General register
• 4-bit manipulation: 8 × 4 banks
• 8-bit manipulation: 4 × 4 banks
8 pins
I/O line
(The dual function pins
for LCD-drive are included.
The dedicated pins for
LCD-drive are excluded.)
CMOS input/output pin
Use of pull-up resistor enabled
by software (except P00)
8 pins
CMOS output pin
Dual function with segment pins
8 pins
N-ch open-drain input/output
10 V withstand voltage. On-chip
specification of pull-up resistor
enabled by mask option
20 pins
44
CMOS input pins
LCD controller/driver
• Output pins for LCD-drive
• Segment output pins: 20 pins (dual-function pins with CMOS output: 8 pins)
• Common output pins: 4 pins
• Maximum 20 × 4 segment drive
• Display mode selection: Static 1/2, 1/3, 1/4 duties
A/D converter
On-chip 8-bit resolution A/D converter (successive approximation type)
• 8-channel analog input
• Low-voltage operable VDD = 2.7 to 6.0 V
• A/D conversion speed 40.1 µs (when operated at 4.19 MHz)
Timer
4 channels
• 8-bit timer/event counter × 2 channels
• 8-bit basic interval timer
• Watch timer ... 0.5 sec time interval generation, buzzer output possible
(2 kHz, 4 kHz, 32 kHz)
Serial interface
• NEC standard serial bus interface (SBI)
• Clocked serial interface
Bit sequential buffer
Special bit manipulation memory: 16 bits
Clock output (PCL)
Φ, 524 kHz, 262 kHz, 65.5 kHz (when operated at 4.19 MHz)
Buzzer output (BUZ)
2 kHz, 4 kHz, 32 kHz (with main system clock or subsystem clock in operation)
Vectored interrupt
• External: 3
• Internal: 4
Test input
• External: 1
• Internal: 1
8-bit data processing
Transfer, add/subtract, increase/decrease and compare
System clock oscillator
• Ceramic/crystal oscillator for main system clock oscillation : 4.194304 MHz
• Crystal oscillator for subsystem clock oscillation
: 32.768 kHz
Standby
STOP/HALT mode
Operating voltage
VDD = 2.7 to 6.0 V
Package
• 80-pin plastic QFP ( 14 mm)
• 80-pin plastic TQFP (fine pitch)( 12 mm)
3
µPD75336
CONTENTS
1.
PIN CONFIGURATION (TOP VIEW) ......................................................................................................... 5
2.
BLOCK DIAGRAM ...................................................................................................................................... 7
3.
PIN FUNCTIONS ........................................................................................................................................ 8
3.1
PORT PINS .......................................................................................................................................................... 8
3.2
NON-PORT PINS ............................................................................................................................................... 10
3.3
PIN INPUT/OUTPUT CIRCUITS ...................................................................................................................... 12
3.4
MASK OPTION SELECTION ............................................................................................................................ 15
3.5
RECOMMENDED CONNECTION OF UNUSED PINS .................................................................................... 15
4.
MEMORY CONFIGURATION .................................................................................................................. 16
5.
PERIPHERAL HARDWARE FUNCTIONS ................................................................................................ 19
5.1
PORTS ................................................................................................................................................................ 19
5.2
CLOCK GENERATOR ........................................................................................................................................ 20
5.3
CLOCK OUTPUT CIRCUIT ................................................................................................................................ 21
5.4
BASIC INTERVAL TIMER ................................................................................................................................. 22
5.5
WATCH TIMER .................................................................................................................................................. 23
5.6
TIMER/EVENT COUNTER ................................................................................................................................ 24
5.7
SERIAL INTERFACE .......................................................................................................................................... 26
5.8
LCD CONTROLLER/DRIVER ............................................................................................................................ 28
5.9
A/D CONVERTER ............................................................................................................................................. 30
5.10 BIT SEQUENTIAL BUFFER .............................................................................................................................. 31
6.
INTERRUPT FUNCTIONS ........................................................................................................................ 32
7.
STANDBY FUNCTIONS ........................................................................................................................... 34
8.
RESET FUNCTIONS ................................................................................................................................. 35
9.
INSTRUCTION SET .................................................................................................................................. 38
10. ELECTRICAL SPECIFICATIONS .............................................................................................................. 46
11. PACKAGE INFORMATION ...................................................................................................................... 60
12. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 62
APPENDIX A. DIFFERENCES BETWEEN µPD75336 AND µPD75328 FUNCTIONS ................................ 63
APPENDIX B. DEVELOPMENT TOOLS ....................................................................................................... 64
APPENDIX C. RELATED DOCUMENTS ...................................................................................................... 65
4
µPD75336
1. PIN CONFIGURATION (TOP VIEW)
• 80-pin plastic QFP ( 14 mm)
10
11
12
13
14
15
16
17
18
*
AN3
X1
IC*
XT2
XT1
VDD
AVREF
AVSS
AN5
AN4
57
56
55
54
53
52
19
20
2122232425 262728 2930 31323334353637383940
COM0
S12
6
7
8
9
60
59
58
AN2
AN1
AN0
P83/AN7
P82/AN6
P81
P80/TI1
P33
P32
51
50
49
48
47
46
45
44
43
P31/SYNC
P30/LCDCL
P23/BUZ
P22/PCL
P21/PTO1
P20/PTO0
P13/TI0
P12/INT2
P11/INT1
42
41
P10/INT0
P03/SI/SB1
P50
P51
P52
P53
P00/INT4
P01/SCK
P02/SO/SB0
S15
S14
S13
4
5
P40
P41
P42
P43
VSS
S21
S20
S19
S18
S17
S16
2
3
µPD75336GC-×××-3B9
µPD75336GK-×××-BE9
S26/BP2
S25/BP1
S24/BP0
S23
S22
8079787776 757473 7271 70696867666564636261
COM3
BIAS
VLC0
VLC1
VLC2
S29/BP5
S28/BP4
S27/BP3
1
COM1
COM2
S31/BP7
S30/BP6
P62/KR2
P61/KR1
P60/KR0
RESET
X2
P73/KR7
P72/KR6
P71/KR5
P70/KR4
P63/KR3
• 80-pin plastic TQFP (fine pitch)( 12 mm)
Internally connected. Connect the IC PIN to VDD directly.
5
µPD75336
PIN NAMES
P00 to P03
P10 to P13
P20 to P23
P30 to P33
P40 to P43
P50 to P53
P60 to P63
P70 to P73
P80 to P83
BP0 to BP7
KR0 to KR7
AV REF
AV SS
AN0 to AN7
SCK
SI
SO
6
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Bit Port 0 to 7
Key Return 0 to 7
Analog Reference
Analog Ground
Analog Input 0 to 7
Serial Clock
Serial Input
Serial Output
SB0,1
:
RESET
:
S12 to S31
:
COM0 to COM3 :
VLC0 to VLC2
:
BIAS
:
LCDCL
:
SYNC
:
TI0, 1
:
PTO0, 1
:
BUZ
:
PCL
:
INT0, 1, 4
:
INT2
:
X1, 2
:
XT1, 2
:
IC
:
VDD
:
VSS
:
Serial Bus 0, 1
Reset
Segment Output 12 to 31
Common Output 0 to 3
LCD Power Supply 0 to 2
LCD Power Supply Bias Control
LCD Clock
LCD Synchronization
Timer Input 0, 1
Programmable Timer Output 0, 1
Buzzer Clock
Programmable Clock
External Vectored Interrupt 0, 1, 4
External Test Input 2
Main System Clock Oscillation 1, 2
Subsystem Clock Oscillation 1, 2
Internally Connected
Positive Power Supply
Ground
8
A/D
CONVERTER
AVSS
BASIC
INTERVAL
TIMER
INTBT
TIMER/EVENT
COUNTER
#0
TI0/P13
PTO0/P20
PROGRAM
COUNTER (14)
SP(8)
ALU
4
P00-P03
PORT 1
4
P10-P13
PORT 2
4
P20-P23
PORT 3
4
P30-P33
PORT 4
4
P40-P43
PORT 5
4
P50-P53
PORT 6
4
P60-P63
PORT 7
4
P70-P73
PORT 8
4
P80-P83
12
S12-S23
CY
INTT0
BANK
TIMER/EVENT
COUNTER
#1
TI1/P80
PTO1/P21
PORT 0
2. BLOCK DIAGRAM
*
AN0-AN7
AVREF
INTT1
GENERAL REG.
WATCH
TIMER
BUZ/P23
INTW
SI/SB1/P03
f LCD
PROGRAM
MEMORY
(ROM)
16256 × 8 BITS
DECODE
AND
CONTROL
DATA
MEMORY
(RAM)
768 × 4 BITS
CLOCKED
SERIAL
INTERFACE
SO/SB0/P02
SCK/P01
INTCSI
INT0/P10
INT1/P11
INT2/P12
INTERRUPT
CONTROL
INT4/P00
8
N
fX / 2
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
SYSTEM CLOCK
GENERATOR
SUB
MAIN
STAND BY
CONTROL
PCL/P22
XT1 XT2 X1 X2
*
AN6/P82, AN7/P83
4
COM0–COM3
3
VLC0–VLC2
CPU
CLOCK
fLCD
BIT SEQ.
BUFFER (16)
S24/BP0
–S31/BP7
VDD
VSS
RESET
BIAS
LCDCL/P30
SYNC/P31
7
µPD75336
KR0/P60
–KR3/P63
KR4/P70
–KR7/P73
LCD
CONTROLLER
/DRIVER
8
µPD75336
3. PIN FUNCTIONS
3.1
PORT PINS (1/2)
Pin Name
Input/Output
DualFunction Pin
P00
Input
INT4
P01
Input/output
SCK
P02
Input/output
SO/SB0
P03
Input/output
SI/SB1
INT0
P10
Input
P12
INT2
P13
TI0
P20
PTO0
PTO1
P21
Input/output
P22
PCL
P23
BUZ
P30 *2
LCDCL
SYNC
P31 *2
Input/output
8
8-Bit I/O
Reset
I/O Circuit
Type *1
B
4-bit input port (PORT 0)
Pull-up resistor can be used for P01 to P03
as a 3-bit unit by software.
F -A
×
Input
F -B
M-C
With noise elimination function
INT1
P11
*
Function
P32 *2
—
P33 *2
—
×
Input
B -C
4-bit input/output port (PORT 2)
Pull-up resistor can be used as a 4-bit unit
by software.
×
Input
E-B
Programmable 4-bit input/output port (PORT 3)
Input/output can be specified bit-wise.
Pull-up resistor can be used as a 4-bit unit
by software.
×
Input
E-B
High level
(on-chip pull-up resistor) or high-impedance
M
High level
(on-chip pull-up
resistor) or highimpedance
M
4-bit input port (PORT 1)
Pull-up resistor can be used as a 4-bit unit
by software.
P40 to P43 *2
Input/output
—
N-ch open-drain 4-bit input/output port
(PORT 4)
On-chip pull-up resistor can be specified bitwise (mask option).
Open-drain: 10 V withstand voltage
P50 to P53 *2
Input/output
—
N-ch open-drain 4-bit input/output port
(PORT 5)
On-chip pull-up resistor can be specified bitwise (mask option).
Open-drain: 10 V withstand voltage
1.
: Schmitt triggered input
2. LED direct drive possible
µPD75336
3.1
PORT PINS (2/2)
Pin Name
DualFunction Pin
Input/Output
P60
KR0
P61
KR1
Input/output
P62
KR2
P63
KR3
P70
KR4
P71
KR5
Input/output
P72
KR6
P73
KR7
P80
TI1
P81
––
Input/output
P82
AN6
P83
AN7
BP0
S24
Function
8-Bit I/O
Programmable 4-bit input/output port (PORT 6)
Input/output can be specified bit-wise.
Pull-up resistor can be used as a 4-bit unit
by software.
4-bit input/output port (PORT 7)
Pull-up resistor can be used as a 4-bit unit
by software.
Reset
I/O Circuit
Type *1
Input
F -A
Input
F -A
E -E
4-bit input/output port (PORT 8)
Pull-up resistor can be used as a 4-bit unit
by software.
E-B
×
Input
Y-B
BP1
S25
Output
BP2
S26
BP3
S27
BP4
S28
BP5
1-bit output port (BIT PORT)
Also used as segment output pin.
×
*2
G-C
S29
Output
*
BP6
S30
BP7
S31
1.
: Schmitt triggered input
2. BP0 to BP7 select VLC1 as the input source.
However, the output level depends on BP0 to BP7 and VLC1 external circuit.
Example
BP0 to BP7 are connected mutually within the µPD75336 as shown below. Therefore, the output level
of BP0 to BP7 is determined by the value of R1, R2 and R3.
VDD
R2
BP0
ON
VLC1
R1
BP1
ON
R3
µPD75336
9
µPD75336
3.2
NON-PORT PINS (1/2)
Pin Name
Input/Output
DualFunction Pin
Input
External event pulse input to timer/event counter
E -E
P20
PTO0
Output
Timer/event counter output
Input
E-B
P21
PTO1
PCL
Output
P22
Clock output
Input
E-B
BUZ
Output
P23
Fixed frequency output (for buzzer or system clock trimming)
Input
E-B
SCK
Input/output
P01
Serial clock input/output
Input
F -A
SO/SB0
Input/output
P02
Serial data output
Serial bus input/output
Input
F -B
SI/SB1
Input/output
P03
Serial data input
Serial bus input/output
Input
M -C
INT4
Input
P00
Edge detection vectored interrupt input (both rising edge
and falling edge detection effective)
Input
B
Input
B -C
Input
B -C
P10
INT0
Input
INT1
Edge detection vectored interrupt
input (detection edge selectable)
Clocked
Asynchronous
P11
Edge detection testable input (rising edge detection)
INT2
Input
P12
KR0 to KR3
Input
P60 to P63
Parallel falling edge detection testable input
Input
F -A
Input
P70 to P73
Parallel falling edge detection testable input
Input
F -A
Input
—
Main system clock oscillation crystal/ceramic connection
pin. For external clock, the external clock signal is input to
X1 and its opposite phase is input to X2.
––
––
—
Subsystem clock oscillation crystal connection pin. For
external clock, the external clock signal is input to XT1 and
XT2 is opened. XT1 can be used as a 1-bit input (test).
—
––
KR4 to KR7
X1
X2
XT1
10
Input
P80
TI1
I/O Circuit
Type *
B -C
P13
TI0
*
Reset
Function
Input
Asynchronous
XT2
––
RESET
Input
—
System reset input
—
B
IC
—
—
Internally Connected. Connect the IC pin to VDD directly.
—
––
VDD
—
—
Positive power supply
—
––
VSS
—
—
GND potential
—
––
: Schmitt triggered input
µPD75336
3.2
NON-PORT PINS (2/2)
Pin Name
Input/Output
DualFunction Pin
Reset
I/O Circuit
Type
S12 to S23
Output
––
Segment signal output
*2
G-A
S24 to S31
Output
BP0 to BP7
Segment signal output
*2
G-C
COM0 to COM3
Output
––
Common signal output
*2
G-B
VLC0 to VLC2
Input
––
LCD drive power supply with on-chip split resistor
(mask option)
––
––
BIAS
Output
—
Externally mounted split resistor cut output
*3
––
LCDCL *1
Output
P30
Clock output for driving the externally extended driver
Input
E-B
P31
Clock output for synchronizing the externally extended
driver
Input
E-B
SYNC *1
Output
Y
—
AN0 to AN5
AN6
Function
Input
P82
A/D converter analogs signal input
Input
Y-B
P83
AN7
*
AVREF
Input
—
A/D converter reference voltage input
—
Z
AVSS
––
––
A/D converter GND potential
—
Z
1. Reserved pins for future system extension. They are used now only as P30 and P31 pins.
2. For each display output, VLCX is selected as the input source.
S12 to S31
COM0 to COM2
COM3
Each display output
: V LC1
: VLC2
: VLC0
level varies depending on each display output and VLCX external circuit.
3. Low level if there is an on-chip split resistor.
High impedance if there is no on-chip split resistor.
11
µPD75336
3.3 PIN INPUT/OUTPUT CIRCUITS
Input/output circuits of µPD75336 pins are shown in schematic form.
TYPE D (For TYPE E-B, F-A)
TYPE A (For TYPE E-B)
VDD
VDD
data
P-ch
P-ch
OUT
IN
N-ch
output
disable
N-ch
Push-pull output that can be made high-impedance output (PCMOS Standard Input Buffer
TYPE B
ch and N-ch OFF)
TYPE E-B
VDD
P.U.R.
P.U.R.
enable
IN
P-ch
data
IN/OUT
Type D
output
disable
Type A
P.U.R.:Pull-Up Resistor
Schmitt-Triggered Input with Hysteresis Characteristic
TYPE B-C
TYPE E-E
VDD
P.U.R.
VDD
P.U.R.
enable
P-ch
P.U.R.
data
P-ch
P.U.R.
enable
IN/OUT
Type D
output
disable
Type A
IN
P.U.R. : Pull-Up Resistor
Type B
Schmitt-Triggered Input with Hysteresis Characteristic
P.U.R.:Pull-Up Resistor
12
µPD75336
TYPE F-A
TYPE G-B
VDD
VLC0
P-ch
P.U.R.
VLC1
P.U.R.
enable
P-ch
P-ch N-ch
data
IN/OUT
OUT
Type D
output
disable
COM
data
N-ch
P-ch
VLC2
Type B
N-ch
P.U.R.:Pull-Up Resistor
TYPE F-B
TYPE G-C
VDD
P.U.R.
VDD
P.U.R.
enable
P-ch
P-ch
VDD
output
disable
(P)
VLC0
P-ch
IN/OUT
VLC1
data
P-ch
output
disable
SEG
data/Bit Port data
N-ch
output
disable
(N)
OUT
N-ch
VLC2
N-ch
P.U.R.:Pull-Up Resistor
TYPE G-A
TYPE M
VDD
P.U.R.
enable
Mask Opution
IN/OUT
VLC0
P-ch
data
VLC1
N-ch
P-ch
SEG
data
OUT
output
disable
N-ch
VLC2
N-ch
Middle-High Voltage Input Buffer
(+10 V Withstand Voltage)
P.U.R.:Pull-Up Resistor
13
µPD75336
TYPE M-C
TYPE Y-B
VDD
VDD
P.U.R.
P.U.R.
enable
P.U.R.
enable
P-ch
IN/OUT
P-ch
data
IN/OUT
Type D
data
output
disable
N-ch
output
disable
Type A
port *
input
Type Y
P.U.R.:Pull-Up Resistor
P.U.R.:Pull-Up Resistor
TYPE Y
TYPE Z
IN
VDD
IN
P-ch
N-ch
Sampling
C
VDD
+
–
AVSS
Reference Voltage
(from Voltage Tap of
Serial Resistor String)
AVSS
input
enable
*
14
Reference
Voltage
This becomes active in executing input instruction.
AVSS
µPD75336
3.4 MASK OPTION SELECTION
The following mask options are available for the pins.
Pin
Mask Option
P40 to P43,
P50 to P53
VLC0 to VLC2,
BIAS
XT1, XT2
3.5
1
Pull-up resistor not available
(specifiable bit-wise)
2
Pull-up resistor available
(specifiable bit-wise)
1
Split resistor available for LCD
drive power supply
(specifiable in 4 units)
2
Split resistor not available for LCD
drive power supply
(specifiable in 4 units)
1
Feedback resistor available
(when subsystem clock is used)
2
Feedback resistor not available
(when subsystem clock is not used)
RECOMMENDED CONNECTION OF UNUSED PINS
Pin
P00/INT4
Recommended Connection
Connect to V SS.
P01/SCK
P02/SO/SB0
Connect to V SS or VDD.
P03/SI/SB1
P10/INT0 to P12/INT2
Connect to VSS.
P13/TI0
P20/PTO0
P21/PTO1
P22/PCL
P23/BUZ
P30 to P33
Input status : Connect to VSS or VDD.
P40 to P43
Output status: Leave open.
P50 to P53
P60 to P63
P70 to P73
P80, P81
P82/AN6, P83/AN7
S12 to S23
S24/BP0 to S31/BP7
Leave open.
COM0 to COM3
VLC0 to VLC2
BIAS
Connect to V SS.
Connect to V SS only when none of VLC0 to VLC2 are used. Leave open in all
other cases.
XT1
Connect to V SS or VDD.
XT2
Leave open.
AN0 to AN5
IC
Connect to V SS or VDD.
Connect to V DD directly.
15
µPD75336
4. MEMORY CONFIGURATION
• Program memory (ROM) ......16256 × 8 bits (0000H to 3F7FH)
· 0000H, 0001H
: Vector table for writing the program start address by restart
· 0002H to 000DH : Vector table for writing the program start address by interrupt
· 0020H to 007FH : Table area referred to by GETI instruction
• Data memory
· Data area ...768 × 4 bits (000H to 2FFH)
·Peripheral hardware area ...128 × 4 bits (F80H to FFFH)
16
µPD75336
Fig. 4-1 Program Memory Map
Address
0000H
7
6
MBE
RBE
0
Reset Start Address (High-Order 6 Bits)
Reset Start Address (Low-Order 8 Bits)
MBE
0002H
RBE
INTBT/INT4 Start Address (High-Order 6 Bits)
INTBT/INT4 Start Address (Low-Order 8 Bits)
MBE
0004H
RBE
INT0 Start Address (High-Order 6 Bits)
INT0 Start Address (Low-Order 8 Bits)
MBE
0006H
RBE
CALL !addr
Instruction
Subroutine
Entry Address
INT1 Start Address (High-Order 6 Bits)
INT1 Start Address (Low-Order 8 Bits)
MBE
0008H
RBE
INTCSI Start Address (High-Order 6 Bits)
INTCSI Start Address (Low-Order 8 Bits)
MBE
000AH
RBE
CALLF
! faddr
Instruction
Entry
Address
INTT0 Start Address (High-Order 6 Bits)
INTT0 Start Address (Low-Order 8 Bits)
MBE
000CH
RBE
INTT1 Start Address (High-Order 6 Bits)
INTT1 Start Address (Low-Order 8 Bits)
≈
BR !addr
Instruction
Branch Address
BRCB
! caddr
Branch
Address
≈
BR $addr
Instruction
Relative
Branch Address
(-15 to -1,
+2 to +16)
0020H
GETI Instruction Reference Table
007FH
0080H
07FFH
≈
≈
≈
≈
≈
≈
BRCB
! caddr
Branch Address
≈
≈
BRCB
! caddr
Branch Address
≈
≈
BRCB
! caddr
Branch Address
Branch Destination
Address and
Subroutine Entry Address
by GETI Instruction
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
3F7FH
Remarks
Apart from the cases above, branching is possible to an address for which the PC low-order 8 bits
only have been changed, by the BR PCDE or BR PCXA instruction.
17
µPD75336
Fig. 4-2 Data Memory Map
Data Memory
000H
General Register Area
01FH
Memory Bank
(32 × 4)
020H
Stack Area
Bank
0
Bank
1
Bank
2
Bank
15
(224 × 4)
Data Area
Static RAM
(768 × 4)
0FFH
100H
(236 × 4)
1EBH
1ECH
Display Data Memory
Area (20 × 4)
(20 × 4)
1FFH
200H
256 × 4
2FFH
Not Incorporated
F80H
Peripheral Hardware Area
(128 × 4)
128 × 4
FFFH
Remarks
18
Banks 0, 1, 2 : 256 × 4 bits
Bank 15
: 128 × 4 bits
µPD75336
5. PERIPHERAL HARDWARE FUNCTIONS
5.1
PORTS
There are four types of I/O port as follows.
• CMOS input (PORT0, 1)
• CMOS input/output (PORT2, 3, 6, 7, 8)
• CMOS output (BIT PORT)
: 8
: 20
: 8
• N-ch open-drain input/output (PORT4, 5)
Total
:
8
44
Table 5-1 Port Functions
Port (Symbol)
PORT 0
PORT 1
Function
4-bit input
PORT 3 *
PORT 6
Operation/Features
Regardless of the operating mode of the shared
pin, reading or test is always possible.
Can be set in the input or output mode bit-wise
Remarks
Dual-function pins as SO/SB0, SI/
SB1, SCK, INT0 to INT2, INT4 and
TI0
Dual-function pins as LCDCL and
SYNC.
Dual-function pins as KR0 to KR3.
PORT 2
4-bit input/output
Dual-function pins as PTO0, PTO1,
PCL and BUZ in port 2.
Can be set in the input or output mode as a 4bit unit. Port 6 and Port 7 are paired for input
and output of data as an 8-bit unit.
PORT 7
Dual-function pins as TI1, AN6
and AN7
PORT 8
PORT 4 *
PORT 5 *
BP0 to BP7
*
Dual-function pins as KR4 to KR7.
4-bit input/output
(N-ch open-drain 10
V withstand voltage)
Can be set in the input or output mode as a 4bit unit. Port 4 and port 5 are paired for input
and output of data as an 8-bit unit.
1-bit output
Data are output bit-wise. Can be switched with
LCD driver segment outputs S24 to S31 through
software.
In the case of the mask option, onchip pull-up resistors can be specified bit-wise.
LED can be directly driven.
19
µPD75336
5.2 CLOCK GENERATOR
Clock generator operation is determined by the processor clock control register (PCC) and the system clock
control register (SCC).
There are two types of clock: main system clock and subsystem clock.
The instruction execution time can also be changed.
• 0.95 µs/1.91 µ s/3.81 µs/15.3 µs (main system clock: at 4.19 MHz operation)
• 122 µs (subsystem clock: at 32.768 kHz operation)
Fig. 5-1 Block Diagram of Clock Generator
• Basic Interval Timer (BT)
• Timer/Event Counter
• Serial Interface
• Watch Timer
• LCD Controller/Driver
• A/D Converter
• INT0 Noise Eliminator
• Clock Output Circuit
XT1
VDD
XT2
Subsystem
Clock Oscillation Circuit
fXT
Main System
Clock Oscillation Circuit
fX
LCD Controller/
Driver
Watch Timer
X1
VDD
X2
1/8 to 1/4096
Frequency Divider
Oscillation
Stop
Selector
WM. 3
SCC
Selector
1/2 1/4 1/16
SCC3
Internal Bus
SCC0
Frequency
Divider
1/4
PCC
Φ
• CPU
• INT0 Noise Eliminator
• Clock Output Circuit
PCC0
PCC1
4
HALT F/F
HALT *
PCC2
S
PCC3
STOP *
R
PCC2,
PCC3
Clear
STOP F/F
Q
Q
Wait Release Signal from BT
S
RESET Signal
R
*
Instruction execution
Remarks
20
Standby Release Signal from
Interrupt Control Circuit
1.
2.
fX = Main system clock frequency
fXT = Subsystem clock frequency
3.
4.
5.
6.
Φ = CPU clock
PCC: Processor clock control register
SCC: System clock control register
1 clock cycle of Φ (tCY) is 1 machine cycle of instruction. For tCY, refer to "AC CHARACTERISTICS"
in 10. "ELECTRICAL SPECIFICATIONS".
µPD75336
5.3 CLOCK OUTPUT CIRCUIT
The clock output circuit is intended to output clock pulses from the P22/PCL pin and is used for remote control
or to supply clock pulses to peripheral LSIs.
• Clock output (PCL): Φ , 524 kHz, 262 kHz, 65.5 kHz (at 4.19 MHz operation)
Fig. 5-2 Clock Output Circuit Configuration
From Clock
Generator
Φ
fX/2
3
Output Buffer
Selector
fX/2
fX/2
4
PCL/P22
6
PORT2.2
CLOM3
0
CLOM1CLOM0
CLOM
P22
Output Latch
Bit 2 of PMGB
Bit Specified
In Port 2
Input/Output
Mode
4
Internal Bus
Remarks
The clock circuit is so configured that short-width pulses are not generated when clock output
enable/disable is switched.
21
µPD75336
5.4 BASIC INTERVAL TIMER
The basic interval timer has the following functions:
•
•
•
•
Interval timer operation to generate reference time interrupts
Watchdog timer application to detect program runaway
Wait time selection and count after the standby mode is released
Count content read
Fig. 5-3 Basic Interval Timer Configuration
From Clock
Generator
fX/2
fX/2
Clear
5
7
fX/2
Set
Basic Interval Timer
(8-Bit Frequency Divider)
MPX
fX/2
Clear
9
BT
12
3
BTM3
SET1*
BTM2
BTM1
Wait Release
Signal during
Standby Release
BTM0 BTM
8
4
Internal Bus
*
22
Instruction execution
BT Interrupt
Request Flag
IRQBT
Vectored
Interrupt
Request
Signal
µPD75336
5.5 WATCH TIMER
The µPD75336 has one-channel on-chip watch timer. The watch timer has the following functions.
• Sets the test flag (IRQW) at a 0.5 sec. time interval.
Can release the standby mode by IRQW.
• Can generate the 0.5 sec. time interval with the main system clock or the subsystem clock.
• Can carry out program debugging or inspection efficiently in the fast feed mode with a time interval set
to 3.91 µs (128 times the normal feed mode).
• Can generate a frequency of 2.048, 4.096 or 32.768 kHz to the P23/BUZ pin to generate buzzer sound or trim
the system clock oscillation frequency.
• Can start the watch at zero second since it can clear the divider.
Fig. 5-4 Block Diagram of Watch Timer
fW
6
2
(512 Hz : 1.95 ms)
fLCD
fW
(256 Hz : 3.91 ms)
7
2
From
Clock
Generator
fX
128
(32.768 kHz)
fW
14
2
fW
(32.768 kHz)
Selector
INTW
IRQW Set
Signal
Selector
Frequency Divider
fXT
(32.768 kHz)
2 Hz
0.5 sec
(4 kHz) (2 kHz)
fW
3
2
fW
4
2
Clear
Selector
Output Buffer
P23/BUZ
WM
WM7
PORT2.3
0
WM5 WM4 WM3 WM2 WM1 WM0
8
P23
Output
Latch
Bit 2 of PMGB
Port 2
Input/Output
Mode
Bit Test Instruction
Internal Bus
Values in parentheses are when fX = 4.194304 MHz and fXT = 32.768 kHz.
23
µPD75336
5.6
TIMER/EVENT COUNTER
(1) Timer/event counter configuration
The µPD75336 has two channels of timer/event counters.
Channels 0 and 1 of the timer/event counter have the following differences.
Table 5-2 Differences between Timer/Event Counter Channel 0 and Channel 1
Differences
Channel 0
Channel 1
Selection count pulse
fX/210, fX/28, fX/26, fX/24,
fX/212, fX/210, fX/28, fX/26
Clock supply to the serial interface
Possible
Impossible
(2) Timer/event counter functions
The timer/event counter functions are:
• Programmable interval timer operation
• Output of square wave having any selected frequency to the PTOn pin
•
•
•
•
24
Event counter operation
Output of N-divided TIn pin input to the PTOn pin (frequency divider operation)
Serial shift clock supply to the serial interface circuit
Count status call function
Fig. 5-5 Timer/Event Counter Block Diagram
Internal Bus
SET1
8
*1
8
8
TMn
TMODn
Modulo Register (8)
TMn6 TMn5 TMn4 TMn3 TMn2
8
Port Input
Buffer
Match
Input Buffer
8
Reset
TIn
Tn
From Clock
Generator
Count Register (8)
CP
PORT2.n Bit 2 of PGMB
Port 2
P2n
Input/
Output
Output
Latch
Mode
To Serial
Interface
TOUT
F/F
Comparator (8)
MPX
TOEn
TO
Enable
Flag
*2
PTOn
Output
Buffer
INTTn
IRQTn
Set Signal
Clear
Timer Operation Start
RESET
IRQTn
Clear Signal
Remarks n = 0, 1 (n indicates channel number)
* 1. Instruction execution
2. Only from channel 0 of timer/event counter
µPD75336
25
µPD75336
5.7 SERIAL INTERFACE
The µPD75336 incorporates a clocked 8-bit serial interface, with four modes available.
•
•
•
•
26
Operation-halted mode
3-wire serial I/O mode
2-wire serial I/O mode
SBI mode (serial bus interface mode)
Fig. 5-6 Serial Interface Block Diagram
Internal Bus
8/4 Bit
Test
CSIM
8
8
Bit Manipulation
Slave Address Register (SVA)
Addres Comparator
(8)
(8)
RELT
CMDT
SO
SET CLR Latch
D
Q
ACKT
ACKE
BSYE
Shift Register (SIO)
SBIC
Match
Signal
(8)
P03/SI/SB1
Selector
Bit Test
8
Selector
P02/SO/SB0
Busy/
Acknowledge
Output Circuit
Bus Release/
Command/
Acknowledge
Detection Circuit
P01/SCK
Serial Clock
Counter
P01
Output
Latch
RELD
CMDD
ACKD
INTCSI
INTCSI Control
Circuit
 IRQCSI



 Set Signal 
3
Serial Clock
Control Circuit
Serial
Clock
Slector
fX/24
fX/2
6
fX/2
TOUT F/F
(From Timer/
Event Counter 0)
External
SCK
µPD75336
27
µPD75336
5.8 LCD CONTROLLER/DRIVER
The µPD75336 incorporates a display controller which generates a segment signal and a common signal in
accordance with the display data memory and a segment drive and a common driver which can directly operate
the LCD panel.
The LCD controller/driver has the following functions.
• Automatically read display data memory by DMA operation and generates segment and common signals.
• Can select one of the following 5 display modes.
1
2
3
4
Static
1/2 duty (2-time multiplexing), 1/2 bias
1/3 duty (3-time multiplexing), 1/2 bias
1/3 duty (3-time multiplexing), 1/3 bias
5 1/4 duty (4-time multiplexing), 1/3 bias
• Can select one of the four frame frequencies in each display mode.
• Has a maximum of 20 segment signal outputs (S12 to S31) and a maximum of 4 common outputs (COM0
to COM3).
• The segment outputs (S24 to S27, S28 to S31) can be switched to output ports in 4 output units (BP0 to BP3,
BP4 to BP7).
• Can incorporate a split resistor for LCD drive power supply (mask option).
• Applicable to various types of bias methods and LCD drive voltage.
• Cuts off current to the split resistor when display is off.
• The display data memory not used for display can be used as a normal data memory.
• Can operate with subsystem clock.
28
Fig. 5-7 LCD Controller/Driver Block Diagram
4
Display Data
Memory
1FFH
1FEH
1F9H
1ECH
1F8H
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3 2
1 0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3 2
1 0
8
4
4
8
Display Mode
Register
Display
Control
Register
Port 3
Output
Latch
1 0
Port Mode
Register
Group A
1
0
Timing
Controller
fLCD
Multiplexer
Selector
Common Driver
Segment Driver
S31/PB7
S30/BP6
S24/BP0
S23
S12
LCD Driver Voltage
Control
COM3 COM2COM1COM0 V
LC2
VLC1
VLC0 P31/ P30/
SYNC LCDCL
µPD75336
29
µPD75336
5.9 A/D CONVERTER
The µ PD75336 incorporates an 8-bit resolution analog/digital (A/D) converter having 8-channel analog inputs
(AN0 to AN7).
The A/D converter employs the successive approximation method.
Fig. 5-8 A/D Converter Block Diagram
Internal Bus
ADM
0
ADM6 ADM5 ADM4
SOC
EOC
0
0
8
AN0
Control Circuit
AN1
Sample & Hold Circuit
AN2
+
AN3
SA Register (8)
Multiplexer
AN4
–
AN5
Comparator
AN6/P82
8
AN7/P83
Tap Decoder
AVREF
R/2
R
R
Serial Resistor String
AVSS
30
R
R/2
µPD75336
5.10 BIT SEQUENTIAL BUFFER.....16 BIT
The bit sequential buffer 0 to 3 (BSB0 to BSB3) is a special data memory for bit manipulation. Since it can carry
out bit manipulation easily by sequentially changing the address and bit specification, the bit sequential buffer is
useful to process data having a long bit length bit-wise.
Fig. 5-9 Bit Sequential Buffer Format
Address
FC3H
3
Bit
Symbol
L Register L = F
2
1
FC2H
0
3
2
BSB3
1
FC1H
0
3
2
BSB2
L=CL=B
1
0
FC0H
3
2
1
BSB1
L=8L=7
0
BSB0
L=4 L=3
L=0
DECS L
INCS L
Remarks
1.
2.
In pmem.@L addressing, the specified bit shifts in accordance with the L register.
In pmem.@L addressing, BSB is always operable regardless of MBE, MBS specifications.
31
µPD75336
6. INTERRUPT FUNCTIONS
The µPD75336 has seven types of interrupt sources enabling multiplex interruption by the software control.
It has also two types of test source. INT2 of the test source is equipped with two types of edge detection testable
inputs.
The µPD75336 interrupt control circuit has the following functions:
• Vectored interrupt function controlled by the hardware which can control enabling/disabling of interrupt
acknowledge using interrupt flag (IE×××) and interrupt master enable flag (IME)
• Function of setting any interrupt start address
• Multiplex interruption function capable of specifying priority using the interrupt priority select register (IPS)
• Interrupt request flag (IRQ×××) test function (generation of interrupt can be checked by the software)
• Standby mode release function (interrupt to be released can be selected using the interrupt enable flag)
32
Fig. 6-1 Block Diagram Interrupt Control Circuit
Internal Bus
2
1
3
IM2
IM1
IM0
Interrupt Enable Flag (IE XXX )
Both Edges
Detection
Circuit
INT1
/P11
*
Edge
Detection
Circuit
IRQCSI
INTT0
IRQT0
INTT1
IRQT1
INTW
IRQW
KR0/P60
Falling Edge
Detection
Circuit
KR7/P73
IRQ1
INTCSI
Rising Edge
Detection
Circuit
VRQn
IRQ4
IRQ0
Edge
Detection
Circuit
INT2
/P12
IST0
IRQBT
Selector
INT0
/P10
IPS
Decoder
INT
BT
INT4
/P00
IME
Priority Control
Circuit
Standby Release
Signal
IRQ2
IM2
Vector
Table
Address
Generator
* Noise Eliminator
µPD75336
33
µPD75336
7. STANDBY FUNCTIONS
Two standby modes (STOP mode and HALT mode) are available for the µPD75336 to reduce power consumption
during standby for program.
Table 7-1 Operating Status in Standby Mode
Mode
Item
STOP instruction
HALT instruction
System clock at setting
Only main system clock settable
Main system clock or subsystem
clock settable
Clock generator
Only main system clock oscillation
stopped
Only CPU clock Φ stopped
(oscillation continued)
Basic interval timer
Operation stop
Operable only with main system clock
oscillation (IRQBT set at reference time
intervals)
Serial interface
Operable only when external SCK
input selected as serial clock
Operable with main system clock
oscillation or when external SCK input is
selected as serial clock.
Timer/event counter
Operable only when TI0 and TI1 pin
input specified as count clock
Operable with main system clock
oscillation or T10 and TI1 pin input
specified as count clock.
Watch timer
Operable only when fXT selected as
count clock
Operable
LCD controller
Operable only when fXT selected as
LCDCL
Operable
A/D converter
Operation stop
Operable *
External interrupt
INT1, 2, 4: Operable
Only INT0 inoperable
CPU
Operation stop
Operation Status
34
HALT Mode
Setting instruction
Release signal
*
STOP Mode
Interrupt request signal from operable
hardware enabled by interrupt enable
flag, or RESET input
Operation possible only during main system clock oscillation
Interrupt request signal from operable
hardware enabled by interrupt enable
flag, or RESET input
µPD75336
8. RESET FUNCTIONS
The µPD75336 is set by RESET input and each hardware is initialized as shown in Table 8-1. Reset operation timing
is shown in Fig. 8-1.
Fig. 8-1 Reset Operation by RESET Input
Wait
(31.3 ms/4.19 MHz)
RESET Input
Operating Mode or Standby
Mode
HALT Mode
Operating Mode
Internal Reset Operation
35
µPD75336
Table 8-1 Status after Reset of Each Hardware (1/2)
RESET Input in Standby
Mode
RESET Input during
Operation
Low-order 6 bits of program
memory address 0000H are
set to PC13 to PC8 and the
contents of address 0001H
are set in PC7 to PC0.
Low-order 6 bits of program
memory address 0000H are
set to PC13 to PC8 and the
contents of address 0001H
are set in PC7 to PC0.
Held
Undefined
Skip flag (SK0 to SK2)
0
0
Interrupt status flag (IST0)
0
0
Bit 6 of program memory
address 0000H is set in RBE,
and bit 7 is set to MBE.
Bit 6 of program memory
address 0000H is set in RBE,
and bit 7 is set to MBE.
Undefined
Undefined
Data memory (RAM)
Held*
Undefined
General register (X, A, H, L, D, E, B, C)
Held
Undefined
Bank selection register (MBS, RBS)
0, 0
0, 0
Undefined
Undefined
Mode register (BTM)
0
0
Counter (Tn)
0
0
FFH
FFH
0
0
0, 0
0, 0
0
0
Held
Undefined
Operating mode register (CSIM)
0
0
SBI control register (SBIC)
0
0
Held
Undefined
Processor clock control register (PCC)
0
0
System clock control register (SCC)
0
0
Clock output mode register (CLOM)
0
0
Display mode register (LCDM)
0
0
Display control register (LCDC)
0
0
04H (EOC = 1)
04H (EOC = 1)
7FH
7FH
Hardware
Program counter (PC)
Carry flag (CY)
PSW
Bank enable flag (MBE, RBE)
Stack pointer (SP)
Basic interval
timer
Timer/event
counter
(n = 0, 1)
Counter (BT)
Modulo register (TMODn)
Mode register (TMn)
TOEn, TOUT F/F
Watch timer
Mode register (WM)
Shift register (SIO)
Serial interface
Slave address register (SVA)
Clock generator,
clock output
circuit
LCD controller
Mode register (ADM), EOC
A/D converter
SA register
*
36
Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input.
µPD75336
Table 8-1 Status after Reset of Each Hardware (2/2)
RESET Input in Standby
Mode
RESET Input during
Operation
IRQ1, IRQ2, IRQ4
Undefined
Undefined
Other than above
0
0
Interrupt enable flag (IE×××)
0
0
Priority select register (IPS)
0
0
0, 0, 0
0, 0, 0
Output buffer
OFF
OFF
Output latch
Clear (0)
Clear (0)
I/O mode register (PMGA, PMGB, PMGC)
0
0
Pull-up resistor specification register
(POGA, POGB)
0
0
Input
Input
Hardware
Interrupt request
flag
(IRQ×××)
Interrupt function
INT0, 1, 2 mode registers (IM0, IM1, IM2)
★
Digital port
P00
P20
P60
P80
to
to
to
to
P03, P10 to P13,
P23, P30 to P33,
P63, P70 to P73,
P83
P40 to P43, P50 to P53
Pin status
• High level:
With an on-chip pull-up
resistor
• High impedance:
In open-drain
S12 to S31,
COM0 to COM3
BIAS
*
• Low level:
With an on-chip split resistor
• High impedance:
Without an on-chip split
resistor
Bit sequential buffer (BSB0 to BSB3)
*
Held
• High level:
With an on-chip pull-up
resistor
• High impedance:
In open-drain
*
• Low level:
With an on-chip split resistor
• High impedance:
Without an on-chip split
resistor
Undefined
Each display output selects the following VLCX as input source.
S12 to S31: VLC1
COM0 to COM2: VLC2
COM3: VLC0
However, the level of each display output varies depending on each display output and VLCX external circuit.
37
µPD75336
9. INSTRUCTION SET
(1) Operand representation and description methods
In the operand column of each instruction, operands are entered in accordance with the description method for
the operand representation of the instruction (refer to RA75X Assembler Package User’s Manual Language Volume
(EEU-730) for details). If there is more than one description method, select one method. Alphabetic capital letters,
plus and minus signs are keywords. Describe them what they are.
In the case of immediate data, describe appropriate numeric values or labels.
Symbols of various registers and flags can be described as labels in place of mem, fmem, pmem, bit, etc. (Refer
to µPD75336 User’s Manual (IEU-725) for details.) However, labels which can be written for fmem and pmem are
limited.
Identifier
*
38
Description
reg
reg1
X, A, B, C, D, E, H, L
X, B, C, D, E, H, L
rp
rp1
rp2
rp'
rp'1
XA, BC, DE, HL
BC, DE, HL
BC, DE
XA, BC, DE, HL, XA', BC', DE', HL'
BC, DE, HL, XA', BC', DE', HL'
rpa
rpa1
HL, HL+, HL–, DE, DL
DE, DL
n4
n8
4-bit immediate data or label
8-bit immediate data or label
mem
bit
8-bit immediate data or label *
2-bit immediate data or label
fmem
pmem
FB0H to FBFH, FF0H to FFFH immediate data or label
FC0H to FFFH immediate data or label
addr
caddr
faddr
0000H to 3F7FH immediate data or label
12-bit immediate data or label
11-bit immediate data or label
taddr
20H to 7FH immediate data (however, bit0 = 0) or label
PORTn
IE×××
RBn
MBn
PORT 0 to PORT 8
IEBT, IET0, IET1, IE0 to IE2, IE4, IECSI, IEW
RB0 to RB3
MB0, MB1, MB2, MB15
Only even address can be entered for mem in 8-bit data processing.
µPD75336
(2) Operation description legend
A
: A register; 4-bit accumulator
B
: B register; 4-bit accumulator
C
D
E
H
:
:
:
:
C register; 4-bit accumulator
D register; 4-bit accumulator
E register; 4-bit accumulator
H register; 4-bit accumulator
L
X
XA
BC
:
:
:
:
L register; 4-bit accumulator
X register; 4-bit accumulator
Register pair (XA); 8-bit accumulator
Register pair (BC)
DE
HL
XA’
BC’
DE’
HL’
PC
SP
:
:
:
:
:
:
:
:
Register pair (DE)
Register pair (HL)
Expanded register
Expanded register
Expanded register
Expanded register
Program counter
Stack pointer
CY
PSW
MBE
RBE
:
:
:
:
Carry flag; bit accumulator
Program status word
Memory bank enable flag
Register bank enable flag
PORTn
IME
IPS
IE×××
:
:
:
:
Portn (n = 0 to 8)
Interrupt master enable flag
Interrupt priority select register
Interrupt enable flag
RBS
MBS
PCC
•
:
:
:
:
Register bank select register
Memory bank select register
Processor clock control register
Address, bit delimiter
(××)
××H
: Contents addressed by ××
: Hexadecimal data
pair
pair
pair
pair
(XA’)
(BC’)
(DE’)
(HL’)
39
µPD75336
(3) Description of symbols in the addressing area column
Remarks
*1
MB = MBE • MBS (MBS = 0, 1, 2, 15)
*2
MB = 0
*3
MBE = 0 : MB = 0 (000H to 07FH)
MB = 15 (F80H to FFFH)
MBE = 1 : MB = MBS (MBS = 0, 1, 2, 15)
*4
MB = 15, fmem = FB0H to FBFH,
FF0H to FFFH
*5
MB = 15, pmem = FC0H to FFFH
*6
addr = 0000H to 3F7FH
*7
addr = (Current PC) –15 to (Current PC) –1
(Current PC) + 2 to (Current PC) + 16
*8
caddr = 0000H
1000H
2000H
3000H
*9
faddr = 0000H to 07FFH
*10
taddr = 0020H to 007FH
1.
2.
3.
4.
to
to
to
to
0FFFH
1FFFH
2FFFH
3F7FH
(PC13, 12 =
(PC13, 12 =
(PC13, 12 =
(PC13, 12 =
00B) or
01B) or
10B) or
11B)
Data memory
addressing
Program memory
addressing
MB indicates an accessible memory bank.
In *2, MB = 0 irrespective of MBE and MBS.
In *4 and *5, MB = 15 irrespective of MBE and MBS.
*6 to *10 indicate addressable areas.
(4) Description of machine cycle column
S indicates the number of machine cycles required for an instruction with skip function to carry out skip operation.
The value of S varies as follows:
• When not skipped ...................................................................................................................................
• When the skipped instruction is a 1-byte or 2-byte instruction .......................................................
• When the skipped instruction is a 3-byte instruction (BR !adder, CALL !adder instructions) .....
Note
S=0
S=1
S=2
GETI instruction is skipped in a 1 machine cycle.
The 1 machine cycle is equal to one cycle of CPU clock Φ (=tCY) and four time periods are selectable by setting
the PCC.
40
µPD75336
Note 1
Mnemonic
Transfer
MOV
Machine
Cycles
A, #n4
1
1
A ← n4
reg1, #n4
2
2
reg1 ← n4
XA, #n8
2
2
XA ← n8
Stack A
HL, #n8
2
2
HL ← n8
Stack B
rp2, #n8
2
2
rp2 ← n8
A, @HL
1
1
A ← (HL)
*1
A, @HL+
1
2+S
A ← (HL), then L ← L + 1
*1
L=0
A, @HL–
1
2+S
A ← (HL), then L ← L – 1
*1
L = FH
A, @rpa1
1
1
A ← (rpa1)
*2
XA, @HL
2
2
XA ← (HL)
*1
@HL, A
1
1
(HL) ← A
*1
@HL, XA
2
2
(HL) ← XA
*1
A, mem
2
2
A ← (mem)
*3
XA, mem
2
2
XA ← (mem)
*3
mem, A
2
2
(mem) ← A
*3
2
2
(mem) ← XA
*3
2
2
A ← reg
2
2
XA ← rp'
reg1 ← A
mem, XA
A, reg
XA, rp'
Note 2
Note
MOVT
Operation
Skip Condition
Stack A
2
2
rp'1, XA
2
2
rp'1 ← XA
A, @HL
1
1
A ↔ (HL)
*1
A, @HL+
1
2+S
A ↔ (HL), then L ← L + 1
*1
L=0
A, @HL–
1
2+S
A ↔ (HL), then L ← L – 1
*1
L = FH
A, @rpa1
1
1
A ↔ (rpa1)
*2
XA, @HL
2
2
XA ↔ (HL)
*1
A, mem
2
2
A ↔ (mem)
*3
XA, mem
2
2
XA ↔ (mem)
*3
A, reg1
1
1
A ↔ reg1
XA, rp'
2
2
XA ↔ rp'
XA, @PCDE
1
3
XA ← (PC13–8 + DE)ROM
XA, @PCXA
1
3
XA ← (PC13–8 + XA)ROM
reg1, A
XCH
Addressing Area
Bytes
Operands
1. Instruction Group
2. Table reference
41
µPD75336
Bit transfer
Note 1
Mnemonic
MOV1
ADDS
ADDC
Operation
SUBS
SUBC
AND
OR
XOR
Note
42
Addressing Area
Bytes
Machine
Cycles
CY, fmem.bit
2
2
CY ← (fmem.bit)
*4
CY, pmem.@L
2
2
CY ← (pmem7–2 + L3–2.bit(L1–0))
*5
CY, @H+mem.bit
2
2
CY ← (H + mem3–0 .bit)
*1
fmem.bit, CY
2
2
(fmem.bit) ← CY
*4
pmem.@L, CY
2
2
(pmem7–2 + L3–2.bit(L1–0)) ← CY
*5
@H+mem.bit, CY
2
2
(H + mem3–0 .bit) ← CY
*1
A, #n4
1
1+S
A ← A + n4
carry
XA, #n8
2
2+S
XA ← XA + n8
carry
A, @HL
1
1+S
A ← A + (HL)
XA, rp'
2
2+S
XA ← XA + rp'
carry
rp'1, XA
2
2+S
rp'1 ← rp'1 + XA
carry
A, @HL
1
1
A, CY ← A + (HL) + CY
XA, rp'
2
2
XA, CY ← XA + rp' + CY
rp'1, XA
2
2
rp'1, CY ← rp'1 + XA + CY
A, @HL
1
1+S
A ← A – (HL)
XA, rp'
2
2+S
XA ← XA – rp'
borrow
rp'1, XA
2
2+S
rp'1 ← rp'1 – XA
borrow
A, @HL
1
1
A, CY ← A – (HL) – CY
XA, rp'
2
2
XA, CY ← XA – rp' – CY
rp'1, XA
2
2
rp'1, CY ← rp'1 – XA – CY
A, #n4
2
2
A ← A ∧ n4
A, @HL
1
1
A ← A ∧ (HL)
XA, rp'
2
2
XA ← XA ∧ rp'
rp'1, XA
2
2
rp'1 ← rp'1 ∧ XA
A, #n4
2
2
A ← A ∨ n4
A, @HL
1
1
A ← A ∨ (HL)
XA, rp'
2
2
XA ← XA ∨ rp'
rp'1, XA
2
2
rp'1 ← rp'1 ∨ XA
A, #n4
2
2
A ← A ∨ n4
A, @HL
1
1
A ← A ∨ (HL)
Operands
Operation
XA, rp'
2
2
XA ← XA ∨ rp'
rp'1, XA
2
2
rp'1 ← rp'1 ∨ XA
Instruction Group
*1
Skip Condition
carry
*1
*1
*1
*1
*1
*1
borrow
µPD75336
Note 3
Comparison
Increment/decrement Note 2
Note 1
Note
Mnemonic
Operands
Bytes
Machine
Cycles
Operation
Addressing Area
Skip Condition
RORC
A
1
1
CY ← A0, A3 ← CY, An–1 ← A n
NOT
A
2
2
A←A
reg
1
1+S
reg ← reg + 1
reg = 0
rp1
1
1+S
rp1 ← rp1 + 1
rp1 = 00H
@HL
2
2+S
(HL) ← (HL) + 1
*1
(HL) = 0
mem
2
2+S
(mem) ← (mem) + 1
*3
(mem) = 0
reg
1
1+S
reg ← reg – 1
reg = FH
rp'
2
2+S
rp' ← rp' – 1
rp' = FFH
reg, #n4
2
2+S
Skip if reg = n4
reg = n4
@HL, #n4
2
2+S
Skip if (HL) = n4
*1
(HL) = n4
A, @HL
1
1+S
Skip if A = (HL)
*1
A = (HL)
XA, @HL
2
2+S
Skip if XA = (HL)
*1
XA = (HL)
A, reg
2
2+S
Skip if A = reg
A = reg
XA, reg
2
2+S
Skip if XA = rp'
XA = rp'
SET1
CY
1
1
CY ← 1
CLR1
CY
1
1
CY ← 0
SKT
CY
1
1+S
NOT1
CY
1
1
INCS
DECS
SKE
Skip if CY = 1
CY = 1
CY ← CY
1. Instruction Group
2. Accumulator operation
3. Carry flag operation
43
µPD75336
Note
Mnemonic
SET1
Operands
Machine
Bytes Cycles
Operation
Addressing Area
Skip Condition
mem.bit
2
2
(mem.bit) ← 1
*3
fmem.bit
2
2
(fmem.bit) ← 1
*4
pmem.@L
2
2
(pmem7–2 + L3–2.bit (L1–0)) ← 1
*5
@H + mem.bit
2
2
(H + mem3–0.bit) ← 1
*1
mem.bit
2
2
(mem.bit) ← 0
*3
fmem.bit
2
2
(fmem.bit) ← 0
*4
pmem.@L
2
2
(pmem7–2 + L3–2.bit (L1–0)) ← 0
*5
@H + mem.bit
2
2
(H + mem3–0.bit) ← 0
*1
mem.bit
2
2+S
Skip if (mem.bit) = 1
*3
(mem.bit) = 1
fmem.bit
2
2+S
Skip if (fmem.bit) = 1
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem7–2 + L3–2.bit (L1–0)) = 1
*5
(pmem.@L) = 1
@H + mem.bit
2
2+S
Skip if (H + mem3–0.bit) = 1
*1
(@H + mem.bit) = 1
mem.bit
2
2+S
Skip if (mem.bit) = 0
*3
(mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 0
*4
(fmem.bit) = 0
pmem.@L
2
2+S
Skip if (pmem7–2 + L3–2.bit (L1–0)) = 0
*5
(pmem.@L) = 0
@H + mem.bit
2
2+S
Skip if (H + mem3–0.bit) = 0
*1
(@H + mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 1 and clear
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem7–2 + L3–2.bit (L1–0)) = 1 and clear
*5
(pmem.@L) = 1
@H + mem.bit
2
2+S
Skip if (H + mem3–0.bit) = 1 and clear
*1
(@H + mem.bit) = 1
CY, fmem.bit
2
2
CY ← CY ∧ (fmem.bit)
*4
CY, pmem.@L
2
2
CY ← CY ∧ (pmem7–2 + L3–2.bit (L1–0))
*5
CY, @H + mem.bit
2
2
CY ← CY ∧ (H + mem3–0.bit)
*1
CY, fmem.bit
2
2
CY ← CY ∨ (fmem.bit)
*4
CY, pmem.@L
2
2
CY ← CY ∨ (pmem7–2 + L3–2.bit (L1–0))
*5
CY, @H + mem.bit
2
2
CY ← CY ∨ (H + mem3–0.bit)
*1
CY, fmem.bit
2
2
CY ← CY ∨ (fmem.bit)
*4
CY, pmem.@L
2
2
CY ← CY ∨ (pmem7–2 + L3–2.bit (L1–0))
*5
CY, @H + mem.bit
2
2
CY ← CY ∨ (H + mem3–0.bit)
*1
*6
CLR1
Memory bit manipulation
SKT
SKF
SKTCLR
AND1
OR1
Branch
XOR1
BR
BRCB
Note
44
addr
—
—
PC13–0 ← addr
(The assembler selects the optimum
instruction from among the BR !addr, BRCB
!caddr, and BR $addr instructions.)
!addr
3
3
PC13–0 ← addr
*6
$addr
1
2
PC13–0 ← addr
*7
PCDE
2
3
PC13–0 ← PC13–8 + DE
PCXA
2
3
PC13–0 ← PC13–8 + XA
!caddr
2
2
PC13–0 ← PC13,12 + caddr11–0
Instruction Group
*8
µPD75336
Note 1
Mnemonic
!addr
(SP – 4) (SP – 1) (SP – 2) ← PC 11–0
(SP – 3) ← MBE, RBE, PC13, PC12
PC13–0 ← addr, SP ← SP – 4
*6
!faddr
2
2
(SP – 4) (SP – 1) (SP – 2) ← PC 11–0
(SP – 3) ← MBE, RBE, PC13, PC12
PC13–0 ← 000 + faddr, SP ← SP – 4
*9
RET
1
3
PC11–0 ← (SP) (SP + 3) (SP + 2)
MBE, RBE, PC13, PC12 ← (SP + 1)
SP ← SP + 4
RETS
1
3+S
PC11–0 ← (SP) (SP + 3) (SP + 2)
MBE, RBE, PC13, PC12 ← (SP + 1)
SP ← SP + 4, then skip unconditionally
RETI
1
3
PC11–0 ← (SP) (SP + 3) (SP + 2)
MBE, RBE, PC13, PC12 ← (SP + 1)
PSW ← (SP + 4) (SP + 5), SP ← SP + 6
rp
1
1
(SP – 1) (SP – 2) ← rp, SP ← SP – 2
BS
2
2
(SP – 1) ← MBS, (SP – 2) ← RBS, SP ← SP – 2
rp
1
1
rp ← (SP + 1) (SP), SP ← SP + 2
BS
2
2
MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2
2
2
IME(IPS.3) ← 1
2
2
IE × × × ← 1
2
2
IME(IPS.3) ← 0
IE × × ×
2
2
IE × × × ← 0
A, PORTn
2
2
A ← PORTn
(n = 0–8)
XA, PORTn
2
2
XA ← PORTn+1, PORTn
(n = 4, 6)
PORTn, A
2
2
PORTn ← A
(n = 2–8)
PORTn, XA
2
2
PORTn+1, PORTn ← XA
(n =4, 6)
HALT
2
2
Set HALT Mode (PCC.2 ← 1)
STOP
2
2
Set STOP Mode (PCC.3 ← 1)
NOP
1
1
No Operation
RBn
2
2
RBS ← n
(n = 0 – 3)
MBn
2
2
MBS ← n
(n = 0, 1, 2, 15)
Subroutine stack control
PUSH
Note 2
POP
EI
DI
IN*
OUT*
IE × × ×
SEL
Special
Addressing Area
Operation
2
CALLF
Input/output
Machine
Cycles
3
CALL
Note 3
Operands Bytes
GETI
taddr
1
3
• TBR Instruction
PC13–0 ← (taddr) 5–0 + (taddr + 1)
----------------------------------------------------------------------• TCALL Instruction
(SP – 4) (SP – 1) (SP – 2) ← PC11–0
(SP – 3) ← MBE, RBE, PC13, PC12
PC13–0 ← (taddr) 5–0 ← (taddr + 1)
SP ← SP – 4
----------------------------------------------------------------------• Other than TBR and TCALL Instruction
Execution of an instruction addressed at
(taddr) and (taddr + 1)
Skip Condition
Unconditional
-----------------------------
*10
----------------------------Depends on the
referred instruction
*
At IN/OUT instruction execution, MBE = 0 or MBE = 1, MBS =15 must be set in advance.
Remarks TBR and TCALL instructons are assembler pseudo instructions for GETI instruction table definition.
Note 1. Instruction Group
2. Interrupt control
3. CPU control
45
µPD75336
10. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C)
PARAMETER
Power supply
voltage
SYMBOL
TEST CONDITIONS
RATING
UNIT
–0.3 to +7.0
V
–0.3 to V DD +0.3
V
–0.3 to V DD +0.3
V
–0.3 to +11
V
–0.3 to V DD +0.3
V
One pin
–15
mA
All pins
–30
mA
Peak value
30
mA
rms
15
mA
Peak value
100
mA
rms
60
mA
Peak value
100
mA
rms
60
mA
–65 to +150
°C
VDD
VI1
Except ports 4 and 5
VI2
Ports 4 and 5
Input voltage
On-chip pull-up resistor
Open–drain
Output voltage
VO
Output current high
IOH
One pin
Output current low
Total of ports 0, 2, 3, 5 and 8
IOL*
Total of ports 4, 6, and 7
Storage
temperature
Rms is calculated using the following expression: [rms] = [peak value] × √duty
*
★
Tstg
Note
Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even
momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge
of suffering physical damage, and therefore the product must be used under conditions which ensure that
the absolute maximum ratings are not exceeded.
★
GUARANTEED OPRERATING RANGE
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Power supply voltage
VDD
2.7
6.0
V
Operating temperature
Topt
–40
+85
˚C
MAX.
UNIT
15
pF
15
pF
15
pF
CAPACITANCE (Ta = 25 °C, VDD = 0 V)
PARAMETER
Input capacitance
Output capacitance
I/O capacitance
46
SYMBOL
TEST CONDITIONS
CIN
COUT
CIO
f = 1 MHz
Unmeasured pins returned to 0 V.
MIN.
TYP.
µPD75336
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
RESONATOR
RECOMMENDED
CIRCUIT
PARAMETER
TEST
CONDITIONS
Oscillator
frequency (f x)*1
X1
MIN.
TYP.
MAX.
UNIT
5.0*3
MHz
4
ms
5.0*3
MHz
10
ms
30
ms
1.0
5.0*3
MHz
100
500
ns
1.0
X2
Ceramic
resonator
C1
C2
Oscillation
stabilization time*2
VDD
After V DD
reaches the
MIN. value of
the oscillation
voltage
range
Oscillator
frequency (f x)*1
X1
1.0
4.19
X2
VDD = 4.5
to 6.0 V
Crystal
resonator
C1
C2
Oscillation
stabilization time*2
VDD
X1
X2
External
clock
X1 input
frequency (f x)*1
X1 input
µPD74HCU04
high-/low-level
width (tXH, tXL)
*
1. The oscillator frequency and X1 input frequency indicate only the oscillator characteristics. For the instruction
execution time refer to the AC CHARACTERISTICS.
2. The oscillation stabilization time is necessary for oscillation to stabilize after VDD reaches the MIN. value of
the oscillation voltage range or releasing the STOP mode.
3. When the oscillator frequency is “4.19 MHz < fX ≤ 5.0 MHz” PCC = 0011 should for the instruction execution
time. If PCC = 0011 is selection, 1 machine cycle is less than 0.95 µs with the result that the specified MIN.
value, 0.95 µs cannot be observed.
Note
When using the main system clock oscillator or the subsystem clock oscillator, wiring in the area enclosed
with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines or not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should always be the same as VSS. Do not ground wiring
to a ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
The subsystem clock oscillator is a circuit with a low amplification level, more prone to misoperation due
to noise than the main system clock. Therefore, when using the subsystem clock, special care is required
in wiring methods.
47
★
µPD75336
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
RESONATOR
RECOMMENDED
CIRCUIT
XT1
PARAMETER
Oscillator
frequency (fXT)*1
XT2
C3
C4
MIN.
TYP.
MAX.
UNIT
32
32.768
35
kHz
1.0
2
s
10
s
32
100
kHz
5
15
µs
VDD = 4.5
to 6.0 V
R
Crystal
resonator
TEST
CONDITIONS
Oscillation
stabilization time*2
VDD
XT1 input
frequency (fXT)*1
XT1
External
clock
XT2
Leave
Open
XT1 input high-/
low-level width
(t XTH,t XTL)
*
★
1. The oscillator frequency and X1 input frequency indicate only the oscillator characteristics. For the instruction
execution time refer to the AC CHARACTERISTICS.
2. The oscillation stabilization time is necessary for oscillation to stabilize after VDD reaches the MIN. value of
the oscillation voltage range or releasing the STOP mode.
Note
When using the main system clock oscillator or the subsystem clock oscillator, wiring in the area enclosed
with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines or not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should always be the same as VSS. Do not ground wiring
to a ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
The subsystem clock oscillator is a circuit with a low amplification level, more prone to misoperation due
to noise than the main system clock. Therefore, when using the subsystem clock, special care is required
in wiring methods.
48
µPD75336
DC CHARACTERISTICS (Ta = –40 to +85 °C, V DD = 2.7 to 6.0 V) (1/2)
PARAMETER
SYMBOL
TEST CONDITIONS
TYP.
MAX.
UNIT
VIH1
Ports 2, 3 and 8
0.7 VDD
VDD
V
VIH2
Ports 0, 1, 6, 7, RESET
0.8 VDD
VDD
V
On-chip pull-up resistor
0.7 VDD
VDD
V
VIH3
Ports 4 and 5
Open–drain
0.7 VDD
10
V
VDD –0.5
VDD
V
Input voltage high
Input voltage low
MIN.
VIH4
X1, X2, XT1
VIL1
Ports 2, 3, 4, 5 and 8
0
0.3 VDD
V
VIL2
Ports 0, 1, 6, 7, RESET
0
0.2 VDD
V
VIL3
X1, X2, XT1
0
0.4
V
VOH1
Ports 0, 2, 3, 6, 7, 8
BIAS
VDD = 4.5 to 6.0 V
IOH = –1 mA
VDD –1.0
V
IOH = –100 µA
VDD –0.5
V
VDD = 4.5 to 6.0 V
IOH = –100 µA
VDD –2.0
V
IOH = –50 µA
VDD –1.0
V
Output voltage high
VOH2
BP0 to BP7
(with 2 IOH outputs)
Ports 3, 4 and 5
VDD = 4.5 to 6.0 V
IOL = 15 mA
Ports 0, 2, 3, 4, 5, 6,
7 and 8
VOL1
Output voltage low
SB0, SB1
VOL2
BP0 to BP7 (with 2
IOL outputs)
ILIH1
2.0
V
VDD = 4.5 to 6.0 V
IOL = 1.6 mA
0.4
V
IOL = 400 µA
0.5
V
0.2 VDD
V
VDD = 4.5 to 6.0 V
IOL = 100 µA
1.0
V
IOL = 50 µA
1.0
V
Other than below
3
µA
X1, X2, XT1
20
µA
Ports 4 and 5
(open–drain)
20
µA
Other than below
–3
µA
X1, X2, XT1
–20
µA
3
µA
20
µA
–3
µA
Open–drain
pull-up resistor ≥ 1 kΩ
0.4
VIN = VDD
Input leakage
current high
ILIH2
ILIH3
Input leakage
current low
Output leakage
current high
Output leakage
current low
VIN = 10 V
ILIL1
VIN = 0 V
ILIL2
ILOH1
VOUT = VDD
Other than below
ILOH2
VOUT = 10 V
Ports 4 and 5
(open–drain)
ILOL
VOUT = 0 V
49
µPD75336
DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) (2/2)
PARAMETER
SYMBOL
RL1
On-chip pull-up
resistor
RL2
TEST CONDITIONS
Ports 0, 1, 2, 3, 6, 7
and 8 (Except P00)
VIN = 0 V
Ports 4 and 5
VOUT = VDD –2.0 V
MIN.
TYP.
MAX.
UNIT
VDD = 5.0 V ±10%
15
40
80
kΩ
VDD = 3.0 V ±10%
30
300
kΩ
VDD = 5.0 V ±10%
15
70
kΩ
VDD = 3.0 V ±10%
10
60
kΩ
VDD
V
140
kΩ
0
±0.2
V
0
±0.2
V
LCD drive voltage
VLCD
2.5
LCD split resistor
RLCD
60
LCD output voltage
deviation*1
(common)
VODC
IO = ±5 µA
LCD output voltage
deviation*1
(segment)
VODS
IO = ±1 µA
IDD1
4.19 MHz*3
crystal oscillation
C1 = C2 = 22 pF
IDD2
Supply current*2
IDD3
32 kHz*6
crystal oscillation
IDD4
VLCD0 = VLCD
VLCD1 = VLCD × 2/3
VLCD2 = VLCD × 1/3
2.7 V ≤ VLCD ≤ VDD
IDD5
*
100
VDD = 5 V ±10%*4
2.5
8
mA
VDD = 3 V ±10%*5
0.35
1.2
mA
VDD = 5 V ±10%
500
1500
µA
VDD = 3 V ±10%
150
450
µA
Operating mode
VDD = 3 V ±10%
30
90
µA
HALT
mode
VDD = 3 V ±10%
5
15
µA
0.5
20
µA
0.1
10
µA
0.1
5
µA
HALT
mode
VDD = 5 V ±10%
XT1 = 0 V
STOP mode
40
VDD =
3 V ±10%
Ta = 25 °C
1. The voltage deviation is the difference between the output voltage and the segment or common output
desired value (VLCDn; n = 0, 1, 2)
2. Current which flows in the on-chip pull-up resistor or LCD split resistor is not included.
3. Including oscillation of the subsystem clock.
4. When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-speed
mode.
5. When PCC is set to 0000 and the device is operated in the low-speed mode.
6. When the system clock control register (SCC) is set to 1011 and the device is operated on the subsystem clock,
with main system clock oscillation stopped.
50
µPD75336
A/D CONVERTER CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
Resolution
2.5 V ≤ AVREF ≤ VDD
Absolute accuracy *1
*
MIN.
TYP.
MAX.
UNIT
8
8
8
bit
–10 ≤ Ta ≤ +85 °C
±1.5
–40 ≤ Ta < –10 °C
±2.0
LSB
Conversion time
tCONV
*2
168/fX
s
Sampling time
tSAMP
*3
44/fX
s
Analog input voltage
VIAN
AVREF
V
Analog Input impedance
RAN
1000
AVREF current
IREF
1.0
AVSS
MΩ
2.0
mA
1. Absolute accuracy excluding quantization (±1/2 LSB) error.
2. Time up to end of conversion (EOC = 1) after execution of the conversion start instruction. (40.1 µ s: fX = 4.19
MHz operation)
3. Time up to end of sampling after execution of the conversion start instruction. (10.5 µs: fX = 4.19 MHz
operation)
51
µPD75336
AC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
PARAMETER
CPU clock cycle
time (minimum
instruction
execution time = 1
SYMBOL
Operating on main
system clock
TI0, TI1 input width
high/low
Interrupt input
width high/low
RESET width low
*
MIN.
VDD = 4.5 to 6.0 V
tCY
machine cycle)*1
TI0, TI1 input
frequency
TEST CONDITIONS
fTI
tTIH,
TYP.
MAX.
UNIT
0.95
64
µs
3.8
64
µs
125
µs
Operating on
subsystem clock
114
VDD = 4.5 to 6.0 V
0
1
MHz
0
275
kHz
122
0.48
µs
1.8
µs
INT0
*2
µs
INT1, INT2, INT4
10
µs
KR0 to KR7
10
µs
10
µs
VDD = 4.5 to 6.0 V
tTIL
tINTH,
tINTL
tRSL
1. CPU clock (Φ) cycle time is determined by the
oscillator frequency of the connected resonator,
the system clock control register (SCC) and the
tCY vs VDD
(Operating on Main System Clock)
70
64
60
processor clock control register (PCC). The figure at the right indicates the cycle time tCY
versus supply voltage VDD characteristic with
the main system clock operating.
Guaranteed
Operating Range
4
Cycle Time tCY [ µ s]
2. 2tCY or 128/fX is set by setting the interrupt mode
register (IM0).
6
5
3
2
1
0.5
0
1
2
3
4
5
Supply Voltage VDD [V]
52
6
µPD75336
SERIAL TRANSFER OPERATION
2-Wired and 3-Wired Serial I/O Modes (SCK ... Internal clock output)
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
MIN.
TYP.
MAX.
UNIT
1600
ns
3800
ns
tKCY1/2-50
ns
tKH1
tKCY1/2-150
ns
SI setup time
(to SCK↑)
tSIK1
150
ns
SI hold time
(from SCK↑)
tKSI1
400
ns
SO output
delay time
from SCK↓
tKSO1
SCK cycle time
tKCY1
tKL1
VDD = 4.5 to 6.0 V
SCK width high/low
VDD = 4.5 to 6.0 V
RL = 1 kΩ,
CL = 100 pF*
250
ns
1000
ns
MAX.
UNIT
2-Wired and 3-Wired Serial I/O Modes (SCK ... External clock input)
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
TYP.
800
ns
3200
ns
400
ns
tKH2
1600
ns
SI setup time
(to SCK↑)
tSIK2
100
ns
SI hold time
(from SCK ↑)
tKSI2
400
ns
SO output
delay time
from SCK↓
tKSO2
SCK cycle time
tKCY2
tKL2
SCK width high/low
*
MIN.
VDD = 4.5 to 6.0 V
RL = 1 kΩ,
CL = 100 pF*
VDD = 4.5 to 6.0 V
300
ns
1000
ns
RL and CL are load resistor and load capacitance of the SO output line.
53
µPD75336
SBI Mode (SCK ... Internal clock output (Master))
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
MIN.
TYP.
MAX.
UNIT
1600
ns
3800
ns
tKCY3/2-50
ns
tKH3
tKCY3/2-150
ns
SB0, 1 setup time
(to SCK ↑)
tSIK3
150
ns
SB0, 1 hold time
(from SCK ↑)
tKSI3
tKCY3/2
ns
SB0, 1 output
delay time from
SCK ↓
tKSO3
SB0, 1 ↓ from SCK ↑
tKSB
tKCY3
ns
SCK from SB0, 1 ↓
tSBK
tKCY3
ns
SB0, 1 width low
tSBL
tKCY3
ns
SB0, 1 width high
tSBH
tKCY3
ns
SCK cycle time
tKCY3
tKL3
VDD = 4.5 to 6.0 V
SCK width high/low
VDD = 4.5 to 6.0 V
RL = 1 kΩ,
CL = 100 pF*
0
250
ns
0
1000
ns
SBI Mode (SCK ... External clock input (Slave))
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
MIN.
TYP.
MAX.
UNIT
800
ns
3200
ns
400
ns
tKH4
1600
ns
SB0, 1 setup time
(to SCK ↑)
tSIK4
100
ns
SB0, 1 hold time
(from SCK ↑)
tKSI4
tKCY4/2
ns
SB0, 1 output
delay time from
SCK ↓
tKSO4
SB0, 1 ↓ from SCK ↑
tKSB
tKCY4
ns
SCK ↓ from SB0, 1 ↓
tSBK
tKCY4
ns
SB0, 1 width low
tSBL
tKCY4
ns
SB0, 1 width high
tSBH
tKCY4
ns
SCK cycle time
tKCY4
tKL4
VDD = 4.5 to 6.0 V
SCK width high/low
*
54
RL = 1 kΩ,
CL = 100 pF*
VDD = 4.5 to 6.0 V
0
300
ns
0
1000
ns
RL and CL are load resistor and load capacitance of the SB0, 1 output lines.
µPD75336
AC Timing Test Point (Excluding X1 and XT1 inputs)
0.8 VDD
0.8 VDD
Test Points
0.2 VDD
0.2 VDD
Clock Timings
1/fX
tXL
tXH
VDD -0.5 V
0.4 V
X1 Input
1/fXT
tXTL
tXTH
VDD -0.5 V
0.4 V
XT1 Input
TI0 Timing
1/fTI
tTIL
tTIH
TI0
55
µPD75336
Serial Transfer Timing
3-wired serial I/O mode:
tKCY1
tKL1
tKH1
SCK
tKSI1
tSIK1
Input Data
SI
tKSO1
SO
Output Data
2-wired serial I/O mode:
tKCY2
tKL2
tKH2
SCK
tSIK2
SB0,1
tKSO2
56
tKSI2
µPD75336
Serial Transfer Timing
Bus release signal transfer:
tKL3,4
tKCY3,4
tKH3,4
SCK
tKSB
tSBL
tSBH
tSIK3,4
tSBK
tKSI3,4
SB0,1
tKSO3,4
Command signal transfer:
tKL3,4
tKCY3,4
tKH3,4
SCK
tKSB
tSIK3,4
tSBK
tKSI3,4
SB0,1
tKSO3,4
Interrupt Input Timing
tINTL
tINTH
INT0,1,2,4
KR0-7
RESET Input Timing
tRSL
RESET
57
µPD75336
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to 85 °C)
PARAMETER
SYMBOL
Data retention supply voltage
VDDDR
Data retention supply current*1
IDDDR
Release signal setup time
tSREL
Oscillation stabilization
wait time*2
tWAIT
TEST CONDITIONS
TYP.
2.0
VDDDR = 2.0 V
0.1
Release by RESET
MAX.
UNIT
6.0
V
10
µA
µs
0
Release by interrupt request
*
MIN.
217/fx
ms
*3
ms
1. Current which flows in the on-chip pull-up resistor is not included.
2. The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent
unstable operation at the oscillation start.
3. Depends on the basic interval timer mode register (BTM) setting (table below).
58
WAIT TIME
(Figures in parentheses are for operation at fx = 4.19 MHz)
BTM3
BTM2
BTM1
BTM0
—
0
0
0
220/fx (approx. 250 ms)
—
0
1
1
217/fx (approx. 31.3 ms)
—
1
0
1
215/fx (approx. 7.82 ms)
—
1
1
1
213/fx (approx. 1.95 ms)
µPD75336
Data Retention Timing (STOP mode release by RESET)
Internal Reset Operation
HALT Mode
STOP Mode
Operating
Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT Mode
STOP Mode
Operating
Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
59
µPD75336
11. PACKAGE INFORMATION
80 PIN PLASTIC QFP ( 14)
A
B
60
61
41
40
Q
5°±5°
S
C
D
detail of lead end
21
20
F
80
1
G
H
I M
J
M
P
K
N
L
S80GC-65-3B9-3
NOTE
Each lead centerline is located within 0.13
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
60
ITEM
MILLIMETERS
INCHES
A
17.2 ± 0.4
0.677 ± 0.016
B
14.0 ± 0.2
0.551+0.009
–0.008
C
14.0 ± 0.2
0.551+0.009
–0.008
D
17.2 ± 0.4
0.677 ± 0.016
F
0.8
0.031
G
0.8
0.031
H
0.30 ± 0.10
0.012+0.004
–0.005
I
0.13
0.005
J
0.65 (T.P.)
0.026 (T.P.)
K
1.6 ± 0.2
0.063 ± 0.008
L
0.8 ± 0.2
0.031+0.009
–0.008
M
0.15+0.10
–0.05
0.006+0.004
–0.003
N
0.10
0.004
P
2.7
Q
0.1 ± 0.1
S
3.0 MAX.
0.106
0.004 ± 0.004
0.119 MAX.
µPD75336
80 PIN PLASTIC TQFP (FINE PITCH) (
12)
A
B
60
41
61
40
Q
5°±5°
S
D
C
detail of lead end
21
F
80
1
G
20
H
I M
J
M
P
K
N
L
P80GK-50-BE9-3
NOTE
Each lead centerline is located within 0.10
mm (0.004 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
14.0 ± 0.4
0.551 ± 0.016
B
12.0 ± 0.2
0.472+0.009
–0.008
C
12.0 ± 0.2
0.472+0.009
–0.008
D
14.0 ± 0.4
0.551 ± 0.016
F
1.25
0.049
G
1.25
0.049
H
0.20 ± 0.10
0.008 ± 0.004
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
K
1.0 ± 0.2
0.039 –0.008
L
0.5 ± 0.2
0.020+0.008
–0.009
M
0.125 +0.10
–0.05
0.005+0.004
–0.001
N
0.10
P
1.05
Q
0.05 ± 0.05
S
1.27 MAX.
+0.009
0.004
0.041
0.002 ± 0.002
0.05 MAX.
61
µPD75336
★
12. RECOMMENDED SOLDERING CONDITIONS
The µPD75336 should be soldered and mounted under the conditions recommended in the table below.
For detail of recommended soldering conditions, refer to information document “Surface Mount Technology
Manual” (IEI-1207).
For soldering methods and conditions other than those recommended below, contact our salesman.
Table 12-1 Surface Mounting Type Soldering Conditions
µPD75336GC-×××-3B9 : 80-pin plastic QFP ( 14mm)
(1)
Soldering Method
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 230˚C,
Duration: 30 sec. max. (at 210˚C above), Number of times: Once,
Time limit: 7 days* (thereafter 10 hours prebaking required at 125˚C)
IR30-107-1
VPS
Package peak temperature: 215˚C,
Duration: 40 sec. max. (at 200˚C above), Number of times: Once,
Time limit: 7 days* (thereafter 10 hours prebaking required at 125˚C)
VP15-107-1
Wave soldering
Solder bath temperature: 260˚C max.,
Duration: 10 sec. max., Number of times: Once,
Preliminary heat temperature: 120˚C max. (Package surface temperature),
Time limit: 7 days* (thereafter 10 hours prebaking required at 125˚C)
WS60-107-1
Pin part heating
Pin part temperature: 300˚C max., Duration: 3 sec. max. (per device side)
(2)
µPD75336GK-×××-BE9 : 80-pin plastic TQFP (fine pitch)( 12mm)
Soldering Method
*
Soldering Conditions
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 230˚C,
Duration: 30 sec. max. (at 210˚C above), Number of times: Once,
Time limit: 1 days* (thereafter 16 hours prebaking required at 125˚C)
IR30-161-1
VPS
Package peak temperature: 215˚C,
Duration: 40 sec. max. (at 200˚C above), Number of times: Once,
Time limit: 1 days* (thereafter 16 hours prebaking required at 125˚C)
VP15-161-1
Pin part heating
Pin part temperature: 300˚C max., Duration: 3 sec. max. (per device side)
For the storage period after dry-pack decompression, storage conditions are max. 25°C, 65% RH.
Note
Use of more than one soldering method should be avoided (except in the case of pin part heating).
Notice
A version of this product with improved recommended soldering conditions is available.
For details (improvements such as infrared reflow peak temperature extension (235˚C), number of times:
twice, relaxation of time limit, etc.), contact NEC sales personnel.
62
µPD75336
APPENDIX A. DIFFERENCES BETWEEN µPD75336 AND µPD75328 FUNCTIONS
Product Name
CPU core
ROM (Byte)
RAM (× 4 bits)
General register
Main system clock
Instruction cycle
µPD75336
µPD75328
75X High End
75X Standard
16256
8064
768
512
4 bits × 8 × 4
4 bits × 8 × 1
0.95 µs, 1.91 µs, 3.81 µs, 15. 3 µs
(at 4.19 MHz operation)
0.95 µs, 1.91 µs, 15.3 µs
(at 4.19 MHz operation)
122 µs (at 32.768 kHz operation)
Subsystem clock
A/D converter
• 8-bit resolution × 8 channels
(successive approximation)
• A/D operating range: VDD = 2.7 to 6.0 V
• 8-bit resolution × 6 channels
(successive approximation)
• A/D operating range: VDD = 3.5 to 6.0 V
Timer/counter
• Basic interval timer × 1
• Timer/event counter × 2
• Watch timer × 1
• Basic interval timer × 1
• Timer/event counter × 1
• Watch timer × 1
Vectored interrupt
• External: 3
• Internal: 4
• External: 3
• Internal: 3
Buzzer output (BUZ)
2 kHz, 4 kHz, 32 kHz
2 kHz
8-bit data processing
Transfer, add/subtract,
increase/decrease, compare
Transfer
Package
Product with on-chip PROM
• 80-pin plastic QFP ( 14 mm)
• 80-pin plastic TQFP (fine pitch)(
µPD75P336
12 mm)
• 80-pin plastic QFP ( 14 mm)
µPD75P328
63
µPD75336
APPENDIX B. DEVELOPMENT TOOLS
Software
Hardware
The following development tools are available for system development using the µPD75336.
*
IE-75000-R*1
IE-75001-R
75X series in-circuit emulator
IE-75000-R-EM*2
IE-75000-R/IE-75001-R emulation board
EP-75336GC-R
µPD75336 emulation probe. 80-pin conversion socket EV-9200GC-80 added.
EV-9200GC-80
EP-75336GK-R
EV-9500GK-80
µPD75336 emulation probe. 80-pin conversion socket EV-9500GK-80 added.
PG-1500
PROM programmer
PA-75P328GC
µPD75P336GC PROM programmer adapter, connected to PG-1500
PA-75P336GK
µPD75P336GK PROM programmer adapter, connected to PG-1500
IE control program
Host Machine
• PC-9800 series (MS-DOS Ver. 3.30 to 5.00A*3 )
• IBM PC/AT (PC DOS Ver. 3.1)
PG-1500 controller
RA75X relocatable assembler
1. Maintenance products
2. Not incorporated in the IE-75001-R.
3. The task swap function, which is provided with Ver. 5.00/5.00A, is not available with this software.
★
Remarks
64
For development tools manufactured by a third party, see the “75X Series Selection Guide (IF-151)”.
µPD75336
APPENDIX C.
RELATED DOCUMENTS
★
Device Related Documents
Document Name
Document Number
User’s Manual
Instruction Application Table
75X Series Selection Guide
Development Tools Related Documents
Document Name
Document Number
Hardware
IE-75000-R/IE-75001-R User’s Manual
IE-75000-R-EM User’s Manual
EP-75336GC-R User’s Manual
EP-75336GK-R User’s Manual
Software
PG-1500 User’s Manual
Operation Volume
RA75X Assembler Package User’s Manual
Language Volume
PG-1500 Controller User’s Manual
Other Related Documents
Document Name
Document Number
Package Manual
Surface Mount Technology Manual
Quality Grade on NEC Semiconductor Devices
NEC Semiconductor Device Reliability & Quality Control
Electrostatic Discharge (ESD) Test
Semiconductor Devices Quality Guarantee Guide
Microcomputer Related Products Guide Other Manufactures Volume
Note
The contents of the above related documents are subject to change without notice. The latest documents
should be used for design, etc.
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[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special
: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime systems, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation.
PC DOS and PC/AT are trademarks of IBM Corporation.