NEC UPD75218

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75218
4-BIT SINGLE-CHIP MICROCOMPUTER
The µPD75218 is a microcomputer with a CPU capable of 1-, 4-, and 8-bit-wise data processing, ROM, RAM,
I/O ports, an FIP controller/driver, a watch timer, a timer/pulse generator capable of outputting 14-bit PWM pulses,
a serial interface and a vectored interrupt function integrated on a single chip.
It is most suitable for applications which use fluorescent display tubes as display devices and require the timer/
watch function and high-speed interrupt servicing, such as VCR, CD and ECR. It can help to provide the unit with
many functions and to decrease performance costs.
The µPD75218 has larger ROM and RAM capacity than its predecessor, µPD75217. So several codes required
before have been reduced to only one code in the µPD75218 specifications.
The one-time PROM product, µPD75P218 and various development tools (IE-75001-R, assembler, etc.) are
available for system development evaluation or small production.
The following manual provides detailed description of the functions of the µPD75218. Be sure to read this manual
when you design an application system.
µPD75218 User’s Manual: IEU-692
FEATURES
• On-chip large-capacity ROM and RAM
• Program memory (ROM) : 32K × 8 bits
• Data memory (RAM)
: 1K × 4 bits
• Architecture equal to that of an 8-bit microcomputer
• High-speed operation: Minimum instruction execution time : 0.67 µs (when the microcomputer operates at
6.0 MHz)
• Instruction execution time variable function realizing a wide range of operating voltages
• On-chip programmable fluorescent indication panel (FIP) controller/driver
• Timer function : 4 ch
• 14-bit PWM output capability with the voltage synthesizer type electronic tuner
• Buzzer output capability
• Interrupt function with importance attached to applications
• For power-off detection
• For reception of remote-controller signal
• Product with an on-chip PROM : µPD75P218 (on-chip EPROM : WQFN package)
The information in this document is subject to change without notice.
Document No. IC-3035
(O. D. No. IP-8484)
Date Published November 1993 P
Printed in Japan
Major changes in this version are indicated by stars (★) in the margins.
© NEC Corporation 1993
µPD75218
ORDERING INFORMATION
Part number
Package
µ PD75218CW-×××
µ PD75218GF-×××-3BE
Remark
Quality grade
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14 × 20 mm)
Standard
Standard
××× is a ROM code.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications
LIST OF FUNCTIONS
Item
Function
Built-in memory
ROM: 32640 × 8 bits, RAM: 1024 × 4 bits
I/O line (including FIP ® dualfunction pins and excluding
FIP dedicated pins)
•
•
33 lines
•
•
Instruction cycle
• 0.67 µs, 1.33 µs, 10.7 µs (with main system clock operating at 6.0 MHz)
• 0.95 µs, 1.91 µs, 15.3 µs (with main system clock operating at 4.19 MHz)
• 122 µs (with subsystem clock operating at 32.768 kHz)
FIP controller/driver
•
•
•
•
•
CMOS input : 8 lines
CMOS I/O
: 20 lines (LED drive: 8 lines)
CMOS output : 1 line (PWM/pulse output)
P-ch open-drain output with high withstand voltage and high current: 4 lines (LED drive)
Number of segments : 9 to 16 segments
Number of digits
: 9 to 16 digits
Dimmer function
: 8 levels
Mask option for pull-down resistors
Key scan interrupt generation
Timer
4 channels
2
•
•
•
•
Timer/pulse generator : 14-bit PWM output enabled
Watch timer
: Buzzer output enabled
Timer/event counter
Basic interval timer
: Watchdog timer application capability
Serial interface
• MSB start/LSB start switchable
• Serial bus configuration capability
Vectored interrupt
External : 3, Internal : 5
Test input
External : 1, Internal : 1
System clock oscillator
• Ceramic/crystal oscillator for main system clock oscillation : 6.0 MHz standard
• Ceramic/crystal oscillator for main system clock oscillation : 4.19 MHz standard
• Crystal oscillator for subsystem clock oscillation
: 32.768 kHz standard
Mask option
• High withstand-voltage port (pull-down resistor)
• Port 6 (pull-down resistor)
Operating temperature range
–40 to +85 °C
Operating supply voltage
2.7 to 6.0 V (standby data hold : 2.0 to 6.0 V)
Package
• 64-pin plastic shrink DIP (750 mil)
• 64-pin plastic QFP (14 × 20 mm)
µPD75218
CONTENTS
1.
PIN CONFIGURATION (TOP VIEW) .........................................................................................
5
2.
BLOCK DIAGRAM ......................................................................................................................
6
3.
PIN FUNCTIONS ........................................................................................................................
7
3.1
PORT PINS ......................................................................................................................................
7
3.2
NON-PORT PINS ............................................................................................................................
8
3.3
PIN INPUT/OUTPUT CIRCUIT LIST ..............................................................................................
9
3.4
HANDLING UNUSED PINS ...........................................................................................................
10
3.5
NOTES ON USE OF THE P00/INT4 PIN AND RESET PIN .........................................................
11
3.6
NOTES ON USE OF THE XT1, XT2 AND P50 PIN ......................................................................
11
4.
MEMORY CONFIGURATION ....................................................................................................
12
5.
PERIPHERAL HARDWARE FUNCTIONS ..................................................................................
15
5.1
PORTS ..............................................................................................................................................
15
5.2
CLOCK GENERATOR ......................................................................................................................
16
5.3
BASIC INTERVAL TIMER ...............................................................................................................
17
5.4
WATCH TIMER ..............................................................................................................................
18
5.5
TIMER/EVENT COUNTER .............................................................................................................
19
5.6
TIMER/PULSE GENERATOR .........................................................................................................
20
5.7
SERIAL INTERFACE .......................................................................................................................
21
5.8
FIP CONTROLLER/DRIVER ............................................................................................................
23
6.
INTERRUPT FUNCTIONS ..........................................................................................................
24
7.
STANDBY FUNCTIONS .............................................................................................................
26
8.
RESET FUNCTIONS ...................................................................................................................
27
9.
INSTRUCTION SET ....................................................................................................................
29
10. MASK OPTION SELECTION ......................................................................................................
38
11. APPLICATION BLOCK DIAGRAM .............................................................................................
39
11.1
VCR TIMER TUNER ........................................................................................................................
39
11.2
COMPACT DISK PLAYER ..............................................................................................................
40
11.3
ECR ...................................................................................................................................................
41
3
µPD75218
★
12. ELECTRICAL SPECIFICATIONS ...............................................................................................
42
★
13. CHARACTERISTIC CURVES (FOR REFERENCE) .....................................................................
53
14. PACKAGE DIMENSIONS ...........................................................................................................
55
15. RECOMMENDED SOLDERING CONDITIONS ........................................................................
57
APPENDIX A
FUNCTIONS OF µPD752×× SERIES PRODUCTS ................................................
58
APPENDIX B
DEVELOPMENT TOOLS .........................................................................................
59
APPENDIX C
RELATED DOCUMENTS ........................................................................................
60
★
4
µPD75218
1. PIN CONFIGURATION (TOP VIEW)
P02/SO
P03/SI
P10/INT0
P11/INT1
P12/INT2
P13/TI0
VDD
S4
S5
S6
S7
S8
S9
VPRE
VLOAD
T15/S10
T14/S11
T13/S12/PH0
T12/S13/PH1
T11/S14/PH2
T10/S15/PH3
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
RESET
P53
P52
P51
P50
XT2
XT1
P20
P21
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P22
P23/BUZ
P30
P31
P32
P33
P60
P61
P62
P63
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
µ PD75218CW-× × ×
P40
S3
S2
S1
S0
P00/INT4
P01/SCK
P02/SO
P03/SI
P10/INT0
P11/INT1
P12/INT2
P13/TI0
P20
P21
P22
P23/BUZ
P30
P31
P32
P33
P60
P61
P62
P63
P40
P41
P42
P43
PPO
X1
X2
VSS
P41
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
52
32
P01/SCK
P42
53
31
P00/INT4
P43
54
30
S0
PPO
55
29
S1
X1
56
28
S2
X2
57
27
S3
VSS
58
XT1
µ PD75218GF-× × ×-3BE
62
22
S7
P52
63
21
S8
P53
64
1
S9
VPRE
VLOAD
T15/S10
T14/S11
8
T13/S12/PH0
7
T12/S13/PH1
6
T11/S14/PH2
5
T10/S15/PH3
4
T9
3
T8
2
20
9 10 11 12 13 14 15 16 17 18 19
T7
S6
P51
T6
S5
23
T5
24
61
T4
60
P50
T3
XT2
T2
S4
T1
25
T0
VDD
59
RESET
26
5
INTBT
TI0/P13
Program counter (15)
Timer/event
counter #0
Bank
INTT0
Timer/pulse
generator
Port 0
4
P00–P03
Port 1
4
P10–P13
Port 2
4
P20–P23
Port 3
4
P30–P33
Port 4
4
P40–P43
Port 5
4
P50–P53
Port 6
4
P60–P63
10
T0–T9
4
T10/S15/PH3–
T13/S12/PH0
2
T14/S11,
T15/S10
10
S0–S9
SP(8)
SBS(4)
CY
ALU
General register
2. BLOCK DIAGRAM
6
Basic interval
timer
PPO
INTTPG
SI/P03
SO/P02
ROM
Program memory
32640 × 8 bits
Decode and control
Serial interface
SCK/P01
RAM
Data memory
1024 × 4 bits
INTSIO
INT0/P10
FIP
controller/
driver
INT1/P11
INT2/P12
INT4/P00
Interrupt control
INTW
Watch timer
fX/2 N
Clock divider
System clock
generator
Sub
Standby control
VPRE
VLOAD
CPU clock
Φ
Main
INTKS
BUZ/P23
XT1 XT2 X1 X2
VDD
VSS
RESET
4
PH0–PH3
µPD75218
Port H
µPD75218
3. PIN FUNCTIONS
3.1
PORT PINS
Pin
I/O
Dualfunction pin
P00
Input
INT4
P01
Input/output
SCK
F
P02
Input/output
SO
G
P03
Input
SI
B
P10
Input
INT0
Noise elimination function available
P11
INT1
Noise elimination function available
P12
INT2
P13
TI0
P20
P21
Input/
output
–––
Function
4-bit input port (PORT0)
8-bit
I/O
After reset
Input / output
circuit typeNote
×
Input
B
Input
B
Input
E
Input
E
Input
E
Input
E
4-bit input port (PORT1)
4-bit input/output port (PORT2)
×
–––
P22
–––
P23
BUZ
P30 to P33
Input/
output
–––
Programmable 4-bit input/ output port (PORT3).
Input/output specifiable in 1-bit units.
P40 to P43
Input/
output
–––
4-bit input/output port (PORT4).
LED direct drive capability.
P50 to P53
Input/
output
–––
4-bit input/output port (PORT5).
LED direct drive capability.
P60 to P63
Input/
output
–––
Programmable 4-bit input/output port (PORT6).
Input/output specifiable in 1-bit units.
On-chip pull-down resistor available (mask
option). Suitable for key input.
×
Input
V
PH0
Output
T13/S12
4-bit P-ch open-drain output port with high
withstand voltage and high current (PORTH).
LED direct drive capability. On-chip pull-down
resistor available (mask option).
×
Low level
(with an onchip pulldown resistor)
or high
impedance.
I
PH1
T12/S13
PH2
T11/S14
PH3
T10/S15
Note
●
The circuit-type codes enclosed in circles indicate that the corresponding circuits have a Schmitt-triggered
input.
7
µPD75218
3.2
NON-PORT PINS
Pin
T0 to T9
I/O
Dualfunction pin
Output
–––
T10/S15 to
T13/S12
PH3 to PH0
T14/S11,
T15/S10
–––
After reset
Output pins with high withstand voltage Low level
(with an onand high current for digit output
chip pullOutput pins with high withstand voltage down
and high current also used for digit/seg- resistor ) or
high
ment output
impedance
Extra pins can be used as PORTH.
(without a
pull-down
Output pins with high withstand voltage
resistor)
and high current also used for digit/
segment output
Static output also possible.
High withstand-voltage output for segment
output. Static output also possible.
S0 to S8
High withstand-voltage output for segment
output
PPO
Output
–––
Timer/pulse generator pulse output
TI0
Input
P13
External event pulse input for timer/event counter
SCK
Input/output
P01
SO
Input/output
SI
Input / output
circuit typeNote
I
High
impedance
D
–––
B
Serial clock input/output
Input
F
P02
Serial data output or serial data input/output
Input
G
Input
P03
Serial data input or normal input
Input
B
INT4
Input
P00
Edge-detected vectored interrupt input (rising and falling
edge detection).
–––
B
INT0
Input
P10
Edge-detected vectored interrupt input with noise
elimination function (detection edge selection possible).
–––
B
–––
B
Input
E
P11
INT2
Input
P12
Edge-detected testable input (rising edge detection).
BUZ
Input/output
P23
Fixed frequency output (for buzzer or system clock
trimming).
X1
Input
–––
–––
–––
X2
–––
Crystal/ceramic connection pin for main system clock
oscillation.
External clock input to X1 and its inverted clock input to
X2.
–––
Crystal connection pin for subsystem clock oscillation.
External clock input to XT1. Leave XT2 open.
–––
–––
Input
–––
System reset input (low level active).
–––
B
VPRE
–––
–––
FIP controller/driver output buffer power supply.
–––
I
VLOAD
–––
–––
FIP controller/driver pull-down resistor connection pin.
–––
I
VDD
–––
–––
Positive power supply.
–––
–––
VSS
–––
–––
GND potential.
–––
–––
XT1
Input
XT2
–––
RESET
Note
8
FIP controller/
driver output
pins.
Pull-down
resistor can
be incorporated in bit
units (mask
option).
S9
INT1
★
Function
The circuit-type codes enclosed in circles indicate that the corresponding circuits have a Schmitt-triggered
input.
µPD75218
3.3
PIN INPUT/OUTPUT CIRCUIT LIST
Type A
Type F
VDD
Data
IN/OUT
Type D
Output
disable
P-ch
IN
Type B
N-ch
Input/output circuit consisting of type D push-pull output
and type B schmitt trigger input
CMOS-specified input buffer
Type B
Type G
VDD
P-ch output
disable
Data
P-ch
IN/OUT
IN
N-ch
Type B
Schmitt trigger input having hysteresis characteristics
Input/output circuit capable of switching between push-pull
output and N-ch open-drain output (with P-ch off).
Type D
Type V
VDD
Data
Data
IN/OUT
P-ch
OUT
Output
disable
Type D
Output
disable
N-ch
Type A
Pull-down
resistor
Push-pull output which can be set to high-impedance output
(off for both P-ch and N-ch)
Type E
Type I
VDD
Data
Output
disable
(Mask option)
VDD
IN/OUT
Type D
Data
P-ch
N-ch
Type A
P-ch
OUT
Pull-down resistor
(Mask option)
VLOAD
VPRE
Input/output circuit consisting of type D push-pull output
and type A input buffer
9
µPD75218
3.4
HANDLING UNUSED PINS
Pin
Recommended connection
P00/INT4
Connect to VSS
P01/SCK
Connect to VSS or VDD
P02/SO
P03/SI
P10/INT0 to P12/INT2
Connect to VSS
P13/TI0
P20 to P22
Input state : Connect to VSS or V DD
P23/BUZ
Output state : Leave open
P30 to P33
P40 to P43
P50 to P53
P60 to P63
PPO
Leave open
S0 to S9
T15/S10 to T14/S11
T0 to T9
T10/S15/PH3 to T13/S12/PH0
XT1
Connect to VSS or VDD
XT2
Leave open
VLOAD when there is no on-
Connect to VSS or VDD
chip load resistor
10
µPD75218
3.5 NOTES ON USE OF THE P00/INT4 PIN AND RESET PIN
P00/INT4 and RESET pins have the function (especially for IC test) to test µ PD75218 internal operations in addition
to the functions described in sections 3.1 and 3.2.
The test mode is set when a voltage larger than VDD is applied to one of these pins. If noise larger than VDD is
applied in normal operation, the test mode may be set thereby adversely affecting normal operation.
Since there is a display output pin having a high-voltage amplitude (35 V) next to the P00/INT4 and RESET pins,
if cables for the related signals are routed in parallel, wiring noise larger than VDD may be applied to the P00/INT4
and RESET pins causing errors.
Thus, carry out wiring so that wiring noise can be minimized, If noise still cannot be suppressed, take the measure
against noise using the following external components.
•
Connecting a diode between the pins and VDD
•
Connecting a capacitor between the pins and VDD
VDD
VDD
VDD
VDD
P00/INT4, RESET
P00/INT4, RESET
3.6 NOTES ON USE OF THE XT1, XT2 AND P50 PIN
When selecting the 32.768 kHz subsystem clock connected to the XT1 and XT2 pins as the watch timer source
clock, the signal to be input or output to the P50 pin next to the XT2 pin must be a signal required to be switched
between high and low the minimum number of times (once/second or less).
If the P50 pin signal is switched frequently between high and low, a spike is generated in the XT2 pin because
of capacitance coupling of the P50 and XT2 pins and the correct watch functions cannot be achieved (the watch
becomes fast).
If it is necessary to allow the P50 pin signal to switch between high and low, mount an external capacitor to the
P50 pin as shown below.
µ PD75218
P50
XT1
XT2
0.0068 µ F
32.768 kHz
11
µPD75218
4. MEMORY CONFIGURATION
• Program memory (ROM): 32640 words × 8 bits
• 0000H and 0001H: Vector table which contains the program start address after reset
• 0002H to 000FH : Vector table which contains the program start addresses when interrupts occur
• 0020H to 007FH : Table area referenced by a GETI instruction
• Data memory
• Data area
: 1024 words × 4 bits (000H to 3FFH)
• Peripheral hardware area : 128 words × 4 bits (F80H to FFFH)
12
µPD75218
Fig. 4-1 Program Memory Map
0000H MBE RBE Internal reset start address (high-order 6 bits)
Internal reset start address (low-order 8 bits)
0002H MBE RBE INTBT/INT4 start address
(high-order 6 bits)
INTBT/INT4 start address
(low-order 8 bits)
0004H MBE RBE INT0 start address
(high-order 6 bits)
INT0 start address
(low-order 8 bits)
0006H MBE RBE INT1 start address
(high-order 6 bits)
INT1 start address
(low-order 8 bits)
0008H MBE RBE INTSO start address
Branch address
specified in BRA !addr
instruction
(high-order 6 bits)
INTSO start address
(low-order 8 bits)
000AH MBE RBE INTT0 start address
(high-order 6 bits)
INTT0 start address
Entry address
specified in
CALLF !faddr
instruction
(low-order 8 bits)
000CH MBE RBE INTTPG start address
(high-order 6 bits)
INTTPG start address
(low-order 8 bits)
000EH MBE RBE INTKS start address
(high-order 6 bits)
INTKS start address
(low-order 8 bits)
Branch address
specified in
BRCB !caddr
instruction
Branch address
specified in CALLA !addr
instruction
Relative branch address
specified in BR $addr
instruction (–15 to –1,
+2 to +16)
Branch address
specified in BR !addr
instruction
0020H
GETI instruction reference table
007FH
0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
3FFFH
4000H
4FFFH
5000H
5FFFH
6000H
6FFFH
7000H
7F7FH
Branch address
specified in CALL !addr
instruction
Branch/call
address specified
in GETI instruction
Branch address specified in BRCB !caddr
instruction
Branch address specified in BRCB !caddr
instruction
Branch address specified in BRCB !caddr
instruction
Branch address specified in BRCB !caddr
instruction
Branch address specified in BRCB !caddr
instruction
Branch address specified in BRCB !caddr
instruction
Branch address specified in BRCB !caddr
instruction
Caution The start address of an interrupt vector shown above consists of 14 bits. So the start address must be
set within a 16K-byte space (0000H to 3FFFH).
Remark In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC changed
is enabled by BR PCDE and BR PCXA instructions.
13
µPD75218
Fig. 4-2 Data Memory Map
Data memory
General
register
area
Memory bank
000H
(32 × 4)
01FH
0
020H
256 × 4
0FFH
100H
Stack
area
Data area
Static RAM
(1024 × 4)
256 × 4
Display
data
memory,
etc.
1BFH
1C0H
1
(64 × 4)
1FFH
200H
256 × 4
2
256 × 4
3
2FFH
300H
3 FFH
Not contained
F80H
Peripheral
hardware area
128 × 4
FFFH
14
15
µPD75218
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORTS
The µPD75218 has the following three types of I/O port:
• 8 CMOS input pins (PORT0 and PORT1)
• 20 CMOS I/O pins (PORT2, PORT3, PORT4, PORT5, and PORT6)
• 4 P-ch open-drain output pins with high withstand voltage and high current (PORTH)
Total: 32 pins
Table 5-1 Functions of Ports
Port
PORT0
Function
4-bit input
PORT1
PORT2
PORT4
PORT5
4-bit
input/output
PORT3
PORT6
PORTH
Operation and feature
Remarks
Always read or test possible irrespective of the dual-function
pin operating mode.
Shares the pins with SI, SO, SCK
and INT4.
Always read or test possible, P10 and P11 are inputs with the
noise elimination function.
Shares the pins with INT0 to
INT2 and TI0.
Can be set to the input or output mode in 4-bit units.
Ports 4 and 5 can input/output data in pairs in 8-bit units.
Ports 4 and 5 can directly drive LEDs.
P23 shares the pin with BUZ.
Can be set bit-wise to the input or output mode. Port 6 can
incorporate a pull-down resistor by mask option.
4-bit output
P-ch open-drain output port with high withstand voltage and
high current. Can drive an FIP and LED directly. Can
incorporate a pull-down resistor in bit units by mask option.
Shares the pins with T10/S15 to
T13/S12.
15
µPD75218
5.2 CLOCK GENERATOR
Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control
register (SCC).
The main system clock or subsystem clock can be selected.
The instruction execution time is variable.
0.67 µs, 1.33 µs, 10.7 µs (main system clock: 6.0 MHz)
0.95 µs, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz)
122 µs (subsystem clock: 32.768 kHz)
Fig. 5-1 Clock Generator Block Diagram
XT1
XT2
Subsystem
clock generator
fXT
Watch timer
Timer/pulse
generator
Main system
clock generator
fX
Selector
X1
X2
• FIP controller
• Basic interval timer (BT)
• Timer/event counter
• Serial interface
• Watch timer
• INT0 noise eliminator
1/8 to 1/4096
fXX
Frequency divider
1/2 1/6
SCC
Oscillation
stop
Frequency
divider
Selector
SCC3
SCC0
1/4
• CPU
• INT0 noise eliminator
• INT1 noise eliminator
PCC
PCC0
Internal bus
Φ
PCC1
4
HALT F/F
HALTNote
STOPNote
PCC2
S
PCC3
R
PCC2 and
PCC3
clear
STOP F/F
Q
Q
Wait release signal from BT
S
RES signal (internal reset)
Note
Instruction execution
R
Remarks 1. fX = Main system clock frequency
2. fXT = Subsystem clock frequency
3. fXX = System clock frequency
4.
5.
6.
7.
★
Φ = CPU clock
PCC: Processor clock control register
SCC: System clock control register
1 clock cycle (tCY) of Φ is 1 machine cycle of an instruction. For tCY, see ”AC Characteristics“ in
Chapter 12.
16
Standby release signal from
interrupt control circuit
µPD75218
5.3 BASIC INTERVAL TIMER
The basic interval timer has the following functions:
•
•
•
•
Interval timer operation to generate reference time
Watchdog timer application to detect inadvertent program loop
Wait time select and count upon standby mode release
Count contents read
Fig. 5-2 Basic Interval Timer Configuration
From clock
generator
Clear
Clear
fXX/25
fXX/27
Set
Basic interval timer
(8-bit frequency divider)
MPX
BT interrupt
request flag
fXX/29
BT
fXX/212
IRQBT
Vectored
interrupt
request
signal
3
BTM3
SET1Note
BTM2
BTM1
BTM0
Wait release
signal during
standby release
BTM
8
4
Internal bus
Note
Instruction execution
17
µPD75218
5.4 WATCH TIMER
The µPD75218 incorporates one channel of watch timer. The watch timer has the following functions:
• Sets the test flag (IRQW) at 0.5 sec intervals.
The standby mode can be released by IRQW.
• 0.5 second interval can be set with the main system clock and subsystem clock.
• The fast mode enables to set 128-time (3.91 ms) interval useful to program debugging and inspection.
• The fixed frequencies (2.048 kHz) can be output to the P23/BUZ pin for use to generate buzzer sound
and trim the system clock oscillator frequency.
• Since the frequency divider can be cleared, the watch can be started from zero second.
Fig. 5-3 Watch Timer Block Diagram
fW
(256 Hz : 3.91 ms)
7
2
From
clock
generator
fXX
128
(32.768 kHz)
Selector
fW
14
2
fW
Frequency divider
(32.768 kHz)
fXT
(32.768 kHz)
INTW
IRQW
set signal
Selector
2 Hz
0.5 sec
fW
16
(2.048 kHz) Clear
Output buffer
P23/BUZ
WM
WM7 WM6
PORT2.3
WM5
WM4 WM3 WM2
WM1
WM0
P23
output
latch
Bit 2 of PMGB
Port 2
input/output
mode
8
Internal bus
Remark
Values when fXX is 4.194304 MHz and fXT is 32.768 kHz are indicated in parentheses.
Caution When the main system clock operates at 6.0 MHz, a time interval of 0.5 second cannot be produced.
Before producing this time interval, the main system clock must be changed to the subsystem clock.
18
µPD75218
5.5 TIMER/EVENT COUNTER
The µPD75218 incorporates one channel of timer/event counter. The timer/event counter has the following
functions:
• Program interval timer operation
• Event counter operation
• Count state read function
Fig. 5-4 Timer/Event Counter Block Diagram
Internal bus
8
SET1Note
8
8
TM0
TMOD0
Modulo register (8)
TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMn1 TMn0
8
Match
Comparator (8)
Input buffer
INTT0
IRQT0
set signal
8
T0
P13/TI0
From clock
generator





(See Fig. 5-1.)
Count register (8)
MPX
CP
Clear
Timer operation start
IRQT0
clear
Note
Instruction execution
19
µPD75218
5.6 TIMER/PULSE GENERATOR
The µPD75218 incorporates one channel of timer/pulse generator which can be used as a timer or a pulse
generator. The timer/pulse generator has the following functions:
(a)
Functions available in the timer mode
• 8-bit interval timer operation (IRQTPG generation) enabling the clock source to be varied at 5 levels
• Square wave output to PPO pin
(b)
Functions available in the PWM pulse generation mode
• 14-bit accuracy PWM pulse output to the PPO pin (Used as a digital-to-analog converter and applicable
to tuning)
2 15
• Fixed time interval (
= 5.46 ms when the microcomputer operates at 6.0 MHz)Note interrupt generation
fX
If pulse output is not necessary, the PPO pin can be used as a 1-bit output port.
Note
7.81 ms when the microcomputer operates at 4.19 MHz
Caution If the STOP mode is set while the timer/pulse generator is in operation, erroneous operation may result.
To prevent that from occurring, preset the timer/pulse generator to the stop state using its mode
register.
Fig. 5-5 Block Diagram of Timer/Pulse Generator (Timer Mode)
Internal bus
8
8
MODL
Modulo register L (8)
MODH
Modulo register H (8)
TPGM3
(Set to 1)
INTTPG
IRQTPG
set signal
Modulo latch H (8)
8
Match
Comparator (8)
Output buffer
Selector
T F/F
PPO
Frequency
divider
fX
1/2
TPGM1
CP
Prescalar select latch (5)
Clear
20
Set
8
Count register (8)
Clear
TPGM4 TPGM5 TPGM7
µPD75218
Fig. 5-6 Timer/Pulse Generator Block Diagram (PWM Pulse Generation Mode)
Internal bus
8
8
MODH
Modulo register H (8)
MODL
Modulo register L (8)
(2)
TPGM3
MODL7-2 (6)
MODH (8)
Modulo latch (14)
Output buffer
TPGM1
fX
PWM pulse generator
1/2
Selector
PPO
Frequency divider
INTTPG
TPGM5
(IRQTPG set signal)
15
2
(
= 5.46 ms : when fX is 6.0 MHz)Note
fX
Note
TPGM7
7.81 ms when the microcomputer operates at 4.19 MHz.
5.7 SERIAL INTERFACE
The serial interface has the following functions:
• Clock synchronous 8-bit send/receive operation (simultaneous send/receive)
• Clock synchronous 8-bit serial bus operation (data input/output from the SO pin. N-ch open-drain SO output)
• Start LSB/MSB switching
These functions facilitate data communication with another microcomputer of µPD7500 series or 78K series via
a serial bus and coupling with peripheral devices.
21
22
Fig 5-7 Serial Interface Block Diagram
Internal bus
8
8
Selector
P03/SI
SIO0
SET1Note 2
SIO7
SIO
SIOM
Shift register (8)
Note 1
P02/SO
8
SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0
SO output
latch
Serial clock
counter (3)
INTSIO
IRQSIO
set signal
Overflow
Clear
IRQSIO
clear signal
Serial start
P01/SCK
R
Q
Φ
S
fXX/24
MPX
fXX/210
CMOS output and N-ch open-drain output switchable output buffer.
Instruction execution
µPD75218
Notes 1.
2.
µPD75218
5.8 FIP CONTROLLER/DRIVER
The FIP controller/driver in the µPD75218 has the same functions as that in its predecessor, µPD75216A:
• The FIP controller/driver outputs the segment signal by automatically reading display data (DMA operation)
and automatically generates the digit signal.
• The FIP controller/driver can control the FIP of 9 to 16 segments and 9 to 16 digits with the display mode register
(DSPM) and the digit select register (DIGS) (within the range of up to 26 display outputs).
• The display outputs unused for dynamic display can be used as static outputs.
• The dimmer function provides eight levels of intensity.
• Such hardware is contained that a key scan application is possible.
•
•
•
•
A
•
•
A
A key scan interrupt (IRQKS) is caused. (A key scan timing is detected.)
Key scan data can be output from key scan registers (KS0 and KS1) onto a segment output pin.
high-voltage output pin (40 V) is provided which can directly drive the FIP.
Pins dedicated to segments (S0 to S9): VOD = 40 V, IOD = 3 mA
Digit output pins (T0 to T15): VOD = 40 V, IOD = 15 mA
mask option enables a pull-down resistor to be incorporated for each bit.
Fig. 5-8 FIP Controller/Driver Block Diagram
Internal bus
Display data memory
(64 × 4 bits)
Key scan registers
(KS0 and KS1)
4
4
4
Display
mode
register
Digit
select
register
Dimmer
select
register
Key scan
flag (KSF)
Port H
12
4
Digit signal
generator
Segment data latch (16)
4
IRQKS
generation
signal
4
Selector
10
2
2
4
4
Selector
2
4
10
Output buffer with a high withstand voltage
10
S0-S9
2
T15/S10
and T14/S11
4
T13/S12/PH0T10/S15/PH3
10
T0-T9
VLOAD VPRE
Caution The FIP controller/driver can only operate at the high and intermediate speeds (PCC = 0011B or 0010B)
of the main system clock (SCC.0 = 0). It may cause errors with any other clock or in the standby mode.
Thus, be sure to stop FIP controller operation (DSPM.3 = 0) and then shift the unit to any other clock mode
or the standby mode.
23
µPD75218
6. INTERRUPT FUNCTIONS
The µPD75218 has eight types of interrupt sources and can generate multiple interrupts with priority order.
It is also equipped with two types of test sources. INT2 is an edge detected testable input.
The µPD75218 interrupt control circuit has the following functions:
• Hardware-controlled vectored interrupt function which can control interrupt acknowledge with the interrupt
enable flag (IE×××) and the interrupt master enable flag (IME).
• Function of setting any interrupt start address.
• Multiple interrupt function which can specify priority order with the interrupt priority select register (IPS).
• Interrupt request flag (IRQ×××) test function. (Interrupt generation can be checked by software.)
• Standby mode release function (Interrupts to be released can be selected by interrupt enable flags.)
24
Fig. 6-1 Interrupt Control Circuit Block Diagram
Internal bus
2
2
IM1
IM0
INT
BT
Both edges
detection
circuit
INT4/
P00
INT0/
P10
Note
INT1/
P11
Note
Edge
detection
circuit
Edge
detection
circuit
Note
IPS
IST
Decoder
IRQBT
IRQ4
VRQn
IRQ0
IRQ1
IRQSIO
INTT0
IRQT0
Priority control
circuit
Vector
table
address
generator
circuit
IRQTPG
INTKS
IRQKS
INTW
IRQW
Rising edge
detection
circuit
2
Interrupt enable flag (IE XXX )
INTSIO
INTTPG
INT2/
P12
(IME)
4
Standby release
signal
IRQ2
Noise eliminator
µPD75218
25
µPD75218
7. STANDBY FUNCTIONS
Two standby modes (STOP mode and HALT mode) are available for the µPD75218 to decrease power consumption in the program standby mode.
Table 7-1 Operation Status in Standby Mode
HALT mode
STOP mode
STOP instruction
HALT instruction
System clock when set
Setting enabled only for main system
clock
Setting enabled for either main system
clock or subsystem clock
Clock oscillator
Oscillator stops only for main system
clock
Stops only for CPU clock Φ (oscillation
continued)
Basic interval timer
Operation stopped
Operation continued (IRQBT set at reference
time intervals)
Serial interface
Operation enabled only when external
SCK input is selected for serial clock
Operation enabled when serial clock other
than Φ is specified
Timer/event counter
Operation enabled only when TI0 pin
input is specified for count clock
Operation enabled
Timer/pulse generator
Operation stopped
Operation enabled
Watch timer
Operation enabled only fXT is selected for Operation enabled
count clock
FIP controller/driver
Operation disabled (display off mode set before disabling)
CPU
Operation stopped
Operating State
Set instruction
Release signal
26
Interrupt request signals (except INT0, INT1, and INT2) from operable hardware
enabled by interrupt enable flags, or RESET input.
µPD75218
8. RESET FUNCTIONS
The reset signal (RES) generator has a configuration shown in Fig. 8-1.
Fig. 8-1 Reset Signal Generator
Internal reset signal
(RES)
RESET
Fig. 8-2 shows the reset operation.
Fig. 8-2 Reset Operation by RESET Input
Wait
(21.8 ms/when the microcomputer
operates at 6.0 MHz)Note
RESET input
Normal operation mode or
standby mode
HALT mode
Normal operation
mode
Internal reset operation
Note
31.3 ms when the microcomputer operates at 4.19 MHz
Table 8-1 lists the hardware statuses after reset operation.
27
µPD75218
Table 8-1 Hardware Statuses after Reset Operation
Hardware
Program counter (PC)
PSW
Carry flag (CY)
Skip flag (SK0-SK2)
Interrupt status flag (IST0, IST1)
RESET input during operation
Set the low-order six bits at
address 0000H in program
memory to PC13-8, set the
contents of address 0001H to
PC7-0, and set PC14 to zero.
Set the low-order six bits at
address 0000H in program
memory to PC13-8, set the
contents of address 0001H to
PC7-0, and set PC14 to zero.
Retained
Undefined
0
0
0
0
Set bit 6 of address 0000H in
program memory to RBE and
set bit 7 to MBE.
Set bit 6 of address 0000H in
program memory to RBE and
set bit 7 to MBE.
Stack pointer (SP)
Undefined
Undefined
Stack bank selection register (SBS)
Undefined
Undefined
RetainedNote
Undefined
Retained
Undefined
0, 0
0, 0
Undefined
Undefined
0
0
Bank enable flag (MBE, RBE)
Data memory (RAM)
General register (X, A, H, L, D, E, B, C)
Bank selection register (MBS, RBS)
Basic interval timer
Counter (BT)
Mode register (BTM)
Timer/event counter Counter (T0)
Modulo register (TMOD0)
Mode register (TM0)
0
0
FFH
FFH
0
0
Retained
Undefined
Timer/pulse
generator
Modulo register (MODH, MODL)
Mode register (TPGM)
0
0
Clock timer
Mode register (WM)
0
0
Serial interface
Shift register (SIO)
Retained
Undefined
Set bit 4 to 1 and other bits to 0.
Set bit 4 to 1 and other bits to 0.
Processor clock control
register (PCC)
0
0
System clock control register
(SCC)
0
0
Interrupt request flag (IRQ×××)
Mode register (SIOM)
Clock generator
Interrupt
Digital port
Reset (0)
Reset (0)
Interrupt enable flag (IE×××)
0
0
Priority specification flag (IPS)
0
0
INT0/INT1 mode register (IM0,
IM1)
0, 0
0, 0
Output buffer
Off
Off
Output latch
Cleared (0)
Cleared (0)
0
0
Retained
Undefined
Display mode register (DSPM)
0
0
Digit selection register (DIGS)
1000B
1000B
I/O mode register (PMGA, PMGB)
PORT H
Output latch
FIP controller/driver
Dimmer selection register (DIMS)
Display data memory
Output buffer
Note
28
RESET input in standby mode
0
0
Retained
Undefined
Off
Off
Data from address 0F8H to address 0FDH in the data memory becomes undefined by RESET input.
µPD75218
9. INSTRUCTION SET
(1) Representation format and description method of operands
An operand is described in the operand field of each instruction according to the description method
corresponding to the operand representation format of the instruction (refer to "RA75X Assembler Package
User's Manual, Language" (EEU-1363) for details). When two or more elements are described in the
description method field, select one of them. Uppercase letters, a plus sign (+), and a minus sign (-) are
keywords, so they can be used without alteration.
Specify an appropriate numeric value or label for immediate data.
Representation format
Note
Description method
reg
X, A, B, C, D, E, H, L
reg1
X, B, C, D, E, H, L
rp
XA, BC, DE, HL
rp1
BC, DE, HL
rp2
BC, DE
rp’
XA, BC, DE, HL, XA’, BC’, DE’, HL’
rp’1
BC, DE, HL, XA’, BC’, DE’, HL’
rpa
HL, HL+, HL-, DE, DL
rpa1
DE, DL
n4
4-bit immediate data or label
n8
8-bit immediate data or label
mem
8-bit immediate data or labelNote
bit
2-bit immediate data or label
fmem
FB0H-FBFH/FF0H-FFFH immediate data or label
pmem
FC0H-FFFH immediate data or label
addr1
0000H-7F7FH immediate data or label
addr
0000H-3F7FH immediate data or label
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H-7FH immediate data (bit 0 = 0) or label
PORTn
PORT0-PORT6
IE×××
IEBT, IESIO, IET0, IETPG, IE0, IE1, IEKS, IEW, IE4
RBn
RB0-RB3
MBn
MB0, MB1, MB2, MB3, MB15
Only even addresses can be specified for 8-bit data processing.
29
µPD75218
(2) Legend
A
: A register, 4-bit accumulator
B
: B register, 4-bit accumulator
C
: C register, 4-bit accumulator
D
: D register, 4-bit accumulator
E
: E register, 4-bit accumulator
H
: H register, 4-bit accumulator
L
: L register, 4-bit accumulator
X
: X register, 4-bit accumulator
XA
: Register pair (XA), 8-bit accumulator
BC
: Register pair (BC), 8-bit accumulator
DE
: Register pair (DE), 8-bit accumulator
HL
: Register pair (HL), 8-bit accumulator
XA’
: Extended register pair (XA’)
BC’
: Extended register pair (BC’)
DE’
: Extended register pair (DE’)
HL’
: Extended register pair (HL’)
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag, bit accumulator
PSW
: Program status word
MBE
: Memory bank enable flag
RBE
: Register bank enable flag
PORTn : Port n (n = 0 to 6)
IME
: Interrupt master enable flag
IPS
: Interrupt priority specification register
IE××× : Interrupt enable flag
30
RBS
: Register bank select register
MBS
: Memory bank select register
PCC
: Processor clock control register
.
: Address/bit delimiter
(××)
: Contents addressed by ××
××H
: Hexadecimal data
µPD75218
(3) Explanation of the symbols in the addressing area field
Remarks 1.
2.
3.
4.
*1
MB = MBE•MBS
(MBS = 0, 1, 2, 3, or 15)
*2
MB = 0
*3
MBE = 0: MB = 0 (00H-7FH)
MB = 15 (80H-FFH)
MBE = 1: MB = MBS (MBS = 0, 1, 2, 3, or 15)
*4
MB = 15, fmem = FB0H-FBFH or
FF0H-FFFH
*5
MB = 15, pmem = FC0H-FFFH
*6
addr = 0000H-3F7FH
*7
addr = (Current PC) - 15 to (Current PC) - 1 or
(Current PC) + 2 to (Current PC) + 16
*8
caddr = 0000H-0FFFH
1000H-1FFFH
2000H-2FFFH
3000H-3FFFH
4000H-4FFFH
5000H-5FFFH
6000H-6FFFH
7000H-7F7FH
*9
faddr = 0000H-07FFH
*10
taddr = 0020H-007FH
*11
addr1 = 0000H-7F7FH
(PC14,13,12
(PC14,13,12
(PC14,13,12
(PC14,13,12
(PC14,13,12
(PC14,13,12
(PC14,13,12
(PC14,13,12
=
=
=
=
=
=
=
=
000B)
001B)
010B)
011B)
100B)
101B)
110B)
111B)
Data memory
addressing
or
or
or
or
or
or
or
Program
memory
addressing
MB indicates an accessible memory bank.
For *2, MB is always 0 irrespective of MBE and MBS.
For *4 and *5, MB is always 15 irrespective of MBE and MBS.
*6 to *11 indicate each addressable area.
(4) Explanation of the machine cycle column
S represents the number of machine cycles required when a skip instruction with the skip function performs
a skip operation. S assumes one of the following values:
• When no skip operation is performed
: S=0
• When a 1-byte instruction or 2-byte instruction is skipped : S = 1
• When a 3-byte instruction is skipped
: S=2
Caution The GETI instruction is skipped in one machine cycle.
One machine cycle is equal to one cycle of the CPU clock Φ (= tCY), and three types of times are available for
selection according to the PCC setting.
31
µPD75218
Instruction Mnemonic
Transfer
MOV
XCH
Table
reference
32
MOVT
Operand
Number Machine
Operation
of bytes cycle
Addressing area
Skip
condition
A,#n4
1
1
A ← n4
reg1,#n4
2
2
reg1 ← n4
XA,#n8
2
2
XA ← n8
String effect A
HL,#n8
2
2
HL ← n8
String effect B
rp2,#n8
2
2
rp2 ← n8
A,@HL
1
1
A ← (HL)
*1
A,@HL+
1
2+S
A ← (HL), then L ← L + 1
*1
L=0
A,@HL-
1
2+S
A ← (HL), then L ← L - 1
*1
L = FH
A,@rpa1
1
1
A ← (rpa1)
*2
XA,@HL
2
2
XA ← (HL)
*1
@HL,A
1
1
(HL) ← A
*1
@HL,XA
2
2
(HL) ← XA
*1
A,mem
2
2
A ← (mem)
*3
XA,mem
2
2
XA ← (mem)
*3
mem,A
2
2
(mem) ← A
*3
mem,XA
2
2
(mem) ← XA
*3
A,reg
2
2
A ← reg
XA,rp’
2
2
XA ← rp’
reg1,A
2
2
reg1 ← A
rp’1,XA
2
2
rp’1 ← XA
A,@HL
1
1
A ↔ (HL)
*1
A,@HL+
1
2+S
A ↔ (HL), then L ← L + 1
*1
L=0
A,@HL-
1
2+S
A ↔ (HL), then L ← L - 1
*1
L = FH
A,@rpa1
1
1
A ↔ (rpa1)
*2
XA,@HL
2
2
XA ↔ (HL)
*1
A,mem
2
2
A ↔ (mem)
*3
XA,mem
2
2
XA ↔ (mem)
*3
A,reg1
1
1
A ↔ reg1
XA,rp’
2
2
XA ↔ rp’
XA,@PCDE
1
3
XA ← (PC14-8+DE)ROM
XA,@PCXA
1
3
XA ← (PC14-8+XA)ROM
XA, @BCDE
1
3
XA ← (BCDE)ROM
*11
XA, @BCXA
1
3
XA ← (BCXA)ROM
*11
String effect A
µPD75218
Operand
Instruction Mnemonic
Bit
transfer
Arithmetic/logical
ing area
Skip
condition
2
CY ← (fmem.bit)
*4
CY,pmem.@L
2
2
CY ← (pmem7-2+L3-2.bit(L 1-0))
*5
CY,@H+mem.bit
2
2
CY ← (H+mem3-0.bit)
*1
fmem.bit,CY
2
2
(fmem.bit) ← CY
*4
pmem.@L,CY
2
2
(pmem7-2+L3-2.bit(L1-0)) ← CY
*5
@H+mem.bit,CY
2
2
(H+mem3-0.bit) ← CY
*1
A,#n4
1
1+S
A ← A + n4
carry
XA,#n8
2
2+S
XA ← XA + n8
carry
A,@HL
1
1+S
A ← A + (HL)
XA,rp’
2
2+S
XA ← XA + rp’
carry
rp’1,XA
2
2+S
rp’1 ← rp’1 + XA
carry
A,@HL
1
1
A,CY ← A + (HL) + CY
XA,rp’
2
2
XA,CY ← XA + rp’ + CY
rp’1,XA
2
2
rp’1,CY ← rp’1 + XA + CY
A,@HL
1
1+S
A ← A - (HL)
XA,rp’
2
2+S
XA ← XA - rp’
borrow
rp’1,XA
2
2+S
rp’1 ← rp’1 - XA
borrow
A,@HL
1
1
A,CY ← A - (HL) - CY
XA,rp’
2
2
XA,CY ← XA - rp’ - CY
rp’1,XA
2
2
rp’1,CY ← rp’1 - XA - CY
A,#n4
2
2
A←A
A,@HL
1
1
∧
A←A∧
XA,rp’
2
2
XA ← XA
rp’1,XA
2
2
rp’1 ← rp’1
A,#n4
2
2
A,@HL
1
1
XA,rp’
2
2
rp’1,XA
2
2
A,#n4
2
2
A,@HL
1
1
XA,rp’
2
2
rp’1,XA
2
2
∨ n4
A ← A ∨ (HL)
XA ← XA ∨ rp’
rp’1 ← rp’1 ∨ XA
A ← A ∨ n4
A ← A ∨ (HL)
XA ← XA ∨ rp’
rp’1 ← rp’1 ∨ XA
RORC
A
1
1
CY ← A0, A3 ← CY, An-1 ← An
NOT
A
2
2
A←A
ADDS
SUBC
AND
OR
XOR
lation
Address-
2
SUBS
tor manipu-
Operation
of bytes cycle
CY,fmem.bit
MOV1
ADDC
Accumula-
Number Machine
*1
carry
*1
*1
borrow
*1
n4
*1
(HL)
∧
rp’
∧
XA
A←A
*1
*1
33
µPD75218
Operand
Instruction Mnemonic
34
Addressing area
Skip
condition
1
1+S
reg ← reg + 1
reg = 0
rp1
1
1+S
rp1 ← rp1 + 1
rp1 = 00H
@HL
2
2+S
(HL) ← (HL) + 1
*1
(HL) = 0
mem
2
2+S
(mem) ← (mem) + 1
*3
(mem) = 0
reg
1
1+S
reg ← reg - 1
reg = FH
rp’
2
2+S
rp’ ← rp’ - 1
rp’ = FFH
reg,#n4
2
2+S
Skip if reg = n4
reg = n4
@HL,#n4
2
2+S
Skip if (HL) = n4
*1
(HL) = n4
A,@HL
1
1+S
Skip if A = (HL)
*1
A = (HL)
XA,@HL
2
2+S
Skip if XA = (HL)
*1
XA = (HL)
A,reg
2
2+S
Skip if A = reg
A = reg
XA,rp’
2
2+S
Skip if XA = rp’
XA = rp’
SET1
CY
1
1
CY ← 1
CLR1
CY
1
1
CY ← 0
SKT
CY
1
1+S
NOT1
CY
1
1
DECS
Carry flag
manipulation
Operation
of bytes cycle
reg
Increment/ INCS
decrement
Comparison
Number Machine
SKE
Skip if CY = 1
CY ← CY
CY = 1
µPD75218
Instruction Mnemonic
SET1
Memory
bit
manipulation
CLR1
SKT
SKF
SKTCLR
AND1
OR1
XOR1
Branch
BR
Operand
Number Machine
Operation
of bytes cycle
Addressing area
Skip
condition
mem.bit
2
2
(mem.bit) ← 1
*3
fmem.bit
2
2
(fmem.bit) ← 1
*4
pmem.@L
2
2
(pmem 7-2+L3-2.bit(L 1-0)) ← 1
*5
@H+mem.bit
2
2
(H+mem3-0.bit) ← 1
*1
mem.bit
2
2
(mem.bit) ← 0
*3
fmem.bit
2
2
(fmem.bit) ← 0
*4
pmem.@L
2
2
(pmem 7-2+L3-2.bit(L 1-0)) ← 0
*5
@H+mem.bit
2
2
(H+mem3-0.bit) ← 0
*1
mem.bit
2
2+S
Skip if (mem.bit) = 1
*3
(mem.bit) = 1
fmem.bit
2
2+S
Skip if (fmem.bit) = 1
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem7-2+L3-2.bit(L 1-0)) = 1
*5
(pmem.@L) = 1
@H+mem.bit
2
2+S
Skip if (H+mem3-0.bit) = 1
*1
(@H+mem.bit) = 1
mem.bit
2
2+S
Skip if (mem.bit) = 0
*3
(mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 0
*4
(fmem.bit) = 0
pmem.@L
2
2+S
Skip if (pmem7-2+L3-2.bit(L 1-0)) = 0
*5
(pmem.@L) = 0
@H+mem.bit
2
2+S
Skip if (H+mem3-0.bit) = 0
*1
(@H+mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 1 and clear
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1 and clear
*5
(pmem.@L) = 1
@H+mem.bit
2
2+S
Skip if (H+mem3-0.bit) = 1 and clear
*1
(@H+mem.bit) = 1
CY,fmem.bit
2
2
CY,pmem.@L
2
2
CY,@H+mem.bit
2
2
CY,fmem.bit
2
2
CY,pmem.@L
2
2
CY,@H+mem.bit
2
2
CY,fmem.bit
2
2
CY,pmem.@L
2
2
CY,@H+mem.bit
2
2
∧ (fmem.bit)
CY ← CY ∧ (pmem7-2+L3-2.bit(L1-0))
CY ← CY ∧ (H+mem3-0.bit)
CY ← CY ∨ (fmem.bit)
CY ← CY ∨ (pmem7-2+L3-2.bit(L1-0))
CY ← CY ∨ (H+mem3-0.bit)
CY ← CY ∨ (fmem.bit)
CY ← CY ∨ (pmem7-2+L3-2.bit(L1-0))
CY ← CY ∨ (H+mem3-0.bit)
addr1
—
—
PC14-0 ← addr1
CY ← CY
*4
*5
*1
*4
*5
*1
*4
*5
*1
*11
(The assembler selects an appropriate instruction from the BR !addr, BRA
!addr1, BRCB !caddr, and BR $addr
instructions.)
$addr
1
2
PC14-0 ← addr
*7
!addr
3
3
PC14 ← 0, PC13-0 ← !addr
*6
PCDE
2
3
PC14-0 ← PC14-8 + DE
PCXA
2
3
PC14-0 ← PC14-8 + XA
BCDE
2
3
PC14-0 ← BCDE
BCXA
2
3
PC14-0 ← BCXA
BRA
!addr1
3
3
PC14-0 ← !addr1
*11
BRCB
!caddr
2
2
PC14-0 ← PC14,13,12 + caddr11-0
*8
35
µPD75218
Operand
Instruction Mnemonic
Subroutine stack
control
CALL
(SP-6)(SP-3)(SP-4) ← PC11-0
*6
3
3
(SP-6)(SP-3)(SP-4) ← PC11-0
(SP-5) ← 0,PC14,PC13, PC12
(SP-2) ← ×,×,MBE,RBE
PC14-0 ← addr1, SP ← SP - 6
*11
CALLF
!faddr
2
3
(SP-6)(SP-3)(SP-4) ← PC11-0
(SP-5) ← 0,PC14,PC13, PC12
(SP-2) ← ×,×,MBE,RBE
PC14-0 ← 0000, faddr, SP ← SP - 6
*9
RET
1
3
×,×,MBE,RBE ← (SP+4)
PC11-0 ← (SP)(SP+3)(SP+2)
×,PC14,PC13,PC12 ← (SP+1)
SP ← SP + 6
RETS
1
3+S
×,×,MBE,RBE ← (SP+4)
PC11-0 ← (SP)(SP+3)(SP+2)
×,PC14,PC13,PC12 ← (SP+1)
SP ← SP + 6
then skip unconditionally
RETI
1
3
×,PC14,PC13,PC12 ← (SP+1)
PC11-0 ← (SP)(SP+3)(SP+2)
PSW ← (SP+4)(SP+5), SP ← SP + 6
rp
1
1
(SP-1)(SP-2) ← rp, SP ← SP - 2
BS
2
2
(SP-1) ← MBS, (SP-2) ← RBS, SP ←
SP - 2
rp
1
1
rp ← (SP+1)(SP), SP ← SP + 2
BS
2
2
MBS ← (SP+1), RBS ← (SP), SP ←
SP + 2
2
2
IME(IPS.3) ← 1
2
2
IE××× ← 1
2
2
IME(IPS.3) ← 0
IE×××
2
2
IE××× ← 0
A,PORTn
2
2
A ← PORTn (n=0 to 6)
XA,PORTn
2
2
XA ← PORTn+1,PORTn (n=4)
PORTn,A
2
2
PORTn ← A (n=2 to 6)
PORTn,XA
2
2
PORTn+1,PORTn ← XA (n=4)
EI
IE×××
INNote
OUTNote
36
4
ing area
!addr1
DI
Note
3
Skip
condition
Address-
CALLA
POP
I/O
Operation
of bytes cycle
(SP-5) ← 0,PC14,PC13, PC12
(SP-2) ← ×,×,MBE,RBE
PC14 ← 0, PC13-0 ← addr, SP ← SP - 6
PUSH
Interrupt
control
!addr
Number Machine
Unconditionally
MBE = 0, or MBE = 1 and MBS = 15 must be set when an IN/OUT instruction is executed.
µPD75218
Instruction Mnemonic
CPU
control
Special
Operand
Number Machine
of bytes cycle
Operation
HALT
2
2
Set HALT mode (PCC.2 ← 1)
STOP
2
2
Set STOP mode (PCC.3 ← 1)
NOP
1
1
No operation
RBn
2
2
RBS ← n (n=0-3)
MBn
2
2
MBS ← n (n=0,1,2,3,15)
taddr
1
3
• For a TBR instruction
PC13-0 ← (taddr)5-0 + (taddr+1)
PC14 ← 0
4
• For a TCALL instruction
(SP-6)(SP-3)(SP-4) ← PC11-0
(SP-5) ← 0, PC14, PC13, PC12
(SP-2) ← ×,×,MBE,RBE
PC13-0 ← (taddr)5-0 + (taddr+1)
SP ← SP-6 PC14 ← 0
3
• For an instruction other than TBR
and TCALL
SEL
GETINote
Executes the instruction in
(taddr)(taddr+1).
Note
Addressing area
Skip
condition
*10
Depends
upon the
referenced
instruction.
The TBR and TCALL instructions are table definition assembler pseudo instructions of the GETI
instructions.
37
µPD75218
10. MASK OPTION SELECTION
The µPD75218 has the following mask options enabling or disabling on-chip components.
Pin
P60 to P63
Mask option
Pull-up resistor incorporation enabled in bit units
T0/T9
T10/S15/PH3 to T13/S12/PH0
T14/S11, T15/S10
S0 to S9
XT1, XT2
The feedback resistor for the subsystem clock oscillator can be
removed
Cautions 1. In a system not using subsystem clocks, power consumption in the STOP mode can be decreased by
removing the feedback resistor from the oscillator.
2. The feedback resistor must be incorporated when the subsystem clock is used.
38
µPD75218
11. APPLICATION BLOCK DIAGRAM
11.1 VCR TIMER TUNER
Main power supply
+
Super capacitor
Power
failure
detection
Electronic
tuner
Tape count pulse
Tape up/down
SCK
System
controller
SO
microcomputer SI
LPF
VSS
T0–T9 10
VDD
INT4
PPO
µPD75218
 Timer

 Tuner

 Remote
 controller

INT1 

signal


 reception

 Tape counter 
Fluorescent indication panel (FIP)
16 segments × 10 digits
Key matrix
(16 × 4)
PORT6
SCK
SO
µ PD75104 or µPD75106
EEPROM™
µ PD6252
µ PD6253
µ PD6254
S0–S15 16
Remote-controller
signal
INT0
µ PC2800A
BUZ
X1
X2
XT1
XT2
BZ
Piezoelectric buzzer
39
µPD75218
11.2 COMPACT DISK PLAYER
SIO
Servo
control IC
T0–T13 14
SCK
SI/SO
S0–S11 12
Loading
circuit
Fluorescent indication panel (FIP)
12 segments × 14 digits
µPD75218
PORT6
Key matrix
(12 × 4)
BUZ
BZ
Remote-controller
signal
INT0
µ PC2800A
X1
40
X2
µPD75218
11.3 ECR
Main power supply
Power
failure
detection
+
VDD
VSS
INT4
T0–T15 16
S0–S9 10
Fluorescent indication panel (FIP)
10 segments × 16 digits
RAM
µPD75218
Key matrix
(10 × 4)
Printer
PPO
BZ
X1
X2
XT1
XT2
41
µPD75218
★
12. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C)
Parameter
Power supply voltage
Input voltage
Symbol
Conditions
Rating
Unit
VDD
–0.3 to +7.0
V
VLOAD
VDD – 40 to VDD + 0.3
V
VPRE
VDD – 11 to VDD + 0.3
V
VI
–0.3 to VDD + 0.3
V
–0.3 to VDD + 0.3
V
VDD – 40 to VDD + 0.3
V
VO
Pins except display output pins
VOD
Display output pins
Output voltage
Output high current
Output low current
Total lossNote 1
IOH
IOL
PT
Per pin except display output pins
–15
mA
Per pin for S0 to S9
–15
mA
Per pin for T0 to T15
–30
mA
Total of pins except display output pins
–20
mA
Total of display output pins
–120
mA
Per pin
17
mA
Total of pins
60
mA
Plastic QFP
450
mW
Plastic shrink DIP
600
mW
Operating temperature
Topt
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
OPERATING SUPPLY VOLTAGE (Ta = –40 to +85 °C)
Parameter
Min.
Max.
Unit
CPUNote 2
Note 3
6.0
V
Display controller
4.5
6.0
V
Timer/pulse generator
4.5
6.0
V
2.7
6.0
V
Other
42
Conditions
hardwareNote 2
µPD75218
Notes 1. Calculation of total loss
Design so that the sum of the following three power consumption values for the µPD75218CW/GF will be
less than the total loss PT (It is recommended to use the system with 80 % or less of the rating).
➀ CPU loss
: Given as VDD (Max.) × IDD1 (Max.)
➁ Output pin loss
: There are normal output pin loss and display output pin loss. It is necessary
to add a loss derived from the flow of maximum current to each output pin.
➂
Example
Pull-down register loss: Power loss due to a pull-down resistor incorporated in the display output
pin by mask option.
Suppose 4-LED output with 9 segments and 11 digits, VDD = 5 V + 10 % and 4.19 MHz oscillation and let
a maximum of 3 mA, 15 mA and, 10 mA flow to a segment pin, timing pin and LED output pin, respectively.
Further, let the voltage of fluorescent display tube (VLOAD voltage) be –30 V and normal voltage be small.
➀ CPU loss : 5.5 V × 9.0 mA = 49.5 mW
➁ Pin loss : Segment pin ..... 2 V × 3 mA × 9 = 54 mW
Timing pin ......... 2 V × 15 mA = 30 mW
LED output ........
➂
10
×2V
15
× 10 mA × 4 = 53 mW
2
Pull-down resistor loss ........ (30 + 5.5 V) × 10 = 504.1 mW
25 kΩ
PT = ➀ + ➁ + ➂ = 690.6 mW
In this example, the power consumption of 690.6 mW is higher than the allowable total loss for the shrink
DIP package (600 mW). It is necessary to decrease power consumption by decreasing the number of onchip pull-down resistors. In this example, power consumption can be adjusted to 577.8 mW by
incorporating pull-down resistors in only 11 digit outputs and 7 segment outputs and externally
mounting pull-down resistors to the 2 remaining segment outputs.
2. Except the system clock oscillator, display controller and timer/pulse generator.
3. The operating voltage range varies depending on the cycle time. Refer to the AC characteristics.
CAPACITANCE (Ta = 25 °C, VDD = 0 V)
Parameter
Input capacitance
Symbol
CIN
Except display output
Output capacitance
COUT
Display output
Input /output capacitance
Conditions
CIO
f = 1 MHz
0 V for pins other than pins
to be measured
Min.
Typ.
Max.
Unit
15
pF
15
pF
35
pF
15
pF
43
µPD75218
CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V)
Resonator
Recommended
constants
Ceramic
resonator
X1
X2
Note 3
C1
C2
Parameter
Oscillator
frequency
(fXX) Note 1
VDD = Oscillation
voltage range
Oscillation
settling time
After VDD reaches
Min. of the oscillation voltage range
Note 2
Crystal
resonator
X1
X2
C2
Oscillation
settling time
Min.
Typ.
2.0
2.0
Oscillator
frequency
(fXX) Note 1
Note 3
C1
Conditions
4.19
VDD = 4.5 to 6.0 V
Note 2
External
clock
X1
X2
µ PD74HCU04
Notes 1.
Max.
Unit
6.2
MHz
4
ms
6.2
MHz
10
ms
30
ms
X1 input
frequency
(fX) Note 1
2.0
6.2
MHz
X1 input
high/low
level width
(tXH, tXL)
100
250
ns
2.
The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item
of AC characteristics for the instruction execution time.
The oscillation settling time means the time required for the oscillation to settle after VDD reaches Min.
3.
of the oscillation voltage range or after the STOP mode is released.
See "Recommended Parameters for the Oscillation Circuit" for the resonators.
Caution When the main system clock oscillator is used, conform to the following guidelines when wiring at the
portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity.
• The wiring must be as short as possible.
• Other signal lines must not run in these areas. Any line carrying a high fluctuating current must be
kept away as far as possible.
• The grounding point of the capacitor of the oscillator must have the same potential as that of VDD. It
must not be grounded to ground patterns carrying a large current.
• No signal must be taken from the oscillator.
44
µPD75218
CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V)
Resonator
Recommended
constants
Crystal
resonator
XT1
XT2
Note 3
330 kΩ
C3
C4
Conditions
Parameter
Oscillator
frequency
(fXT) Note 1
Oscillation
settling time
Min.
Typ.
Max.
Unit
32
32.768
35
kHz
1.0
2
s
10
s
VDD = 4.5 to 6.0 V
Note 2
VDD
External
clock
XT1
XT2
Leave open
XT1 input
frequency
(fXT)
32
100
kHz
XT1 input
high/low
level width
(tXTH, tXTL)
10
32
µs
Notes 1.
The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item
of AC characteristics for the instruction execution time.
2.
The oscillation settling time means the time required for the oscillation to settle after VDD reaches Min.
of the oscillation voltage range.
Recommended resonators are listed on the next page.
3.
Caution When the subsystem clock oscillator is used, conform to the following guidelines when wiring at the
portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity.
• The wiring must be as short as possible.
• Other signal lines must not run in these areas. Any line carrying a high fluctuating current must be
kept away as far as possible.
• The grounding point of the capacitor of the oscillator must have the same potential as that of VDD.
It must not be grounded to ground patterns carrying a large current.
• No signal must be taken from the oscillator.
When the subsystem clock is used, pay special attention to its wiring; the subsystem clock oscillator
has low amplification to minimize current consumption and is more likely to malfunction due to noise
than the main system clock oscillator.
45
µPD75218
RECOMMENDED PARAMETERS FOR THE OSCILLATION CIRCUIT
When a ceramic resonator is used for the main system clock (Ta = -40 to +70 ˚C)
Manufacturer
Murata
Mfg.
Product name
CSA×××MG
External capacitance Oscillation voltage
Oscillation frequency (pF)
range (V)
(MHz)
Min.
C1
C2
Max.
2.00 to 2.44
CST×××MG
CSA×××MG093
2.45 to 3.50
CST×××MGW093
CSA×××MGU
2.51 to 6.00
CST×××MGWU
CSA×××MG
2.45 to 3.50
CST×××MGW
CSA×××MG
2.51 to 6.00
CST×××MGW
30
30
Built-in
Built-in
30
30
Built-in
Built-in
30
30
Built-in
Built-in
30
30
Built-in
Built-in
30
30
Built-in
Built-in
2.7
6.0
3.0
3.3
When a ceramic resonator is used for the main system clock (Ta = -20 to +80 ˚C)
Manufacturer
Kyocera
Product name
External capacitance Oscillation voltage
Oscillation frequency (pF)
range (V)
(MHz)
Min.
C1
C2
Max.
KBR-2.0MS
2.0
KBR-4.0MWS
4.0
33
33
KBR-4.19MWS
4.19
Built-in
Built-in
47
47
KBR-4.19MSA
33
33
KBR-4.19MKS
Built-in
Built-in
33
33
Built-in
Built-in
KBR-6.0MSA
33
33
KBR-6.0MKS
Built-in
Built-in
PBRC 6.00A
33
33
PBRC 4.19A
KBR-6.0MWS
6.0
2.7
6.0
When a crystal resonator is used for the main system clock (Ta = -20 to +70 ˚C)
Manufacturer
Kinseki
Product name
HC-49/U-S
External capacitance Oscillation voltage
Oscillation frequency (pF)
range (V)
(MHz)
Min.
C1
C2
Max.
3.072 to 6.000
18
18
2.7
6.0
When a crystal resonator is used for the subsystem clock (Ta = -15 to +60 ˚C)
Manufacturer
Kyocera
Product name
KF-38G
Oscillation
frequency (MHz)
32.768
External capacitance and
resistance
C1 (pF)
C2 (pF)
R (kΩ)
18
18
220
Oscillation voltage
range (V)
Min.
Max.
4.0
6.0
Caution When finely adjusting the oscillation frequency of a crystal resonator, adjust external capacitance C1 or
C3.
46
µPD75218
DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
Input high voltage
Input low voltage
Output high voltage
Symbol
Conditions
Min.
Max.
Unit
VIH1
Except below
0.7V DD
VDD
V
VIH2
Ports 0, 1, RESET
0.75VDD
VDD
V
VIH3
X1, X2, XT1
V DD–0.4
VDD
V
VIH4
Port 6
0.65VDD
VDD
V
0.7V DD
VDD
V
VDD = 4.5 to 6.0 V
VIL1
Except below
0
0.3VDD
V
VIL2
Ports 0, 1, 6, RESET
0
0.2VDD
V
VIL3
X1, X2, XT1
0
0.4
V
VOH
All output pins VDD = 4.5 to 6.0 V, IOH = –1 mA V DD–1.0
IOH = –100 µA
Output low voltage
Typ.
VOL
Input high leakage
current
ILIH1
Input low leakage
current
ILIL1
ILIH2
Ports 4, 5
V
V DD–0.5
VDD = 4.5 to 6.0 V, IOL = 15 mA
V
2.0
V
All output pins VDD = 4.5 to 6.0 V, IOL = 1.6 mA
0.4
V
IOL = 400 µA
0.5
V
3
µA
20
µA
–3
µA
–20
µA
0.5
Except X1,X2,XT1 VIN = VDD
X1, X2, XT1
Except X1,X2,XT1 VIN = 0 V
ILIL2
X1, X2, XT1
Output high leakage current
ILOH
All output pins VOUT = VDD
3
µA
Output low leakage
current
ILOL1
Except display output VOUT = 0 V
–3
µA
–10
µA
Display output current
ILOL2
IOD
Display output
S0 to S9
T0 to T15
Built-in pull-down
resistor (mask option)
RP6
RL
Supply
currentNote 2
IDD1
VDD = 4.5 to 6.0 V
Display output
VOD – VLOAD = 35 V
6.0 MHz crystal oscillation
C1 = C2 = 15pF
IDD4
IDD5
–3
–5.5
mA
–1.5
–3.5
mA
–15
–22
mA
–7
–15
mA
20
80
20
25
200
kΩ
1000
kΩ
70
135
kΩ
V DD = 5 V ±10
%Note 3
4.0
13.5
mA
VDD = 3 V ±10
%Note 4
0.55
1.8
mA
HALT mode VDD = 5 V ±10 %
600
1800
µA
VDD = 3 V ±10 %
200
600
µA
VDD = 5 V ±10
%Note 3
3.0
9.0
mA
V DD = 4 V ±10
%Note 4
0.45
1.5
mA
HALT mode VDD = 5 V ±10 %
550
1800
µA
VDD = 3 V ±10 %
180
600
µA
VDD = 3 V ±10 %
32 kHz crystal
oscillationNote 5 HALT mode VDD = 3 V ±10 %
40
120
µA
5
15
µA
VDD = 5 V ±10 %
0.5
20
µA
VDD = 3 V ±10 %
0.1
10
µA
4.19 MHz crystal oscillation
C1 = C2 = 15pF
IDD2
IDD3
VDD =
VPRE = VDD – 9 ±1
4.5 to 6.0 V
VPRE = 0 V
VOD =
VPRE = VDD – 9 ±1 VNote 1
VDD – 2 V
VPRE = 0 V
VNote 1
Port 6
VIN = VDD
IDD2
IDD1
VOUT = VLOAD = VDD – 35 V
XT1 = 0 V
STOP mode
47
µPD75218
Notes 1.
The following external circuit is recommended.
µ PD75218
+5 V
VDD
RD9. 1EL
RD9. 1EL : Zener diode (NEC)
Zener voltage = 8.29 to 9.30 V
VPRE
68 kΩ
VLOAD
–30 V
VSS
2. Current to the on-chip pull-down resistor (mask option) is not included.
3. When the processor clock control register (PCC) is set to 0011 and is operated in the high-speed mode.
4. When the PCC register is set to 0000 and is operated in the low-speed mode.
5. When the system clock control register (SCC) is set to 1001 and is operated with the subsystem clock
with main system clock oscillation stopped.
48
µPD75218
AC CHARACTERISTICS (Ta = –40 to +85 °C , VDD = 2.7 to 6.0 V)
Parameter
Symbol
CPU clock cycle time
(minimum instruction
execution time = 1
machine cycle)Note 1
tCY
TI0 input frequency
fTI
TI0 input high and lowlevel widths
SCK cycle time
SCK high and low-level
widths
Conditions
Min.
VDD = 4.5 to 6.0 V
Operation with main
system clock
tKCY
tKH,
tKL
Max.
Unit
0.67
32
µs
2.6
32
µs
125
µs
0
0.6
MHz
0
165
kHz
114
Operation with subsystem clock
tTIH,
tTIL
Typ.
VDD = 4.5 to 6.0 V
0.83
µs
3
µs
Input
0.8
µs
Output
0.95
µs
Input
3.2
µs
Output
3.8
µs
Input
0.4
µs
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
122
tKCY/2–50
1.6
ns
Input
Output
tKCY/2–150
ns
Output
µs
SI setup time (referred to
SCK↑)
tSIK
100
ns
SI hold time (referred to
SCK↑)
tKSI
400
ns
Delay from SCK↓ to SO
output
tKSO
Interrupt input high and
low-level widths
tINTH,
tINTL
RESET low-level width
Notes 1.
VDD = 4.5 to 6.0 V
ns
µs
INT1
2tCY
µs
INT2,
INT4
10
µs
10
µs
VS
VDD
(Operation with main system clock)
40
32
30
6
5
Guaranteed operation
range
4
Cycle time tCY [ µs]
2tCY or 128/fXX is set by interrupt mode register
(IM0) setting.
1000
Note 2
tCY
and the processor clock control register (PCC).
The cycle time tCY characteristics for power
supply voltage VDD when the main system
clock is in operation is shown on the right.
2.
ns
INT0
tRSL
CPU clock (Φ) cycle time is determined by the
oscillator frequency of the connected resonator, the system clock control register (SCC)
300
3
2
1
0.5
0
1
2
3
4
5
6
Power supply voltage VDD [V]
49
µPD75218
AC Timing Measurement Values (Except X1 and XT1 Inputs)
0.75VDD
0.75VDD
Test points
0.2VDD
0.2VDD
Clock Timing
1/fX
tXL
tXH
X1 input
VDD - 0.4 V
0.4 V
1/fXT
tXTL
tXTH
XT1 input
VDD - 0.4 V
0.4 V
TI0 Timing
1/fTI
tTIL
TI0
50
tTIH
µPD75218
Serial Transfer Timing
tKCY
tKH
tKL
SCK
tSIK
SI
tKSI
Input data
tKSO
SO
Output data
Interrupt Input Timing
tINTH
tINTL
INT0, INT1,
INT2 and INT4
RESET Input Timing
tRSL
RESET
51
µPD75218
DATA RETENTION CHARACTERISTICS FOR DATA MEMORY AT LOW SUPPLY VOLTAGE IN STOP MODE
(Ta = –40 to +85 °C)
Parameter
Symbol
Data retention supply voltage
VDDDR
Data retention supply currentNote 1
IDDDR
Release signal set time
tSREL
Oscillation settling timeNote 2
tWAIT
Notes 1.
2.
3.
Conditions
Min.
Typ.
Max.
Unit
6.0
V
10
µA
2.0
VDDDR = 2.0 V
0.1
µs
0
Release by RESET
217/fX
ms
Release by interrupt request
Note 3
ms
Current to the on-chip pull-down resistor (mask option) is not included.
Oscillation settling time is time to stop CPU operation to prevent unstable operation upon oscillation
start.
According to the setting of the basic interval timer mode register (BTM) (See below.)
BTM3
BTM2
BTM1
BTM0
Settling time (values at fXX = 6.0 MHz in parentheses)
—
0
0
0
220/fXX (approx. 175 ms)
—
0
1
1
217/fXX (approx. 21.8 ms)
—
1
0
1
215/fXX (approx. 5.46 ms)
—
1
1
1
213/fXX (approx. 1.37 ms)
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
Normal operation
mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
Normal operation
mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(Interrupt request)
tWAIT
52
µPD75218
★
13. CHARACTERISTIC CURVES (FOR REFERENCE)
IDD vs VDD (Main system clock: 6.0 MHz)
(Ta = 25 ˚C)
PCC = 0011
5000
PCC = 0010
PCC = 0000
Main system clock
HALT mode + 32 kHz
oscillation
1000
Supply current IDD ( µ A)
500
Subsystem clock
Normal operation
mode
100
50
Main system clock
STOP mode + 32 kHz
oscillation
Subsystem clock
HALT mode
10
X1
X2
Crystal
resonator
6.0 MHz
5
15 pF
15 pF
XT1
XT2
Crystal
resonator
32.768 kHz 330 kΩ
15 pF
15 pF
1
0
1
2
3
4
5
6
7
Supply voltage VDD (V)
53
µPD75218
IDD vs VDD (Main system clock: 4.19 MHz)
(Ta = 25 ˚C)
5000
PCC = 0011
PCC = 0010
PCC = 0000
Main system clock
HALT mode + 32 kHz
oscillation
1000
Supply current IDD (µ A)
500
Subsystem clock
Normal operation
mode
100
50
Main system clock
STOP mode + 32 kHz
oscillation
Subsystem clock
HALT mode
10
X1
X2
Crystal
resonator
4.19 MHz
5
15 pF
15 pF
XT1
XT2
Crystal
resonator
32.768 kHz 330 kΩ
15 pF
1
0
1
2
3
4
5
Supply voltage VDD (V)
54
6
7
15 pF
µPD75218
14. PACKAGE DIMENSIONS
64 PIN PLASTIC SHRINK DIP (750 mil)
64
33
1
32
A
K
H
G
J
I
L
F
D
N
M
NOTE
B
C
M
ITEM MILLIMETERS
R
INCHES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
A
58.68 MAX.
2.311 MAX.
B
1.78 MAX.
0.070 MAX.
2) Item "K" to center of leads when formed parallel.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020 +0.004
–0.005
F
0.9 MIN.
0.035 MIN.
G
3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.08 MAX.
0.200 MAX.
K
19.05 (T.P.)
0.750 (T.P.)
L
17.0
0.669
M
0.25 +0.10
–0.05
0.010 +0.004
–0.003
N
0.17
0.007
R
0~15°
0~15°
P64C-70-750A,C-1
55
µPD75218
64 PIN PLASTIC QFP (14×20)
A
B
detail of lead end
33
32
51
52
C
D
S
R
Q
64
1
20
19
F
G
H
I
M
J
K
M
P
N
L
NOTE
Each lead centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.
56
ITEM
MILLIMETERS
INCHES
A
23.6±0.4
0.929±0.016
B
20.0±0.2
0.795 +0.008
–0.009
C
14.0±0.2
0.551+0.009
–0.008
D
17.6±0.4
0.693±0.016
F
1.0
0.039
G
1.0
0.039
H
0.40±0.10
0.016 +0.004
–0.005
0.008
I
0.20
J
1.0 (T.P.)
0.039 (T.P)
K
1.8±0.2
0.071 +0.008
–0.009
L
0.8±0.2
0.031 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
P
Q
R
S
0.10
0.004
2.7
0.106
0.1±0.1
0.004±0.004
5°±5°
5°±5°
3.0 MAX.
0.119 MAX.
P64GF-100-3B8,3BE,3BR-2
µPD75218
15.
RECOMMENDED SOLDERING CONDITIONS
The following conditions (see table below) must be met when soldering this product.
For the details of the recommended soldering conditions refer to our document SMD Surface Mount Technology
Manual(IEI-1207).
Please consult with our sales offices in case other soldering process is used, or in case soldering is done under
different conditions.
Table 15-1
Soldering Conditions for Surface-Mount Devices
µPD75218GF-×××-3BE: 64-pin plastic QFP (14 × 20 mm)
Soldering process
Soldering conditions
Symbol
Wave soldering
Temperature in the soldering vessel: 260 ˚C or less
Soldering time: 10 seconds or less
Number of soldering processes: 1
Pre-heating temperature: 120 ˚C max.
(package surface temperature)
Exposure limitNote: 2 days
(20 hours of pre-baking is required at 125 ˚C afterward.)
WS60-202-1
Infrared ray reflow
Peak package’s surface temperature: 230 ˚C
Reflow time: 30 seconds or less (at 210 ˚C or more)
Number of reflow processes: 1
Exposure limitNote: 2 days
(20 hours of pre-baking is required at 125 ˚C afterward.)
IR30-202-1
VPS
Peak package’s surface temperature: 215 ˚C
Reflow time: 40 seconds or less (at 200 ˚C or more)
Number of reflow processes: 1
Exposure limitNote: 2 days
(20 hours of pre-baking is required at 125 ˚C afterward.)
VP15-202-1
Partial heating method
Terminal temperature: 300 ˚C or less
Flow time: 3 seconds or less (one side per device)
Note
–
Exposure limit before soldering after dry-pack package is opened.
Storage conditions: Temperature of 25 ˚C and maximum relative humidity at 65 % or less
Caution
Do not apply more than a single process at once, except for "Partial heating method."
Table 15-2 Soldering Conditions for Inserted Devices
µPD75218CW-×××: 64-pin plastic shrink DIP (750 mil)
Soldering conditions
Soldering process
Wave soldering (only for leads)
Temperature in the soldering vessel: 260 °C or less
Soldering time: 10 seconds or less
Partial heating method
Terminal temperature: 260 °C or less
Flow time: 10 seconds or less
Caution In wave soldering, apply solder only to the lead section. Care must be taken that jet solder does not
contact the main body of the package.
Notice
Other versions of the products are available. For these versions, the recommended reflow
soldering conditions have been mitigated as follows:
Higher peak temperature (235 °C), two-stage, and longer exposure limit.
Contact an NEC representative for details.
57
µPD75218
APPENDIX A FUNCTIONS OF µPD752×× SERIES PRODUCTS
ROM
16256 × 8
24448 × 8
32640 × 8
RAM
512 × 4
768 × 4
1024 × 4
I/O lines
including
FIP dualfunction
pins and
excluding
FIP dedicated pins
FIP controller/
driver
When main
system clock is
selected
0.95 µs/1.91 µs/15.3 µs (When the microcomputer operates at 4.19 MHz)
When sub-system
clock is selected
122 µs (When the microcomputer operates at 32.768 kHz)
Total number of
I/O lines
33
CMOS input
lines
8
CMOS I/O lines
20: 8 lines for driving LED
0.67 µs/1.33 µs/10.7 µs (When the microcomputer operates at 6.0 MHz)
0.95 µs/1.91 µs/15.3 µs (When the microcomputer operates at 4.19 MHz)
Port 6: Pull-down resistors contained (mask option)
CMOS output
lines
1: Timer/pulse generator output
P-ch open-drain
output with high
withstand voltage
and high current
4 lines for driving LED:
(mask option)
Output with high
withstand
voltage
26 lines: 40 V max.
Number of
segments
9 to 16
Number of digits
9 to 16
Pull-down resistors contained
Whether built-in pull-down resistors are used or the pins are
used as open-drain output is selected bit by bit (mask option).
Port 6: No pull-down
resistors contained
No pull-down
resistors contained
S0-S8,T0-T9:
Built-in pull-down
resistors used
S9,T10-T15:
Open-drain output
Timer


4 channels 


Serial interface
MSB or LSB first can be selected. Serial bus can be configured.
Vectored interrupt
External: 3, internal: 5
Test input
External: 1, internal: 1
•
•
•
•
System clock oscillator
2 built-in circuits
58
µPD75P218
µPD75217
Instruction
cycle
★
µPD75218
µPD75216A
Item
Power-on reset circuit
Incorporated
(mask option)
Data retention at low supply voltage
Possible (2 V)
Timer/event counter
Basic interval timer
: Watchdog timer operation is possible.
Timer/pulse generator : 14-bit PWM output is possible.
Watch timer
: Buzzer output is possible.





• When main system clock is selected:
6.0 MHz (the µPD75218 and µPD75P218 only)
4.19 MHz
• When subsystem clock is selected: 32.768 kHz
None
Operating temperature range
-40 to +85 °C
Operating supply voltage
2.7 to 6.0 V
Package
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14 × 20 mm)
64-pin ceramic WQFN (the µPD75P218 only)
-40 to +70 °C
µPD75218
APPENDIX B DEVELOPMENT TOOLS
Software
Hardware
The following development tools are provided for developing systems including the µPD75218:
IE-75000-RNote 1
IE-75001-R
In-circuit emulator for the 75X series
IE-75000-R-EMNote 2
Emulation board for the IE-75000-R and IE-75001-R
EP-75216ACW-R
Emulation probe for the µPD75218CW
EP-75216AGF-R
Emulation probe for the µPD75218GF. A 64-pin conversion socket, the EV-9200G-64, is attached
to the probe.
EV-9200G-64
PG-1500
PROM programmer
PA-75P216ACW
PROM programmer adapter for the µPD75P218CW. Connected to the PG-1500.
PA-75P218GF
PROM programmer adapter for the µPD75P218GF. Connected to the PG-1500.
PA-75P218KB
PROM programmer adapter for the µPD75P218KB. Connected to the PG-1500.
IE control program
Host machine
• PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00ANote 3)
• IBM PC/ATTM (PC DOS TM Ver. 3.1)
PG-1500 controller
RA75X relocatable
assembler
Notes 1. Maintenance service only
2. Not contained in the IE-75001-R
3. These software cannot use the task swap function, which is available in MS-DOS Ver. 5.00 and Ver. 5.00A.
Remark Refer to "75X Series Selection Guide" (IF-1027) for development tools manufactured by third parties.
59
µPD75218
APPENDIX C RELATED DOCUMENTS
Documents related to the device
Document name
Document No.
User’s manual
IEU-692
75X series selection guide
IF-1027
Documents related to development tools
Software
Hardware
Document name
Document No.
IE-75000-R/IE-75001-R User’s Manual
EEU-1416
IE-75000-R-EM User’s Manual
EEU-1294
EP-75216ACW-R User’s Manual
EEU-1321
EP-75216AGF-R User’s Manual
EEU-1309
PG-1500 User’s Manual
EEU-1335
RA75X Assembler Package User’s Manual
PG-1500 Controller User’s Manual
Operation
EEU-1346
Language
EEU-1363
EEU-1291
Other related documents
Document name
Document No.
Package Manual
IEI-1213
SMD Surface Mount Technology Manual
IEI-1207
Quality Grades on NEC Semiconductor Devices
IEI-1209
NEC Semiconductor Device Reliability/Quality Control System
IEI-1203
Electrostatic Discharge (ESD) Test
IEI-1201
Guide to Quality Assurance for Semiconductor Devices
MEI-1202
Caution The above documents may be revised without notice. Use the latest versions when you design an
application system.
60
µPD75218
Cautions on CMOS Devices
1
Countermeasures against static electricity for all MOSs
Caution
When handling MOS devices, take care so that they are not electrostatically charged.
Strong static electricity may cause dielectric breakdown in gates. When transporting or
storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal
cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during
assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins.
Also handle boards on which MOS devices are mounted in the same way.
2
CMOS-specific handling of unused input pins
Caution
Hold CMOS devices at a fixed input level.
Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an
intermediate-level input may be caused by noise. This allows current to flow in the CMOS
device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input
level. Since unused pins may function as output pins at unexpected times, each unused
pin should be separately connected to the VDD or GND pin through a resistor.
If handling of unused pins is documented, follow the instructions in the document.
3
Statuses of all MOS devices at initialization
Caution
The initial status of a MOS device is unpredictable when power is turned on.
Since characteristics of a MOS device are determined by the amount of ions implanted
in molecules, the initial status cannot be determined in the manufacture process. NEC
has no responsibility for the output statuses of pins, input and output settings, and the
contents of registers at power on. However, NEC assures operation after reset and items
for mode setting if they are defined.
When you turn on a device having a reset function, be sure to reset the device first.
61
µPD75218
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special
: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime systems, etc.
M4 92.6
EEPROM is a trademark of NEC Corporation.
FIP is a trademark of NEC Corporation.
MS-DOS is a trademark of Microsoft Corporation.
PC DOS and PC/AT are a trademarks of IBM Corporation.