DATA SHEET MOS INTEGRATED CIRCUIT µPD75P116 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The µPD75P116 is a version of the µPD75116 in which the on-chip mask ROM is replaced by one-time PROM which can be written to once only. Since the µPD75P116 is capable of program write by a user, it is suitable for evaluation in system development and limited production. Detailed functional descriptions are shown in the following User’s Manual. Be sure to read for design purposes. µPD751×× Series User’s Manual : IEM-922 FEATURES • • • • µPD75116 compatible Program memory (PROM) capacitance : 16256 × 8 bits Data memory (RAM) capacitance : 512 × 4 bits Single power supply 5 V ± 10% ORDERING INFORMATION Ordering Code µ PD75P116CW µ PD75P116GF-3BE Package Quality Grade 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (14 × 20 mm) Standard Standard ★ Please refer to “Quality Grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Note There are no on-chip pull-up resistor and power-on reset function by means of a mask option. The information in this document is subject to change without notice. Document No. IC-3358 (O. D. No. IC-7599A) Date Published February 1994 P Printed in Japan The mark ★ shows major revised points. © NEC Corporation 1994 µPD75P116 PIN CONFIGURATION (TOP VIEW) 64-pin plastic shrink DIP (750 mil) 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 µPD75P116CW P13/INT3 P12/INT2 P11/INT1 P10/INT0 PTH03 PTH02 PTH01 PTH00 TI0 TI1 P23 P22/PCL P21/PTO1 P20/PTO0 P03/SI P02/SO P01/SCK P00/INT4 P123 P122 P121 P120 P133 P132 P131 P130 P143 P142 P141 P140 V PP V DD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 V SS P90 P91 P92 P93 P80 P81 P82 P83 P70 P71 P72 P73 P60 P61 P62 P63 X1 X2 RESET P50 P51 P52 P53 P40 P41 P42 P43 P30/MD0 P31/MD1 P32/MD2 P33/MD3 µPD75P116 P42 P43 P30/MD0 P31/MD1 P32/MD2 P33/MD3 V DD V PP P140 P141 P142 P143 P130 64-pin plastic QFP (14 × 20 mm) 64 636261605958575655545352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P131 P132 P133 P120 P121 P122 P123 P00/INT4 P01/SCK P02/SO P03/SI P20/PTO0 P21/PTO1 P22/PCL P23 T11 T10 PTH00 PTH01 P81 P80 P93 P92 P91 P90 V SS P13/INT3 P12/INT2 P11/INT1 P10/INT0 PTH03 PTH02 µPD75P116GF-3BE P41 P40 P53 P52 P51 P50 RESET X2 X1 P63 P62 P61 P60 P73 P72 P71 P70 P83 P82 Pin Name P00 to P03 P10 to P13 P20 to P23 : Port 0 : Port 1 : Port 2 P30 P40 P50 P60 : : : : Port Port Port Port 3 4 5 6 : : : : Port Port Port Port 7 8 9 12 to to to to P33 P43 P53 P63 P70 to P73 P80 to P83 P90 to P93 P120 to P123 P130 to P133 : Port 13 P140 to P143 : Port 14 m SCK SO SI PTO0, PTO1 : : : : Serial Clock Serial Output Serial Input Programmable Timer Output PCL PTH00 to PTH03 INT0, INT1, INT4 INT2, INT3 : : : : Clock Output Programmable Threshold Input External Vectored Interrupt Input External Test Input TI0, TI1 X1, X2 RESET NC : : : : Timer Input Clock Oscillation Reset No Connection VDD VSS VPP MD0 to MD3 : : : : Positive Power Supply Ground Programming Power Supply Mode Selection 3 µPD75P116 OVERVIEW OF FUNCTIONS Description Item Basic instructions 43 Minimum instruction execution time 0.95 µs, 1.91 µs, 15.3 µs (4.19 MHz operation) 3-stage switching capability ROM 16256 × 8 RAM 512 × 4 Internal memory 4 General register 4 bits × 8 × 4 banks (memory mapping) Accumulator 3 types of accumulators corresponding to bit length of manipulated data • 1-bit accumulator (CY), 4-bit accumulator (A), 8-bit accumulator (XA) Input/output port Total 58 • CMOS input pins • CMOS input/output pins (LED direct drive capability) • Middle-high voltage N-ch open-drain input/output pins (LED direct drive capability) • Comparator input pins (4-bit precision) : 10 : 32 : 12 : 4 Timer/counter • 8-bit timer/event counter × 2 • 8-bit basic interval timer (watchdog timer applicable) Serial interface • 8 bits • LSB-first/MSB-first switchable • Two transfer modes (transmit-receive/receive-only mode) Vectored interrupt External : 3, internal : 4 Test input External : 2 Standby • STOP/HALT mode Instruction set • • • • Operating temperature range –40 to +85 °C Operating voltage 5 V ± 10 % Others • Bit manipulation memory (bit sequential buffer : 16 bits) on-chip Package • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP (14 × 20mm) Various bit manipulation instructions (set, reset, test, boolean operation) 8-bit data transfer, comparison, operation, increment/decrement instructions 1-byte relative branch instruction GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1 byte INTBT SP(8) PROGRAM COUNTER (14) ALU TIMER/EVENT COUNTER #0 TI0 PTO0/P20 PORT 0 4 P00-P03 PORT 1 4 P10-P13 PORT 2 4 P20-P23 PORT 3 4 P30-P33 /MD0-MD3 PORT 4 4 P40-P43 PORT 5 4 P50-P53 PORT 6 4 P60-P63 PORT 7 4 P70-P73 PORT 8 4 P80-P83 PORT 9 4 P90-P93 PORT 12 4 P120-P123 PORT 13 4 P130-P133 PORT 14 4 P140-P143 BLOCK DIAGRAM BIT SEQ. BUFFER (16) BASIC INTERVAL TIMER CY BANK INTT0 TIMER/EVENT COUNTER #1 TI1 PTO1/P21 INTT1 SI/P03 SERIAL INTERFACE SO/P02 SCK/P01 GENERAL REG. PROM PROGRAM MEMORY 16256 × 8 BITS DECODE AND CONTROL RAM DATA MEMORY 512 × 4 BITS INTSIO INT0/P10 INT1/P11 INT2/P12 INT3/P13 INT4/P00 PTH00-PTH03 INTERRUPT CONTROL fX / 2 4 PROGRAMMABLE THRESHOLD PORT #0 CLOCK OUTPUT CONTROL CLOCK GENERATOR X1 X2 STAND BY CONTROL CPU CLOCK Φ VPP VDD VSS RESET 5 µPD75P116 PCL/P22 CLOCK DIVIDER N µPD75P116 CONTENTS 1. PIN FUNCTIONS .................................................................................................................................... 7 1.1 1.2 1.3 1.4 PORT PINS ..................................................................................................................................................... OTHER PINS ................................................................................................................................................... PIN INPUT/OUTPUT CIRCUITS ................................................................................................................... RECOMMENDED CONNECTION OF µPD75P116 UNUSED PINS ........................................................... 7 8 9 10 1.5 NOTES ON USING P00/INT4 PIN AND RESET PIN .................................................................................. 10 2. DIFFERENCES BETWEEN µPD75P116 AND µPD75116 ...................................................................... 11 3. PROM (PROGRAM MEMORY) WRITE AND VERIFY .......................................................................... 12 3.1 3.2 3.3 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES ................................................................... PROGRAM MEMORY WRITE PROCEDURE ................................................................................................ PROGRAM MEMORY READ PROCEDURE ................................................................................................. 12 13 14 4. ELECTRICAL SPECIFICATIONS ............................................................................................................ 15 5. PACKAGE INFORMATION .................................................................................................................... 26 6. RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 28 APPENDIX A. DEVELOPMENT TOOLS ...................................................................................................... 29 APPENDIX B. RELATED DOCUMENTATION ............................................................................................ 30 6 µPD75P116 1. PIN FUNCTIONS 1.1 PORT PINS Pin Name Input/Output DualFunction Pin P00 Input INT4 P01 Input/output SCK P02 Input/output SO P03 Input SI Function 8-bit I/O After Reset I/O Circuit Type *1 B F 4-bit input port (PORT 0). Input E B × P10 INT0 P11 INT1 Input B Input E Programmable 4-bit input/output port (PORT 3). MD0 to MD3 Input/output can be specified bit-wise. *2 Input E INT2 P13 INT3 P20 PTO0 P21 PTO1 Input/output P22 PCL P23 — 4-bit input/output port (PORT 2). × *2 P30 to P33 Input/output P40 to P43 Input/output — 4-bit input/output port (PORT 4). Data input/output pin for program memory (PROM) write/verify (low-order 4 bits). *2 Input E P50 to P53 Input/output — 4-bit input/output port (PORT 5). Data input/output pin for program memory (PROM) write/verify (high-order 4 bits). *2 Input E P60 to P63 Input/output Programmable 4-bit input/output port (PORT 6). Input/output can be specified bit-wise. *2 Input E — P70 to P73 Input/output — 4-bit input/output port (PORT 7). *2 Input E P80 to P83 Input/output — 4-bit input/output port (PORT 8). *2 Input E — 4-bit input/output port (PORT 9). *2 Input E Input M-A Input M-A Input M-A P90 to P93 * 4-bit input port (PORT 1). Input P12 Input/output P120-P123 Input/output — N-ch open-drain 4-bit input/output port (PORT 12). +12 V withstand voltage. *2 P130-P133 Input/output — N-ch open-drain 4-bit input/output port (PORT 13). +12 V withstand voltage. *2 P140-P143 Input/output — N-ch open-drain 4-bit input/output port (PORT 14). +12 V withstand voltage. *2 1. 2. — indicates Schmitt-triggered input. LED direct drive capability 7 µPD75P116 1.2 OTHER PINS Pin Name Input/Output DualFunction Pin PTH00 to PTH03 Input — Variable threshold voltage 4-bit analog input port. N Input — External event pulse input to timer/event counter. Or edge detection vectored interrupt input pin, or 1-bit input is also possible. B TI0 TI1 Input/output I/O Circuit Type *1 Timer/event counter output pin. Input E P21 PTO1 SCK Input/output P01 Serial clock input/output pin. Input F SO Input/output P02 Serial data output pin. Input E SI Input P03 Serial data input pin. Input B INT4 Input P00 Edge detection vector interrupt input pin (detection of both rising and falling edges). B Edge detection vector interrupt input pin (detection edge selectable). B Edge detection testable input pin (rising edge detection) B P10 INT0 Input P11 INT1 P12 INT2 Input P13 INT3 PCL Input/output X1, X2 RESET Input MD0 to MD3 Input/output P22 Clock output pin — System clock oscillation crystal/ceramic connection pin. When an external clock is used, the clock is input to X1 and the inverted clock is input to X2. — System reset input pin (low-level active). P30 to P33 Mode selection pin for program memory (PROM) write/ verify. VDD — Positive power supply pin. Applies +6 V for write/verify. VSS — GND potential pin. — Program voltage impression pin for program memory (PROM) write/verify. Connected to VDD directly in normal operation. Applies +12.5 V for PROM write/verify. VPP *2 8 After Reset P20 PTO0 * Function 1. 2. indicates Schmitt-triggered input. The device will not operate correctly unless VPP is connected to VDD directly in normal use. Input E B Input E µPD75P116 1.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuits of each pin of the µPD75P116 are shown by in abbreviated form. Type F Type A VDD data IN/OUT P-ch Type D output disable IN N-ch Type B Input/output circuit made up to a Type D push-pull output and Type B Schmitt-triggered input. CMOS specification input buffer Type B Type M-A IN/OUT N-ch (+12 V Withstand Voltage) data output disable IN Middle-High Voltage Input Buffer (+12 V Withstand Voltage) Schmitt-triggered input with hysteresis characteristic Type D Type N VDD Comparator data P-ch IN OUT output disable + – N-ch VREF (Threshold Voltage) Push-pull output with high impedance output capability (P-ch and N-ch both OFF) Type E data IN/OUT Type D output disable Type A This is an input/output circuit made up of a Type D push-pull output and Type A input buffer. 9 µPD75P116 RECOMMENDED CONNECTION OF µPD75P116 UNUSED PINS 1.4 Recommended Connection Pin PTH00 to PTH03 TI0 Connect to VSS or VDD. TI1 P00 Connect to VSS. P01 to P03 Connect to VSS or VDD. P10 to P13 Connect to VSS. P20 to P23 P30 to P33 P40 to P43 P50 to P53 Input status : Connect to VSS or VDD. Output status : Leave open. P60 to P63 P70 to P73 P80 to P83 P90 to P93 P120 to P123 P130 to P133 P140 to P143 1.5 NOTES ON USING P00/INT4 PIN AND RESET PIN The P00/INT4 and RESET pins have a test mode setting function (for IC test) which tests internal operations of pin of the µPD75P116 in addition to those functions given in 1.1 and 1.2. The test mode is set when voltage greater than VDD is applied to either pin. Therefore, even during normal operation, the test mode is engaged when noise greater than VDD is added, thus causing interference with normal operation. For example, this problem may occur if the P00/INT4 and RESET pins wiring is too long, causing line noise. To avoid this, try to suppress line noise in wiring. If line noise is still high, try elimminating the noise using the exterior add-on components shown in the Figures below. ● Connect a Diode with Low VF (0.3 V max.) ● Connect a Capacitor Between the VDD and the Pin. Between the VDD and the Pin. VDD Diode with low VF 10 VDD VDD VDD P00/INT4, RESET P00/INT4, RESET µPD75P116 2. DIFFERENCES BETWEEN µPD75P116 AND µPD75116 The µPD75P116 is a product in which the program memory (mask ROM) of the µPD75116 is changed to a user programmable PROM. Other functions of the µPD75P116 and µPD75116 are virtually the same only with the differences shown in Table 2-1. For details of CPU functions and on-chip hardware, see the “µPD75116 User’s Manual” (IEM-922). Table 2-1 Differences between µPD75P116 and µPD75116 Item ★ µPD75P116 µPD75116 One-time PROM Mask ROM Program memory 0000H-3F7FH (16256 × 8 bits) 0000H-01FFH (512 × 4 bits) Data memory Pull-up resistor (ports 12 to 14) No Mask option 5 V ± 10 % 2.7 to 6.0 V VPP NC P33/MD3 to P30/MD0 P33 to P30 Power-on reset function Operating voltage range 31 pins (SDIP) Pin function 57 pins (QFP) 33 to 36 pins (SDIP) 59 to 62 pins (QFP) Electrical specification Other Note Different consumption current, operating temperature range, etc. Refer to the electrical specifications parameters for each data sheet for details. Different noise resistance, noise radiation, etc., due to difference in the size of circuits and mask layout. The PROM and ROM products differ in noise resistance and noise radiation. If you are considering replacement of the PROM products by the mask ROM product in the transition from preproduction to volume production, this should be thoroughly evaluated with the mask ROM CS product (not ES product). 11 µPD75P116 3. PROM (PROGRAM MEMORY) WRITE AND VERIFY The ROM built into the µPD75P116 is a 16256 × 8-bit PROM. The pins shown in the table below are used to write/verify this PROM. There is no address input; instead, a method to update the address by the clock input from the X1 pin is adopted. Function Pin Name VPP Voltage application pin for program memory write/verify (normally VDD potential). X1, X2 Address update clock inputs for program memory write/ verify. Inverse of X1 pin signal is input to X2 pin. MD0 to MD3 Operating mode selection pin for program memory write/ verify. P40 to P43 (low-order 4 bits) 8-bit data input/output pins for progrm memory write/ P50 to P53 (high-order 4 bits) verify. Supply voltage application pin. Applies 5 V ± 10 % in normal operation, and 6 V for program memory write/verify. VDD Note 3.1 Since the µPD75P116 is a one-time PROM version, UV-ray erasure is not possible. PROGRAM MEMORY WRITE/VERIFY OPERATING MODES The µPD75P116 assumes the program memory write/verify mode is +6 V and +12.5 V are applied respectively to the VDD and VPP pins. The table below shows the operating modes available by the MD0 to MD3 pin setting in this mode. The rest of pins are all set at the VSS potential by the pull-down resistor. Operating Mode Setting Operating Mode VPP +12.5 V VDD MD0 MD1 MD2 MD3 H L H L Program memory address zero-clear L H H H Write mode L L H H Verify mode H × H H Program inhibit mode +6 V × : L or H 12 µPD75P116 3.2 PROGRAM MEMORY WRITE PROCEDURE The program memory writing procedure is shown below. High-speed write is possible. (1) Pull down a pin which is not used to VSS via the resistor. A low-level signal is input to the X1 pin. (2) Supply +5 V to the VDD and VPP pins. (3) 10 µs wait. (4) (5) (6) (7) The program memory address 0 clear mode. Supply +6 V and +12.5 V respectively to VDD and VPP. The program inhibit mode. Write data in the 1-ms write mode. (8) (9) (10) (11) The program inhibit mode. The verify mode. If written, proceed to (10); if not written, repeat (7) to (9). (Number of times written in (7) to (9): X) × 1-ms additional write. The program inhibit mode. (12) (13) (14) (15) Update (+1) the program memory address by inputting 4 pulses to the X1 pin. Repeat (7) to (12) up to the last address. The program memory address 0 clear mode. Change the VDD and VPP pins voltage to +5 V. (16) Power off. The diagram below shows the procedure of the above (2) to (12). Repeated X Times Write Verify Additional Write Address Increment VPP VPP VDD VDD + 1 VDD VDD X1 P40-P43 P50-P53 Data Input Data Output Data Input MD0 MD1 MD2 MD3 13 µPD75P116 3.3 PROGRAM MEMORY READ PROCEDURE The µPD75P116 can read the content of the program memory in the following procedure. (1) Pull down a pin which is not used to VSS via the resistor. A low-level signal is input to the X1 pin. (2) (3) (4) (5) Supply +5 V to the VDD and VPP pins. 10 µs wait. The program memory address 0 clear mode. Supply +6 V and +12.5 V respectively to VDD and VPP. (6) The program inhibit mode. (7) The verify mode. If clock pulses are input to the X1 pin, data is output sequentially 1 address at a time at the period of inputting 4 pulses. (8) The program inhibit mode. (9) The program memory address 0 clear mode. (10) Change the VDD and VPP pins voltage to +5 V. (11) Power off. The diagram below shows the procedure of the above (2) to (9). VPP VPP VDD VDD + 1 VDD VDD X1 P40-P43 P50-P53 Data Output MD0 MD1 MD2 MD3 14 “L” Data Output µPD75P116 4. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C) PARAMETER SYMBOL TEST CONDITIONS UNIT Supply voltage VDD –0.3 to + 7.0 V Supply voltage VPP –0.3 to 13.5 V –0.3 to VDD + 0.3 V –0.3 to +13 V –0.3 to VDD + 0.3 V 1 pin –15 mA Total pins –30 mA Peak value 30 mA Effective value 15 mA Ports 0, 2 to 4, 12 to 14 total Peak value 100 mA Effective value 36 mA Ports 5 to 9 total Peak value 100 mA Effective value 36 mA Input voltage VI1 VI2 *1 Output voltage VO Output current high IOH Except ports 12 to 14 Ports 12 to 14 1 pin Output current low * RATING IOL*2 Operating temperature Topt –40 to +85 °C Storage temperature Tstg –65 to +125 °C 1. The power supply impedance (pull-up resistor) should be 50 kΩ or more when the voltage exceeding 2. 10 V applied to ports 12, 13 and 14. Effective value should be calculated as follows: [Effective value] = [Peak value] × √duty Note Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. 15 µPD75P116 OSCILLATION CIRCUIT CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 5 V ± 10 %) RESONATOR RECOMMENDED CIRCUIT X1 Ceramic resonator Oscillator frequency (fXX) *1 X2 C2 C1 X1 Crystal resonator X1 External clock * 1. 2. ★ 3. Oscillation stabilization time *2 TEST CONDITIONS C2 X2 µPD74HCU04 Oscillation stabilization time *2 MIN. TYP. 2.0 VDD = After V DD reaches 4.5 V. Oscillator frequency (fXX) *1 X2 C1 PARAMETER 2.0 After VDD reaches 4.5 V. 4.19 MAX. UNIT *3 5.0 MHz 4 ms *3 5.0 MHz 10 ms X1 input frequency (fX) *1 2.0 *3 5.0 MHz X1 input high/low level width (tXH , tXL ) 100 250 ns Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction execution time. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN. or STOP mode release. When the oscillator frequency is 4.19 MHz < fXX < – 5.0MHz, PCC = 0011 should not be selected as instruction execution time. If PCC = 0011 is selected, 1 machine cycle becomes less than 0.95 µs, with the result that the specified MIN value of 0.95 µs cannot be observed. ★ Note When the system clock oscillator is used, the following points should be noted concerning wiring in the section enclosed by dots, in order to prevent the effects of wiring capacitance, etc. • Keep the wiring as short as possible. • Do not cross any other signal lines. • Keep away from lines in which a high fluctuating current flows. • Ensure that oscillator capacitor connection points are always at the same potential as VSS . Do not ground in a ground pattern in which a high current flows. • Do not take a signal from the oscillator. 16 µPD75P116 DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 5 V ± 10 %) PARAMETER Input voltage high Input voltage low Output voltage high Output voltage low SYMBOL TEST CONDITIONS MIN. TYP. Other than below Ports 0 & 1, TI0 & 1, RESET Ports 12 to 14 0.7VDD 0.8V DD 0.7VDD VDD VDD 12 V V V VIH4 X1, X2 VDD–0.5 VDD V VIL1 Other than below 0 0.3VDD V VIL2 Ports 0 & 1, TI0 & 1, RESET 0 0.2VDD V VIL3 X1, X2 0 0.4 V VOH IOH = –1 mA VOL VDD–1.0 V IOL = 15 mA Ports 0, 2, to 9 0.55 2.0 V IOL = 10 mA Ports 12 to 14 0.35 2.0 V 0.4 V 3 µA X1, X2 20 µA Ports 12 to 14 20 µA Except X1 & X2 –3 µA X1, X2 –20 µA ILIH1 Other than below VIN = VDD ILIH2 ILIH3 VIN = 12 V Input leakage current low ILIL1 Output leakage current high ILOH1 VOUT = VDD Other than below 3 µA ILOH2 VOUT = 12 V Ports 12 to 14 20 µA ILOL VOUT = 0 V –3 µA 5 10 mA 500 1500 µA 0.5 20 µA Output leakage current low VIN = 0 V ILIL2 IDD1 Power supply current *1 IDD2 IDD3 * UNIT VIH1 VIH2 VIH3 IOL = 1.6 mA Input leakage current high MAX. 4.19 MHz Crystal oscillation C1 = C2 = 22 pF VDD = 5 V ± 5 % *2 HALT mode*3 STOP mode, VDD = 5 V ± 5 % VDD = 5 V ± 5 % 1. Not including current flowing in comparator. 2. 3. When processor clock control register (PCC) is set to 0011 operating in high-speed mode. When PCC is set to 0100 and CPU is halted in HALT mode. 17 µPD75P116 CAPACITANCE (Ta = 25 °C, VDD = 0 V) PARAMETER Input capacitance Output capacitance I/O capacitance SYMBOL TEST CONDITIONS MIN. TYP. CIN COUT f = 1 MHz Unmeasured pins returned to 0 V. CIO MAX. UNIT 15 pF 15 pF 15 pF MAX. UNIT ±100 mV COMPARATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 5 V ± 10 %) PARAMETER SYMBOL Comparison accuracy VACOMP MIN. TYP. Threshold voltage VTH 0 VDD V PTH input voltage VIPTH 0 VDD V Comparator circuit current consumption 18 TEST CONDITIONS PTHM7 set to "1" 1 mA µPD75P116 AC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) PARAMETER SYMBOL CPU clock cycle time* (minimum instruction execution time = 1 machine cycle) tCY TI input frequency fTI TI input high/low-level width TEST CONDITIONS VDD = 4.75 to 5.5 V tTIH, TYP. MAX. UNIT 0.95 32 µs 1.1 32 µs 0 1 MHz 0.48 µs Input 0.8 µs Output 0.95 µs tKH, Intput 0.4 µs tKL Output tKCY/2–50 ns tTIL tKCY SCK cycle time MIN. SCK high/low-level width SI setup time (to SCK↑) tSIK 100 ns SI hold time (from SCK↑) tKSI 400 ns SO output delay time from SCK↓ tKSO INT0 to INT4 high/lowlevel width tINTH, tINTL 5 µs tRSL 5 µs RESET low level width * 300 ns The cycle time of the CPU clock (Φ) is determined by the oscillator frequency of the connected resonator and the processor clock control register (PCC). The graph on the below shows the cycle time tCY characteristics against supply voltage VDD. Relation between Cycle Time and Supply Voltage tCY vs. VDD Operating Guaranteed Range Cycle Time tCY [µs] 5 10 5 1 0.5 0 1 2 3 4 5 Supply Voltage VDD [V] 6 Note tCY vs. VDD characteristics are different from those of the µPD75P108 19 µPD75P116 AC Timing Test Point (Excluding ports 0 & 1, TI0, TI1, X1, X2, RESET) 0.7 VDD 0.3 VDD 0.7 VDD 0.3 VDD Test Points Clock Timing 1/fX tXL tXH VDD - 0.5 0.4 X1 Input TI Input Timing 1/fTI tTIL TI0, TI1 20 tTIH 0.8 VDD 0.2 VDD µPD75P116 Serial Transfer Timing tKCY tKL tKH 0.8 VDD 0.2 VDD SCK tSIK tKSI 0.8 VDD Input Data SI 0.2 VDD tKSO SO Output Data Interrupt Input Timing tINTL tINTH 0.8 VDD INT0-INT4 0.2 VDD RESET Input Timing tRSL RESET 0.2 VDD 21 µPD75P116 DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to +85 °C) PARAMETER SYMBOL Data retention supply voltage VDDDR Data retention power supply current *1 IDDDR Release signal set time tSREL Oscillation stabilization wait time *2 tWAIT * 1. 2. 3. TEST CONDITIONS MIN. TYP. 2.0 VDDDR = 2.0 V 0.1 0 217/f x *3 Release by RESET Release by interrupt request MAX. UNIT 5.5 V 10 µA µs ms ms Does not include current flowing in the comparator. The oscillator stabilization wait time is the time during which CPU operation is halted to prevent unstable operation when oscillation begins. Depends on the setting of the basic interval timer mode register (BTM) (table below). BTM3 BTM2 BTM1 BTM0 WAIT Time (Figure in Parentheses is for fXX = 4.19 MHz) – 0 0 0 220/fXX (Approx. 250 ms) – 0 1 1 217/fXX (Approx. 31.3 ms) – 1 0 1 215/fXX (Approx. 7.82 ms) – 1 1 1 213/fXX (Approx. 1.95 ms) Data Retention Timing (STOP Mode Release by RESET) Internal RESET Operation HALT Mode Operating Mode STOP Mode Data Retention Mode VDD tSREL VDDDR STOP Instruction Execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT 22 µPD75P116 DC PROGRAMMING CHARACTERISTICS (Ta = 25 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V, VSS = 0 V) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VIH1 Except X1 & X2 0.7V DD VDD V VIH2 X1, X2 VDD–0.5 VDD V VIL1 Except X1 & X2 0 0.3 VDD V VIL2 X1, X2 0 0.4 V 10 µA Input voltage high Input voltage low Input leakage current ILI Output voltage high VOH IOH = –1 mA Output voltage low VOL IOL = 1.6 mA VDD supply current IDD VPP supply current IPP Note 1. 2. VIN = VIL or VIH V VDD–1.0 MD0 = VIL, MD1 = VIH 0.4 V 30 mA 30 mA Ensure that VPP does not reach +13.5 V or above including overshot. Ensure that VDD is applied before VPP and cut off after VPP. 23 µPD75P116 AC PROGRAMMING CHARACTERISTICS (Ta = 25 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V, VSS = 0 V) PARAMETER TYP. *1 Address setup time *2 (to MD0↓) tAS tAS 2 µs MD1 setup time (to MD0↓) tM1S tOES 2 µs Data setup time (to MD0↓) tDS tDS 2 µs Address hold time *2 (from MD0↑) tAH tAH 2 µs Data hold time (from MD0↑) tDH tDH 2 µs Data output float delay time from MD0↑ tDF tDF 0 VPP setup time (to MD3↑) tVPS tVPS 2 µs VDD setup time (to MD3↑) tVDS tVCS 2 µs Initial program pulse width tPW tPW 0.95 Additional program pulse width tOPW tOPW 0.95 MD0 setup time (to MD1↑) tMOS tCES 2 Data output delay time from MD0↓ tDV tDV MD1 hold time (from MD0↑) tM1H tOEH MD1 recovery time (from MD0↓) tM1R tOR Program counter reset time tPCR MIN. MD0 = MD1 = VIL MAX. 130 1.0 UNIT ns 1.05 ms 21.0 ms µs 1 µs 2 µs 2 µs — 10 µs tXH, tXL — 0.125 µs X1 input frequency fX — Initial mode setting time tI — 2 µs MD3 setup time (to MD1↑) tM3S — 2 µs MD3 hold time (from MD1↓) tM3H — 2 µs MD3 setup time (to MD0↓) tM3SR — In program memory read 2 µs Data output delay time from address *2 tDAD tACC In program memory read 2 µs Data output hold time from address *2 tHAD tOH In program memory read 0 MD3 hold time (from MD0↑) tM3HR — In program memory read 2 µs Data output float delay time from MD3↓ tDFR — In program memory read 2 µs X1 input high-/low-level width * 24 TEST CONDITIONS SYMBOL tM1H + tM1R > – 50 µs 4.19 130 MHz ns 1. Corresponding to µPD27C256 symbol. 2. Internal address signal is incremented by 1 on rise of 4th X1 input, and is not connected to a pin. µPD75P116 Program Memory Write Timing tVPS VPP VPP VDD tVDS VDD + 1 VDD VDD tXH X1 Data Output tXL P40-P43 P50-P53 Data Input Data Input tDS t1 tDV tOH tDS tDF Data Input tDH tAH tAS MD0 tM1R tPW tOPW tMOS MD1 tPCR tMIS tM1H MD2 tM3H tM3S MD3 Program Memory Read Timing tVPS VPP VPP VDD tVDS tXH VDD + 1 VDD VDD X1 tXL tDAD tHAD P40-P43 P50-P53 t1 Data Output Data Output tDFR tDV tM3HR MD0 MD1 “L” tPCR MD2 tM3SR MD3 25 µPD75P116 5. PACKAGE INFORMATION 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 32 A K H G J I L F D N M NOTE B C M ITEM MILLIMETERS R INCHES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. A 58.68 MAX. 2.311 MAX. B 1.78 MAX. 0.070 MAX. 2) Item "K" to center of leads when formed parallel. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K 19.05 (T.P.) 0.750 (T.P.) L 17.0 0.669 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15° 0~15° P64C-70-750A,C-1 26 µPD75P116 ★ 64 PIN PLASTIC QFP (14×20) A B 51 52 detail of lead end 33 32 C D S R Q 64 1 20 19 F G H I M J K M P N L NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 23.6±0.4 0.929±0.016 B 20.0±0.2 0.795 +0.008 –0.009 C 14.0±0.2 0.551+0.009 –0.008 D 17.6±0.4 0.693±0.016 F 1.0 0.039 G 1.0 0.039 H 0.40±0.10 0.016 +0.004 –0.005 0.008 I 0.20 J 1.0 (T.P.) 0.039 (T.P) K 1.8±0.2 0.071 +0.008 –0.009 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N P Q R S 0.10 0.004 2.7 0.106 0.1±0.1 0.004±0.004 5°±5° 5°±5° 3.0 MAX. 0.119 MAX. P64GF-100-3B8,3BE,3BR-2 27 µPD75P116 ★ 6. RECOMMENDED SOLDERING CONDITIONS The µPD75P116 should be mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document “Surface Mount Technology Manual” (IEI-1207). For soldering methods and conditions other than those recommended below, contact our salesman. Table 6-1 Surface Mount Type Soldering Conditions µPD75P116GF-3BE : 64-pin plastic QFP (14 × 20 mm) Soldering Method * Soldering Conditions Infrared reflow Package peak temperature: 230°C, Duration: 30 sec. max. (at 210°C or above), Number of times: Once Time limit: 2 days* (thereafter 16 hours prebaking required at 125°C) VPS Package peak temperature: 215°C, Duration: 40 sec. max. (at 200°C or above), Number of times: Once Time limit: 2 days* (thereafter 16 hours prebaking required at 125°C) Wave soldering Solder bath temperature: 260°C max., Duration: 10 sec. max Number of times: Once Preheating temperature: 120°C max. (package surface temperature), Time limit: 2 days* (thereafter 16 hours prebaking required at 125°C) Pin part heating Pin part temperature: 300°C max., Duration: 3 sec. max. (per device side) Recommended Condition Symbol IR30-162-1 VP15-162-1 WS60-162-1 — For the storage period after dry-pack decapsulation, storage conditions are max. 25°C, 65% 1H. Note Use of more than one soldering method should be avoided (except in the case of pin part heating). Table 6-2 Insertion Type Soldering Conditions µPD75P116CW : 64-pin plastic shrink DIP (750 mil) Soldering Method Soldering Conditions Wave Soldering (lead part only) Solder bath temperature: 260°C max., Duration: 10sec. max. Pin part heating Pin part temperature: 260°C max., Duration: 10sec. max. Note Ensure that the application of (wave soldering) is limited to the lead part and no solder touches the main unit directly. Notice A version of this product with improved recommended soldering conditions is available. For details (improvements such as infrared reflow peak temperature extension (230 °C), number of times: twice, relaxation of time limit, etc.), contact NEC sales personnel. 28 µPD75P116 APPENDIX A. DEVELOPMENT TOOLS Hardware The following development tools are available for system development using the µPD75P116. In-circuit emulator for 75X series IE-75000-R-EM *2 Emulation board for IE-75000-R and IE-75001-R EP-75108CW-R Emulation probe for µPD75P116CW EP-75108GF-R Emulation probe for µPD75P116GF A 64-pin conversion socket EV-9200G-64 is provided. EV-9200G-64 PG-1500 PROM programmar PA-75P108CW This is a PROM programmar adapter for µPD75P116CW and connects to PG-1500. PA-75P116GF This is a PROM programmar adapter for µPD75P116GF and connects to PG-1500. IE control program Software * IE-75000-R *1 IE-75001-R PG-1500 controller RA75X relocatable assembler Host machine • PC-9800 series (MS-DOS™ Ver.3.30 to Ver.5.00A *3) • IBM PC/AT™ series (PC DOS™ Ver.3.1) 1 Maintenance product 2 3 This is not incorporated in the IE-75001-R. A task swap function is provided with Ver.5.00/5.00A; however, a task swap function cannot be used with this software. Remarks For development tools manufactured by a third pary, see the “75X Series Selection Guide” (IF-151). 29 µPD75P116 APPENDIX B. RELATED DOCUMENTATION List of Device-Related Documents Document Name Document No. User's Manual Instruction Application Table (I) Introductory Volume Application Note (II) Remote-Controlled Reception Volume (III) Bar-Code Reader-Volume (IV) IC Control for MSK Transmission/Reception Volume 75X Series Selection Guide List of Development Tool Related Documents Document Name Document No. Hardware IE-75000-R/IE-75001-R User's Manual IE-75000-R-EM User's Manual EP-75108CW-R User's Manual EP-75108GF-R User's Manual PG-1500 User's Manual Software ★ Operation Volume RA75X Assembler Package User's Manual Language Volume PG-1500 Controller User's Manual Other Documents Document Name Document No. Package Manual Surface Mount Technology Manual Quality Grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability Quality Control Electrostatic Discharge (ESD) Test Semiconductor Device Quality Guarantee Guide Microcomputer Related Product Guide Other Manufacturer Volume Note 30 The above related documents may be changed without notice. Be sure to use the latest documents for design purposes. µPD75P116 [MEMO] 31 µPD75P108B [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation.