NEC UPD75P068CU

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P068
4 BIT SINGLE-CHIP MICROCOMPUTER
The µPD75P068 is produced by replacing the internal mask ROM of the µPD75068 with a one-time PROM
in which data can be written once.
The following user's manual describes the details of the functions of the µPD75P068. Be sure to read it
before designing an application system.
µPD75068 User's Manual: IEU-1366
FEATURES
• Compatible with the µPD75068
• Can be replaced with the µPD75068 containing mask ROM on a full-production basis.
•
•
•
•
•
Internal one-time PROM: 8064 words × 8 bits
Internal RAM: 512 words × 4 bits
Internal pull-up resistors can be specified with software: Ports 0 to 3 and 6
N-ch open-drain input-output: Ports 4 and 5
Can operate at low voltage: VDD = 2.7 to 6.0 V
ORDERING INFORMATION
Part number
Package
Quality grade
µPD75P068CU
42-pin plastic shrink DIP (600 mil)
Standard
µPD75P068GB-3B4
44-pin plastic QFP (Square 10 mm)
Standard
Caution The µPD75P068 is not provided with mask-selected pull-up resistors.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice.
Document No. IC-3290A
(O.D. No. IC-8623A
Date Published April 1994 P
Printed in Japan
Major changes in this revision are indicated by stars (★) in the margins.
1993
1990
© NEC CORPORATION
µPD75P068
PIN CONFIGURATION (TOP VIEW)
• 42-pin plastic shrink DIP
XT1
1
42
VSS
XT2
2
41
P40
RESET
3
40
P41
X1
4
39
P42
5
38
P43
6
37
P50
MD2/P32
7
36
P51
MD1/P31
8
35
P52
MD0/P30
9
34
P53
33
P00/INT4
32
P01/SCK
31
P02/SO/SB0
µ PD75P068CU
X2
MD3/P33
AVSS
10
AN7/KR3/P63
11
AN6/KR2/P62
12
AN5/KR1/P61
13
30
P03/SI/SB1
AN4/KR0/P60
14
29
P10/INT0
AN3/P113
15
28
P11/INT1
AN2/P112
16
27
P12/INT2
AN1/P111
17
26
P13/ TI0
AN0/P110
18
25
P20/PTO0
AVREF
19
24
P21
VPP
20
23
P22/PCL
VDD
21
22
P23/BUZ
NC
P111/AN1
P110/AN0
AVREF
VDD
VPP
P23/BUZ
P22/PCL
P21
INT2/P12
1
44 43 42 41 40 39 38 37 36 35 34
33
P112 /AN2
INT1/P11
2
32
P113/AN3
INT0/P10
3
31
P60/KR0/AN4
SB1/SI/P03
4
30
P61/KR1/AN5
SB0/SO/P02
5
29
P62/KR2/AN6
28
P63/KR3/AN7
µ PD75P068GB-3B4
25
P31/MD1
10
24
P32/MD2
P50
11
23
12 13 14 15 16 17 18 19 20 21 22
P33/MD3
X2
9
P51
X1
P52
XT2
P30/MD0
RESET
26
XT1
8
VSS
AVSS
P53
P40
27
P41
7
P42
6
P43
SCK /P01
INT4/P00
NC
2
P20/PTO0
P13/ TI0
• 44-pin plastic QFP
INTBT
TI0/P13
PTO0/P20
Port 0
4
P00-P03
Port 1
4
P10-P13
Serial
interface
Port 2
4
P20-P23
INTCSI
Port 3
4
P30/MD0-P33/MD3
Port 4
4
P40-P43
Port 5
4
P50-P53
Port 6
4
P60-P63
Port 11
4
P110-P113
Timer/
counter #0
Program
counter (13)
SP
Bank
SI/SB1/P03
SO/SB0/P02
SCK/P01
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0-KR3/P60-P63
CY
ALU
INTT0
General register
Interrupt
control
PROM program
memory
8064 × 8 bits
4
BUZ/P23
Decode and
control
Watch timer
RAM data
memory
512 × 4 bits
INTW
AVREF
AVSS
AN0-AN3/P110-P113
AN4-AN7/P60-P63
BLOCK DIAGRAM
Bit sequential
buffer
Basic interval
timer
A/D
converter
8
CPU clock
Φ
fX/2N
PCL/P22
Clock generator
Sub
XT1 XT2
Stand by control
Main
X1
X2
3
VPP
VDD
VSS RESET
µPD75P068
Clock output
Clock divider
control
µPD75P068
CONTENTS
1.
★
★
★
PIN FUNCTIONS ........................................................................................................................
5
1.1 PORT PINS ..........................................................................................................................................
5
1.2 NON-PORT PINS ................................................................................................................................
6
1.3 PIN INPUT/OUTPUT CIRCUITS ........................................................................................................
7
2.
DIFFERENCE BETWEEN THE µPD75P068 AND µPD75068 ...................................................
9
3.
WRITING TO AND VERIFYING PROM (PROGRAM MEMORY) ............................................
10
3.1 OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY .........
10
3.2 WRITING TO THE PROGRAM MEMORY .........................................................................................
11
3.3 READING THE PROGRAM MEMORY ..............................................................................................
12
4.
SCREENING ONE-TIME PROM PRODUCTS ...........................................................................
13
5.
ELECTRICAL CHARACTERISTICS .............................................................................................
14
6.
CHARACTERISTIC CURVES (FOR REFERENCE) .....................................................................
27
7.
PACKAGE DRAWINGS ..............................................................................................................
33
8.
RECOMMENDED SOLDERING CONDITIONS .......................................................................
35
APPENDIX A DEVELOPMENT TOOLS..........................................................................................
36
APPENDIX B RELATED DOCUMENTS ..........................................................................................
37
4
µPD75P068
1.
PIN FUNCTIONS
1.1
PORT PINS
Pin
Input/
output
Shared pin
P00
Input
INT4
P01
I/O
SCK
P02
I/O
SO/SB0
P03
I/O
SI/SB1
P11
Input
P12
INT1
INT2
P13
TI0
P20
PTO0
P21
I/O
P22
—
P23
BUZ
MD0
P31Note 2
P32Note 2
I/O
P33Note 2
P40-P43Note 2
P50-P53Note 2
MD1
MD2
I/O
4-bit input port (PORT1).
Pull-up resistors can be provided by
software in units of 4 bits.
4-bit I/O port (PORT2).
Pull-up resistors can be provided by
software in units of 4 bits.
Programmable 4-bit I/O port (PORT3).
I/O can be specified bit by bit.
Pull-up resistors can be provided by
software in units of 4 bits.
I/O
—
—
N-ch open-drain 4-bit I/O port (PORT5).
Withstand voltage of 10 V
Data input-output (high-order 4 bits)
when writing to and verifying program
memory (PROM)
KR0/AN4
I/O
KR1/AN5
B
×
Input
F -A
F -B
×
Input
B -C
×
Input
E-B
×
Input
E-B
High
Impedance
M-A
High
Impedance
M-A
KR3/AN7
AN0
Input
Programmable 4-bit I/O port (PORT6).
Pull-up resistors can be provided by
software in units of 4 bits.
×
Input
Y -D
×
Input
Y-A
●
KR2/AN6
P63
P113
I/O
circuit
typeNote 1
With noise elimination function
N-ch open-drain 4-bit I/O port (PORT4).
Withstand voltage of 10 V
Data input-output (low-order 4 bits) when
writing to and verifying program memory
(PROM)
P110
P112
When reset
MD3
P60
P111
8 bit
I/O
M -C
PCL
P30Note 2
P62
4-bit input port (PORT0).
For P01-P03, pull-up resistors can be
provided by software in units of 3 bits.
INT0
P10
P61
Function
4-bit input port (PORT11)
AN1
AN2
AN3
Notes 1. The circle (●
● ) indicates the Schmitt trigger input.
2. Can directly drive the LED.
5
µPD75P068
1.2
NON-PORT PINS
When reset
I/O
circuit
typeNote 1
Input for receiving external event pulse signal for
timer/event counter
Input
B -C
P20
Timer/event counter output
Input
E-B
P22
Clock output
Input
E-B
Input
E-B
Pin
Input/
output
Shared pin
TI0
Input
P13
PTO0
I/O
PCL
I/O
Function
BUZ
I/O
P23
Output for arbitrary frequency output (for buzzer
output or system clock trimming)
SCK
I/O
P01
Serial clock I/O
Input
F -A
Input
F -B
SO/SB0
I/O
P02
Serial data output
Serial bus I/O
SI/SB1
I/O
P03
Serial data input
Serial bus I/O
Input
M -C
INT4
Input
P00
Edge detection vectored interrupt input (either
rising edge or falling edge detection)
Input
B
Edge detection vectored interrupt input (detection
edge selectable)
Input
B -C
Edge detection testable input (rising edge
detection)
Input
B -C
Input
Y -D
INT0
Input
P10
P11
INT1
INT2
Input
P12
KR0-KR3
I/O
P60-P63/
AN4-AN7
AN0-AN3
Input
P110-P113
AN4-AN7
I/O
P60-P63/
KR0-KR3
AVREF
Input
AVSS
—
X1, X2
Input
Parallel falling edge detection testable input
Y-A
8-bit analog input
—
—
Reference voltage input
—
Z
—
GND potential
—
Z
—
Crystal/ceramic connection for main system clock
generation. When external clock signal is used, it
is applied to X1, and its reverse phase signal is
applied to X2.
—
—
—
—
—
B
Input
E-B
—
—
For A/D converter only
XT1, XT2
Input
—
Crystal connection for subsystem clock generation.
When external clock signal is used, it is applied to
XT1, and its reverse phase signal is applied to
XT2. XT1 can be used as a 1-bit input (test).
RESET
Input
—
System reset input
MD0-MD3
I/O
P30-P33
Mode selection when writing to or verifying
program memory (PROM)
VPPNote 2
—
—
Programming voltage application when writing to
or verifying program memory (PROM)
Directly connected to VDD during normal operation.
+12.5 V is applied when data is written in PROM or
when the PROM is verified.
VDD
—
—
Main power supply
—
—
VSS
—
—
GND potential
—
—
Notes 1. The circle (●
● ) indicates the Schmitt trigger input.
2. Unless the VPP pin is directly connected to the VDD pin during normal operation, the
µ PD75P068 does not operate normally.
6
Y -D
µPD75P068
1.3
PIN INPUT/OUTPUT CIRCUITS
The input/output circuit of each µ PD75P068 pin is shown below in a simplified manner.
(1/3)
Type A
(For type E-B)
Type D
(For type E-B,F-A)
VDD
VDD
Data
P-ch
P-ch
OUT
IN
Output
disable
N-ch
N-ch
Push-pull output which can be set to high-impedance output
(off for both P-ch and N-ch)
CMOS input buffer
Type B
Type E-B
V DD
P.U.R.
P.U.R.
enable
IN
P-ch
Data
Output
disable
Schmitt trigger input with hysteresis
Type D
IN/OUT
Type A
P.U.R.: Pull-up resistor
Type B-C
VDD
P.U.R.
P-ch
P.U.R.
enable
IN
P.U.R.: Pull-up resistor
7
µPD75P068
(2/3)
Type F-A
Type M-C
VDD
VDD
P.U.R.
P.U.R.
enable
P.U.R.
P.U.R.
enable
P-ch
Data
P-ch
IN/OUT
IN/OUT
Type D
Output
disable
Data
N-ch
Output
disable
Type B
P.U.R.: Pull-up resistor
P.U.R.: Pull-up resistor
Type F-B
Type Y
(For type Y-A , Y-D)
VDD
P.U.R
P.U.R.
enable
P-ch
VDD
IN
P-ch
N-ch
VDD
Output
disable
+
Sampling C
VDD
(P)
–
P-ch
AVSS
IN/OUT
AVSS
Data
Output
disable
Reference voltage
(from voltage tap of
serial resistor string)
N-ch
Input
enable
Output
disable
(N)
P.U.R.: Pull-up resistor
Type Y-A ★
Type M-A
IN instruction
IN/OUT
Data
Output
disable
N-ch
(Withstand
voltage: +10 V)
Type A
Input buffer
IN
Type Y
Input buffer with an intermediate withstand voltage of +10 V
P.U.R.: Pull-up resistor
8
µPD75P068
(3/3)
Type Y-D
Type Z
VDD
P.U.R.
AVREF
P.U.R.
enable
P-ch
Data
IN/OUT
Type D
Output
disable
Reference voltage
Type B
Type Y
AVSS
P.U.R.: Pull-up resistor
2.
DIFFERENCE BETWEEN THE µPD75P068 AND µPD75068
The µPD75P068 is produced by replacing the internal mask ROM (program memory) of the µPD75068 with
a one-time PROM in which data can be written once. Both have the same CPU function and internal hardware.
Table 2-1 shows the difference between the µPD75P068 and µPD75068.
For details of the CPU function and internal hardware, refer to the individual references for the µPD75068.
Table 2-1 Difference between the µPD75P068 and µPD75068
µPD75P068
(One-time PROM product)
Item
Program memory
Pull-up resistor
• 0000H to 1F7FH
• 8064 words × 8 bits
Ports 0 to 3 and 6
Can be specified with software.
Ports 4 and 5
None
Mask option
Contained
Mask option
XT1 feedback resistor
Operating supply voltage range
Pin function
µPD75P068
(Mask ROM product)
Pins 6 to 9 of SDIP
Pins 23 to 26 of
QFP
Pin 20 of SDIP
Pin 38 of QFP
2.7 to 6.0 V
P30/MD0 to P33/MD3
P30 to P33
VPP
IC
Electrical characteristics
They differ in consumption current. For details, refer to the corresponding
items in each data sheet.
Others
Since they differ in circuit scale and mask layout, they differ in noise immunity and noise radiation.
Caution The PROM and mask ROM products differ in noise immunity and noise radiation. Use not ES
products but CS products (mask ROM products) to evaluate them thoroughly when considering
the change from the PROM products to the mask ROM products during processes from
preproduction to volume production.
9
µPD75P068
3.
WRITING TO AND VERIFYING PROM (PROGRAM MEMORY)
The program memory in the µPD75P068 is a one-time PROM which consists of 8064 words × 8 bits. Writing
to and verifying the contents of the one-time PROM is accomplished using the pins shown in the table below.
Note that address inputs are not used; instead, the address is updated using the clock input from the X1 pin.
Pin name
Function
VPP
Voltage is applied to this pin when writing to the program
memory or verifying its contents (normally VDD electric potential).
X1, X2
Address update clock inputs used when writing to the program
memory or verifying its contents. The X2 pin is used to input the
inverted signal of the X1 pin input.
MD0 to MD3 (P30 to P33)
Operation mode selection pins used when writing to the program
memory or verifying its contents.
P40 to P43 (low-order four bits)
P50 to P53 (high-order four bits)
I/O pins for 8-bit data used when writing to the program memory
or verifying its contents.
VDD
Power voltage is applied to this pin. During normal operation,
2.7 to 6.0 V should be applied; 6 V should be applied when
writing to the program memory or verifying its contents.
Caution Since the µPD75P068CU/GB does not have an erasure window, the contents of the memory can
not be erased with ultraviolet radiation.
3.1
OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY
If +6 V is applied to the VDD pin and +12.5 V is applied to the VPP pin, the µPD75P068 enters program memory
write/verify mode. The specific operating mode is then selected by setting the MD0 through MD3 pins as listed
below. The remaining pins are all connected to VSS via pull-down resistors.
Operating mode specification
VPP
+12.5 V
VDD
+6 V
× indicates L or H.
10
Operating mode
MD0
MD1
MD2
MD3
H
L
H
L
Program memory address clear mode
L
H
H
H
Write mode
Verify mode
Program inhibit mode
L
L
H
H
H
×
H
H
µPD75P068
3.2
WRITING TO THE PROGRAM MEMORY
The procedure for writing to program memory is described below; high-speed write is possible.
(1)
Connect all unused pins to VSS through resistors. Apply a low-level signal to the X1 pin.
(2)
Apply 5 V to VDD and VPP pins.
(3)
Wait 10 µs.
(4)
Select program memory address clear mode.
(5)
Apply +6 V to VDD and +12.5 V to VPP.
(6)
Select program inhibit mode.
(7)
Select write mode for 1 ms duration and write data.
(8)
Select program inhibit mode.
(9)
Select verify mode. If write is successful, proceed to step (10). If write fails, repeat steps (7) to (9).
(10) Perform additional write for (Number (X) of repetitions of steps (7) to (9)) × 1 ms duration.
(11) Select program inhibit mode.
(12) Increment the program memory address by inputting four pulses on the X1 pin.
(13) Repeat steps (7) to (12) until the last address is reached.
(14) Select program memory address clear mode.
(15) Apply 5 V to VDD and VPP pins.
(16) Turn the power off.
The timing for steps (2) to (12) is shown below.
Repeat X times
Write
Verify
Additional write
Address
increment
VPP
VPP
VDD
VDD
VDD +1
VDD
X1
P40-P43
P50-P53
Data input
Data output
Data input
MD0
(P30)
MD1
(P31)
MD2
(P32)
MD3
(P33)
11
µPD75P068
3.3
READING THE PROGRAM MEMORY
The procedure for reading the contents of program memory is described below. The read is performed in
the verify mode.
(1)
Connect all unused pins to VSS through resistors. Apply a low-level signal to the X1 pin.
(2)
Apply 5 V to VDD and VPP pins.
(3)
Wait 10 µs.
(4)
Select program memory address clear mode.
(5)
Apply +6 V to VDD and +12.5 V to VPP.
(6)
Select program inhibit mode.
(7)
Select verify mode. Data is output sequentially one address at a time for each cycle of
four clock pulses appearing on the X1 pin.
(8)
Select program inhibit mode.
(9)
Select program memory address clear mode.
(10) Apply 5 V to VDD and VPP pins.
(11) Turn the power off.
The timing for steps (2) to (9) is shown below.
VPP
VPP
VDD
VDD +1
VDD
VDD
X1
P40-P43
P50-P53
Data output
MD0
(P30)
MD1
(P31)
MD2
(P32)
MD3
(P33)
12
“L”
Data output
µPD75P068
4.
SCREENING ONE-TIME PROM PRODUCTS
★
NEC cannot execute a complete test of one-time PROM products (µPD75P068CU and µPD75P068GB-3B4)
due to their structure before shipment. It is recommended that you screen (verify) PROM products after writing
necessary data into them and storing them at 125 °C for 24 hours.
NEC offers a charged service called QTOP microcomputer service. This service includes writing to onetime PROM, marking, screening, and verification.
Ask your sales representative for details.
13
µPD75P068
5. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C)
Parameter
Symbol
Conditions
Rated value
Unit
Supply voltage
VDD
–0.3 to +7.0
V
Supply voltage
VPP
–0.3 to +13.5
V
Input voltage
VI1
Ports other than ports 4 and 5
–0.3 to VDD + 0.3
V
VI2
Ports 4 and 5
–0.3 to +11
V
–0.3 to VDD + 0.3
V
1 pin
–10
mA
All pins
–30
mA
Peak value
30
mA
rms
15
mA
Peak value
20
mA
5
mA
Output voltage
VO
High-level output
current
IOH
Low-level output
IOLNote
N-ch open drain
1 pin of ports 0, 3, 4, and 5
current
1 pin of ports 2 and 6
rms
Total of all pins of ports 0, 3, 4,
and 5
Peak value
160
mA
rms
120
mA
Total of all pins of ports 2, and
6
Peak value
30
mA
rms
20
mA
Operating
temperature
Topt
–40 to +85
˚C
Storage temperature
Tstg
–65 to +150
˚C
Note Calculate rms with [rms] = [peak value] × √duty.
Caution Absolute maximum ratings are rated values beyond which some physical damages may be
caused to the product; if any of the parameters in the table above exceeds its rated value even
for a moment, the quality of the product may deteriorate. Be sure to use the product within the
rated values.
CAPACITANCE (Ta = 25 °C, VDD = 0 V)
Parameter
Symbol
Input capacitance
CI
Output capacitance
CO
I/O capacitance
CIO
14
Conditions
f = 1 MHz
0 V for pins other than pins to be
measured
Min.
Typ.
Max.
Unit
15
pF
15
pF
15
pF
µPD75P068
CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V)
Resonator
Recommended
constant
Ceramic
resonator
VSS
X1
X2
C2
C1
Parameter
Conditions
Min.
Typ.
1.0
Oscillator
frequency
(fX) Note 1
Oscillation
settling time
Max.
Unit
5.0Note 3
MHz
4
ms
5.0Note 3
MHz
10
ms
30
ms
Note 2
Crystal
VSS
X1
X2
C2
C1
1.0
Oscillator
frequency
(fX) Note 1
Oscillation
settling time
VDD = 4.5 to 6.0 V
Note 2
External
clock
X1
X2
µ PD74HCU04
4.19
X1 input
frequency
(fX) Note 1
1.0
5.0Note 3
MHz
X1 input
high/low
level width
(tXH, tXL)
100
500
ns
Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics. See the
item of AC characteristics for the instruction execution time.
2. The oscillation settling time means the time required for the oscillation to settle after VDD is reaches
the minimum voltage in the oscillation voltage range.
3. When 4.19 MHz < fX ≤ 5.0 MHz, do not select PCC = 0011 as the instruction execution time. When
PCC = 0011, one machine cycle falls short of 0.95 µs, the minimum value for the standard.
Caution When the main system clock oscillator is used, conform to the following guidelines when wiring
at the portions surrounded by dotted lines in the figures above to eliminate the influence of the
wiring capacity.
• The wiring must be as short as possible.
• Other signal lines must not run in these areas.
• Any line carrying a high fluctuating current must be kept away as far as possible.
• The grounding point of the capacitor of the oscillator must have the same potential as that
of VDD. It must not be grounded to ground patterns carrying a large current.
• No signal must be taken from the oscillator.
15
µPD75P068
CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V)
Resonator
Recommended
constant
Crystal
VSS XT1
XT2
R
C4
C3
Parameter
Conditions
Oscillator
frequency
(fXT) Note 1
Oscillation
settling time
Min.
Typ.
Max.
Unit
32
32.768
35
kHz
1.0
2
s
10
s
VDD = 4.5 to 6.0 V
Note 2
External
clock
XT1
XT2
XT1 input
frequency
(fXT) Note 1
32
100
kHz
XT1 input
high/low
level width
(tXTH, tXTL )
5
15
µs
Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics. See the
item of AC characteristics for the instruction execution time.
2. The oscillation settling time means the time required for the oscillation to settle after VDD reaches
the minimum voltage in the oscillation voltage range.
Caution When the subsystem clock oscillator is used, conform to the following guidelines when wiring
at the portions surrounded by dotted lines in the figures above to eliminate the influence of the
wiring capacity.
• The wiring must be as short as possible.
• Other signal lines must not run in these areas.
• Any line carrying a high fluctuating current must be kept away as far as possible.
• The grounding point of the capacitor of the oscillator must have the same potential as that
of VSS. It must not be grounded to ground patterns carrying a large current.
• No signal must be taken from the oscillator.
When the subsystem clock is used, pay special attention to its wiring; the subsystem clock
oscillator has low amplification to minimize current consumption and is more likely to malfunction due to noise than the main system clock oscillator.
16
µPD75P068
★
RECOMMENDED CAPACITORS IN THE OSCILLATION CIRCUIT
Main system clock: Ceramic resonator (Ta = –20 to +80°C)
Manufacturer
Part number
Recommended constant
Frequency
(MHz)
KBR-1000F/Y
KBR-2.0MS
C1 (pF)
C2 (pF)
1.00
150
150
2.00
47
47
33
33
Contained
Contained
Oscillation voltage range
Min. (V)
Max. (V)
2.7
6.0
2.7
6.0
PBRC 2.00A
3.00
KBR-3.0MS
KBR-3.58MSA
PBRC 3.58A
3.58
KBR-3.58MKS
Kyocera
KBR-3.58MWS
KBR-4.00MSA
33
PBRC 4.00A
33
4.00
KBR-4.00MKS
Contained
KBR-4.00MWS
Contained
KBR-5.0MSA
33
PBRC 5.00A
5.00
KBR-5.0MKS
Contained
KBR-5.0MWS
CRHF2.50
Toko
33
Contained
2.50
30
CRHF4.19
4.19
CRHT4.19
CRHF5.00
30
Contained
5.00
30
Contained
30
Main system clock: Crystal (Ta = –40 to +85°C)
Manufacturer
Part number
Recommended constant
Frequency
(MHz)
Oscillation voltage range
C1 (pF)
C2 (pF)
Min. (V)
Max. (V)
22
22
3.5
6.0
2.00
Kinseki
HC-49/U
4.19
6.00
Subsystem clock: Crystal (Ta = –15 to +60°C)
Manufacturer
Kyocera
Part number
KF-38G
Frequency
(kHz)
32.768
Recommended constant
Oscillation voltage range
C3 (pF)
C4 (pF)
R (kΩ)
Min. (V)
Max. (V)
15
27
220
2.7
6.0
17
µPD75P068
DC CHARACTERISTICS (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
Symbol
Min.
Conditions
Typ.
Max.
Unit
VIH1
Ports 2, 3, and 11
0.7V DD
VDD
V
VIH2
Ports 0, 1, and 6, and RESET
0.8V DD
VDD
V
VIH3
Ports 4 and 5
0.7V DD
10
V
VIH4
X1, X2, XT1, and XT2
VDD – 0.5
VDD
V
VIL1
Ports 2 to 5 and 11
0
0.3V DD
V
VIL2
Ports 0, 1, and 6, and RESET
0
0.2V DD
V
VIL3
X1, X2, XT1, and XT2
0
0.4
V
High-level
output voltage
VOH
VDD = 4.5 to 6.0 V, IOH = –1 mA
VDD – 1.0
V
IOH = –100 µA
VDD – 0.5
V
Low-level output
voltage
VOL
High-level
input voltage
Low-level input
voltage
High-level input
leakage current
ILIH1
Ports 4 and 5
VDD = 4.5 to 6.0 V, IOL = 15 mA
0.7
2.0
V
Port 3
VDD = 4.5 to 6.0 V, IOL = 15 mA
0.8
2.0
V
VDD = 4.5 to 6.0 V, IOL = 1.6 mA
0.4
V
IOL = 400 µA
0.5
V
SB0 and SB1
Pull-up resistor: 1 kΩ or more
0.2V DD
V
VI = VDD
Other than X1, X2, XT1, and XT2
3
µA
X1, X2, XT1, and XT2
20
µA
ILIH2
ILIH3
VI = 10 V
Ports 4 and 5
20
µA
Low-level input
leakage current
ILIL1
VI = 0 V
Other than X1, X2, XT1, and XT2
–3
µA
X1, X2, XT1, and XT2
–20
µA
High-level output
leakage current
ILOH1
VO = VDD
3
µA
ILOH2
VO = 10 V
20
µA
Low-level out-put
leakage current
ILOL
VO = 0 V
–3
µA
Built-in pull-up
resistor
RU
P01, P02, P03,
and ports 1 to 3,
and 6 VI = 0 V
80
kΩ
300
kΩ
Power supply
currentNote 1
ILIL2
Ports 4 and 5
VDD = 5.0 V ±10 %
15
VDD = 3.0 V ±10 %
30
VDD = 5.0 V ±10 %Note 3
4.19 MHzNote 2
crystal resonance VDD = 3.0 V ±10 %Note 4
C1 = C2 = 22 pF
HALT mode VDD = 5.0 V ±10 %
3.3
10
mA
0.45
1.4
mA
600
1800
µA
VDD = 3.0 V ±10 %
220
700
µA
35
120
µA
IDD4
32.768 kHzNote 5 VDD = 3.0 V ±10 %
crystal resonance
HALT mode VDD = 3.0 V ±10 %
5
15
µA
IDD5
XT1 = 0 V
VDD = 5.0 V ±10 %
0.5
20
µA
VDD =
0.1
10
µA
0.1
5
µA
IDD1
IDD2
IDD3
3.0 V ±10 %
Notes 1.
40
Ta = 25 ˚C
This current excludes the current which flows through the built-in pull-up resistors.
2.
This value applies also when the subsystem clock oscillates.
3.
Value when the processor clock control register (PCC) is set to 0011 and the µPD75036 is operated
in the high-speed mode
4.
Value when the PCC is set to 0000 and the µPD75036 is operated in the low-speed mode
5.
This value applies when the system clock control register (SCC) is set to 1001 to stop the main
system clock pulse and to start the subsystem clock pulse.
18
µPD75P068
AC CHARACTERISTICS (Ta = -40 to +85 °C, VDD = 2.0 to 6.0 V)
Parameter
Symbol
CPU clock cycle time
(minimum instruction
execution time = 1
machine cycle)Note 1
tCY
TI0 input frequency
fTI
Operated by main
system clock
pulse
VDD = 4.5 to 6.0 V
Typ.
Max.
Unit
64
µs
64
µs
125
µs
0
1
MHz
0
275
kHz
0.95
3.8
122
114
Operated by subsystem clock pulse
VDD = 4.5 to 6.0 V
0.48
µs
1.8
µs
Note 2
µs
INT1, INT2, and INT4
10
µs
KR0 to KR3
10
µs
10
µs
TI0 input high/low
level width
tTIH,
tTIL
VDD = 4.5 to 6.0 V
Interrupt input high/
low level width
tINTH,
tINTL
INT0
RESET low level width
Min.
Conditions
tRSL
tCY vs VDD
Notes 1. The cycle time of the CPU clock (Φ)
(Main system clock in operation)
depends on the connected resonator
70
frequency, the system clock control
64
60
register (SCC), and the processor clock
control register (PCC).
6
cycle time tCY characteristics for the
5
supply voltage VDD during main sys-
4
tem clock operation.
2. This value becomes 2tCY or 128/fX
according to the setting of the interrupt mode register (IM0).
Cycle time tCY [ µs]
The figure on the right side shows the
Operation guaranteed
range
3
2
1
0.5
0
1
2
3
4
5
6
Power supply voltage VDD [V]
19
µPD75P068
SERIAL TRANSFER OPERATION
Two-wire and three-wire serial I/O modes (SCK ... Internal clock output):
Parameter
SCK cycle time
Symbol
tKCY1
Conditions
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
Min.
Typ.
Max.
Unit
1600
ns
3800
ns
tKCY1/2 – 50
ns
SCK high/low level
width
tKL1
tKH1
tKCY1/2 – 150
ns
SI setup time
(referred to SCK↑)
tSIK1
150
ns
SI hold time
(referred to SCK↑)
tKSI1
400
ns
Delay time from
SCK↓ to SO output
tKSO1
RL = 1 kΩ,
CL = 100 pFNote
VDD = 4.5 to 6.0 V
0
250
ns
0
1000
ns
Max.
Unit
Two-wire and three-wire serial I/O modes (SCK ... External clock input):
Parameter
SCK cycle time
Symbol
tKCY2
Conditions
VDD = 4.5 to 6.0 V
Min.
Typ.
800
ns
3200
ns
400
ns
SCK high/low level
width
tKL2
tKH2
1600
ns
SI setup time
(referred to SCK↑)
tSIK2
100
ns
SI hold time
(referred to SCK↑)
tKSI2
400
ns
Delay time from
SCK↓ to SO output
tKSO2
VDD = 4.5 to 6.0 V
RL = 1 kΩ,
CL = 100 pFNote
VDD = 4.5 to 6.0 V
0
300
ns
0
1000
ns
Note RL and CL are the resistance and capacitance of the SO output line load respectively.
20
µPD75P068
SBI mode (SCK ... Internal clock output (master)):
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
1600
ns
3800
ns
tKCY3/2 - 50
ns
tKH3
tKCY3/2 - 150
ns
SB0/SB1 setup time
(referred to SCK↑)
tSIK3
150
ns
SB0/SB1 hold time
(referred to SCK↑)
tKSI3
tKCY3/2
ns
Delay time from SCK↓
to SB0/SB1 output
tKSO3
From SCK↑ to SB0/SB1↓
tKSB
tKCY3
ns
From SB0/SB1↓ to SCK
tSBK
tKCY3
ns
SB0/SB1 low level width
tSBL
tKCY3
ns
SB0/SB1 high level
width
tSBH
tKCY3
ns
SCK cycle time
SCK high/low level
width
tKCY3
tKL3
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
RL = 1 kΩ,
CL = 100 pFNote
VDD = 4.5 to 6.0 V
0
250
ns
0
1000
ns
SBI mode (SCK ... External clock input (slave)):
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
800
ns
3200
ns
400
ns
tKH4
1600
ns
SB0/SB1 setup time
(referred to SCK↑)
tSIK4
100
ns
SB0/SB1 hold time
(referred to SCK↑)
tKSI4
tKCY4/2
ns
Delay time from SCK↓
to SB0/SB1 output
tKSO4
From SCK↑ to SB0/SB1↓
tKSB
tKCY4
ns
From SB0/SB1↓ to
SCK↓
tSBK
tKCY4
ns
SB0/SB1 low level width
tSBL
tKCY4
ns
SB0/SB1 high level
width
tSBH
tKCY4
ns
SCK cycle time
SCK high/low level
width
tKCY4
tKL4
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
RL = 1 kΩ,
CL = 100 pFNote
VDD = 4.5 to 6.0 V
0
300
ns
0
1000
ns
Note RL and CL are the resistance and capacitance of the SB0/SB1 output line load respectively.
21
µPD75P068
A/D CONVERTER (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V)
Parameter
Conditions
Min.
Typ.
Max.
Unit
8
8
8
bit
2.5 V ≤ AVREF ≤ VDDNote 2 -10 ≤ Ta ≤ +85˚C
±1.5
LSB
-40 ≤ Ta < -10˚C
±2.0
LSB
Symbol
Resolution
Absolute accuracyNote 1
Conversion timeNote 3
tCONV
168/f X
µs
Sampling timeNote 4
tSAMP
44/fX
µs
Reference input voltage
AVREF
2.5
VDD
V
Analog input voltage
VIAN
AVSS
AVREF
V
Analog input impedance
RAN
1000
AVREF current
AIREF
0.7
MΩ
2.0
mA
Notes 1. Absolute accuracy excluding quantization error (±1/2 LSB)
2. 2.5 V ≤ AVREF ≤ VDD
ADM1 is set to 0 or 1 depending on the A/D converter reference voltage (AVREF) as follows:
2.5 V
0.6VDD
0.65VDD
VDD (2.7 to 6.0 V)
AVREF
ADM1 = 0
ADM1 = 1
When 0.6VDD ≤ AVREF ≤ 0.65V DD, ADM1 can be set to either 0 or 1.
3. Time from the execution of a conversion start instruction till the end of conversion (EOC = 1)
(40.1 µs: fX = 4.19 MHz)
4. Time from the execution of a conversion start instruction till the end of sampling (10.5 µs: fX
= 4.19 MHz)
22
µPD75P068
AC Timing Measurement Points (Excluding X1 and XT1 Inputs)
0.8VDD
0.8VDD
Measurement
points
0.2VDD
0.2VDD
Clock Timing
1/fX
tXL
tXH
VDD – 0.5 V
X1 input
0.4 V
1/fXT
tXTL
tXTH
VDD – 0.5 V
XT1 input
0.4 V
TI0 Timing
1/fTI
tTIL
tTIH
TI0
23
µPD75P068
Serial Transfer Timing
Three-wire serial I/O mode:
tKCY1
tKL1
tKH1
SCK
tSIK1
tKSI1
Input data
SI
tKSO1
Output data
SO
Two-wire serial I/O mode:
tKCY2
tKL2
tKH2
SCK
tSIK2
SB0 and SB1
tKSO2
24
tKSI2
µPD75P068
Serial Transfer Timing
Bus release signal transfer:
tKCY3
tKCY4
tKL3
tKL4
tKH3
tKH4
SCK
tKSB
tSBL
tSBH
tSIK3
tSIK4
tSBK
tKSI3
tKSI4
SB0 and SB1
tKSO3
tKSO4
Command signal transfer:
tKCY3
tKCY4
tKL3
tKL4
tKH3
tKH4
SCK
tKSB
tSIK3
tSIK4
tSBK
tKSI3
tKSI4
SB0 and SB1
tKSO3
tKSO4
Interrupt Input Timing
tINTL
tINTH
INT0, INT1, INT2
and INT4
KR0-KR3
RESET Input Timing
tRSL
RESET
25
µPD75P068
DATA HOLD CHARACTERISTICS BY LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE
(Ta = -40 to +85 °C)
Parameter
Symbol
Data hold supply voltage
VDDDR
currentNote 1
IDDDR
Release signal setting time
tSREL
Oscillation settling timeNote 2
tWAIT
Data hold supply
Notes 1.
2.
3.
Conditions
Min.
Typ.
Max.
Unit
6.0
V
10
µA
2.0
VDDDR = 2.0 V
0.1
µs
0
Release by RESET
2 /fX
ms
Release by interrupt request
Note 3
ms
17
Excluding the current which flows through the built-in pull-up resistors
CPU operation stop time for preventing unstable operation at the beginning of oscillation
This value depends on the settings of the basic interval timer mode register (BTM) shown below.
Wait time
(Values at fX = 4.19 MHz in parentheses)
BTM3
BTM2
BTM1
BTM0
—
0
0
0
220/fX (approx. 250 ms)
—
0
1
1
217/fX (approx. 31.3 ms)
—
1
0
1
215/fX (approx. 7.82 ms)
—
1
1
1
213/fX (approx. 1.95 ms)
Data Hold Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
Operation
mode
STOP mode
Data hold mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Hold Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
Operation
mode
STOP mode
Data hold mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(Interrupt request)
tWAIT
26
µPD75P068
★
6. CHARACTERISTIC CURVES (FOR REFERENCE)
IDD vs VDD (When the main system clock operates at 4.19 MHz with a crystal)
(Ta = 25 ˚C)
X1
5.0
X2
XT1
XT2
Crystal
Crystal
4.19 MHz
32.768 kHz
330 kΩ
18 pF
18 pF
PCC = 0011
3.0
PCC = 0010
22 pF
22 pF
PCC = 0000
1.0
Main system clock
HALT mode +
32 kHz oscillation
Supply current IDD (m A)
0.5
Subsystem clock
operating mode
0.1
0.05
Main system clock
STOP mode + 32 kHz
oscillation, and
subsystem clock
HALT mode
0.01
0.005
0.001
0
2
4
6
8
Supply voltage VDD (V)
27
µPD75P068
IDD vs V DD (When the main system clock operates at 2.0 MHz with a crystal)
(Ta = 25 ˚C)
X1
5.0
X2
XT1
XT2
Crystal
Crystal
2.0 MHz
32.768 kHz
330 kW
18 pF
18 pF
3.0
22 pF
22 pF
PCC = 0011
PCC = 0010
1.0
PCC = 0000
Main system clock
HALT mode +
32 kHz oscillation
Supply current IDD (m A)
0.5
Subsystem clock
operating mode
0.1
0.05
Main system clock
STOP mode + 32 kHz
oscillation, and
subsystem clock
HALT mode
0.01
0.005
0.001
0
2
4
Supply voltage VDD (V)
28
6
8
µPD75P068
IDD vs V DD (When the main system clock operates at 4.19 MHz with a ceramic resonator)
(Ta = 25 ˚C)
X1
5.0
X2
XT1
Crystal
Ceramic
resonator
4.19 MHz
3.0
XT2
32.768 kHz
PCC = 0011
330 kW
PCC = 0010
30 pF
30 pF
18 pF
18 pF
PCC = 0000
Main system clock
HALT mode +
32 kHz oscillation
1.0
Supply current IDD (m A)
0.5
Subsystem clock
operating mode
0.1
0.05
Main system clock
STOP mode + 32 kHz
oscillation, and
subsystem clock
HALT mode
0.01
0.005
0.001
0
2
4
6
8
Supply voltage VDD (V)
29
µPD75P068
IDD vs VDD (When the main system clock operates at 2.0 MHz with a ceramic resonator)
(Ta = 25 ˚C)
X1
5.0
X2
XT1
Crystal
Ceramic
resonator
2.0 MHz
3.0
XT2
32.768 kHz
330 kW
18 pF
18 pF
PCC = 0011
30 pF
30 pF
PCC = 0010
1.0
PCC = 0000
Main system clock
HALT mode +
32 kHz oscillation
Supply current IDD (m A)
0.5
Subsystem clock
operating mode
0.1
0.05
Main system clock
STOP mode + 32 kHz
oscillation, and
subsystem clock
HALT mode
0.01
0.005
0.001
0
2
4
Supply voltage VDD (V)
30
6
8
µPD75P068
IDD vs fx
IDD vs fx
(VDD = 5 V, Ta = 25 ˚C)
3.0
X1
PCC = 0011
X2
(VDD = 3 V, Ta = 25 ˚C)
1.0
X1
X2
2.5
2.0
PCC = 0010
IDD (mA)
IDD (mA)
PCC = 0010
1.5
0.5
PCC = 0011
PCC = 0000
1.0
PCC = 0000
Main system clock
HALT mode
Main system clock
HALT mode
0.5
0
0
1
2
3
fX (MHz)
4
5
0
0
6
1
2
IOL vs VOL (Port 0)
4
5
6
IOL vs VOL (Ports 2 and 6)
(Ta = 25 ˚C)
40
3
fX (MHz)
(Ta = 25 ˚C)
30
25
VDD = 6 V
30
VDD = 5 V
VDD = 6 V VDD = 5 V
VDD = 4 V
IOL (mA)
IOL (mA)
20
20
VDD = 4 V
VDD = 3 V
15
VDD = 2.7 V
VDD = 3 V
10
VDD = 2.7 V
10
5
0
0
1
2
3
VOL (V)
4
5
0
0
1
2
3
4
5
VOL (V)
31
µPD75P068
IOL vs VOL (Port 3)
IOL vs VOL (Ports 4 and 5)
(Ta = 25 ˚C)
40
(Ta = 25 ˚C)
40
VDD = 5 V
VDD = 4 V
30
20
IOL (mA)
IOL (mA)
30
VDD = 6 V
VDD = 3 V
VDD = 6 V
VDD = 5 V
VDD = 4 V
VDD = 3 V
20
VDD = 2.7 V
VDD = 2.7 V
10
0
0
10
1
2
3
4
5
VOL (V)
(Ta = 25 ˚C)
15
VDD = 5 V
VDD = 4 V
IOH (mA)
10
VDD = 3 V
VDD = 2.7 V
5
0
0
32
1
1
2
3
VOL (V)
IOH vs VOH
VDD = 6 V
0
0
2
3
VDD – VOH (V)
4
5
4
5
µPD75P068
7.
PACKAGE DRAWINGS
42PIN PLASTIC SHRINK DIP (600 mil)
42
22
1
21
A
K
H
G
J
I
L
F
B
D
N
R
M
C
M
NOTES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS
INCHES
A
39.13 MAX.
1.541 MAX.
B
1.78 MAX.
0.070 MAX.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020 +0.004
–0.005
F
0.9 MIN.
0.035 MIN.
G
3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.08 MAX.
0.200 MAX.
K
L
15.24 (T.P.)
13.2
0.600 (T.P.)
0.520
M
0.25 +0.10
–0.05
N
0.17
0.007
R
0~15°
0~15°
0.010 +0.004
–0.003
P42C-70-600A-1
33
µPD75P068
44 PIN PLASTIC QFP (
10)
A
B
12
11
D
F
Q
5°±5°
44
1
detail of lead end
S
23
22
C
33
34
G
H
I M
J
M
P
K
N
L
P44GB-80-3B4-2
NOTE
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
34
ITEM
MILLIMETERS
INCHES
A
13.6 ± 0.4
0.535+0.017
–0.016
B
10.0 ± 0.2
0.394+0.008
–0.009
C
10.0 ± 0.2
0.394+0.008
–0.009
D
13.6 ± 0.4
0.535+0.017
–0.016
F
1.0
0.039
G
1.0
0.039
H
0.35 ± 0.10
0.014+0.004
–0.005
I
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8 ± 0.2
0.071+0.008
–0.009
L
0.8 ± 0.2
0.031+0.009
–0.008
M
0.15+0.10
–0.05
0.006+0.004
–0.003
N
0.12
0.005
P
2.7
0.106
Q
0.1 ± 0.1
0.004 ± 0.004
S
3.0 MAX.
0.119 MAX.
µPD75P068
8. RECOMMENDED SOLDERING CONDITIONS
★
The conditions listed below shall be met when soldering the µ PD75P068.
For details of the recommended soldering conditions, refer to our document "SMD Surface Mount
Technology Manual" (IEI-1207).
Please consult with our sales offices in case any other soldering process is used, or in case soldering is
done under different conditions.
Table 8-1 Soldering Conditions for Surface-Mount Devices
µPD75P068GB-3B4: 44-pin plastic QFP (10 × 10 mm)
Soldering process
Soldering conditions
Symbol
Infrared ray reflow
Peak package’s surface temperature: 235 ˚C
Reflow time: 30 seconds or less (at 210 ˚C or more)
Maximum allowable number of reflow processes: 2
<Cautions>
(1) Do not start reflow-soldering the device if its temperature is
higher than the room temperature because of a previous
reflow soldering.
(2) Do not use water for flux cleaning before a second reflow soldering.
IR35-00-2
VPS
Peak package’s surface temperature: 215 ˚C
Reflow time: 40 seconds or less (at 200 ˚C or more)
Maximum allowable number of reflow processes: 2
<Cautions>
(1) Do not start reflow-soldering the device if its temperature is
higher than the room temperature because of a previous
reflow soldering.
(2) Do not use water for flux cleaning before a second reflow soldering.
VP15-00-2
Wave soldering
Solder temperature: 260°C or less
Flow time: 10 seconds or less
Number of flow processes: 1
Preheating temperature: 120 max. (measured on the package surface)
WS60-00-1
Partial heating method
Terminal temperature: 300 ˚C or less
Flow time: 3 seconds or less (for each side of device)
–
Caution Do not apply more than a single process at once, except for “Partial heating method.”
Table 8-2
Soldering Conditions for Through Hole Mount Devices
µPD75P068CU: 42-pin plastic shrink DIP (600 mil)
Soldering process
Soldering conditions
Wave soldering
(only for leads)
Solder temperature: 260 °C or less
Flow time: 10 seconds or less
Partial heating method
Terminal temperature: 260 °C or less
Flow time: 10 seconds or less
Caution In wave soldering, apply solder only to the lead section. Care must be taken that jet solder does
not come in contact with the main body of the package.
Notice
Other versions of the products are available. For these versions, the recommended reflow
soldering conditions have been mitigated as follows:
Higher peak temperature (235 °C), two-stage, and longer exposure limit.
Contact an NEC representative for details.
35
µPD75P068
APPENDIX A
DEVELOPMENT TOOLS
Hardware
The following development tools are provided for developing systems including the µPD75P068:
IE-75000-RNote 1
IE-75001-R
In-circuit emulator for the 75X series
IE-75000-R-EMNote 2
Emulation board for the IE-75000-R and IE-75001-R
EP-75068CU-R
Emulation probe for the µPD75P068CU
EP-75068GB-R
Software
EV-9200G-44
Emulation probe for the µPD75P068GB. A 44-pin conversion socket, the EV-9200G-64, is
attached to the probe.
PG-1500
PROM programmer
PA-75P008CU
PROM programmer adapter for the µPD75P068CU/GB. Connected to the PG-1500.
IE control program
Host machine
• PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00ANote 3)
• PC/ATTM series (PC DOSTM Ver. 3.10)
PG-1500 controller
RA75X relocatable
assembler
Notes 1. Maintenance service only
2. Not contained in the IE-75001-R
3. MS-DOS versions 5.00 and 5.00A are provided with a task swap function. This function, however,
cannot be used in these software.
Remark Refer to 75X Series Selection Guide (IF-1027) for development tools manufactured by third parties.
36
µPD75P068
APPENDIX B RELATED DOCUMENTS
Documents related to the device
Document No.
Document Name
User’s Manual
IEU-1366
Application Note (Preliminary)
IEA-1296
75X Series Selection Guide
IF-1027
Documents related to development tools
Document No.
Software
Hardware
Document Name
IE-75000-R/IE-75001-R User’s Manual
EEU-1455
IE-75000-R-EM User’s Manual
EEU-1294
EP-75068CU-R User’s Manual
EEU-1317
EP-75068GB-R User’s Manual
EEU-1428
PG-1500 User’s Manual
EEU-1335
RA75X Assembler Package User’s Manual
PG-1500 Controller User’s Manual
Operation
EEU-1346
Language
EEU-1363
EEU-1291
Other documents
Document Name
Document No.
Package Manual
IEI-1213
SMD Surface Mount Technology Manual
IEI-1207
Quality Grades on NEC Semiconductor Devices
IEI-1209
NEC Semiconductor Device Reliability/Quality Control System
IEI-1203
Electrostatic Discharge (ESD) Test
IEI-1201
Guide to Quality Assurance for Semiconductor Devices
MEI-1202
Caution The above documents may be revised without notice. Use the latest versions when you design
an application system.
37
µPD75P068
[MEMO]
38
µPD75P068
Cautions on CMOS Devices
1
Countermeasures against static electricity for all MOSs
Caution
When handling MOS devices, take care so that they are not electrostatically charged.
Strong static electricity may cause dielectric breakdown in gates. When transporting or
storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal
cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during
assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins.
Also handle boards on which MOS devices are mounted in the same way.
2
CMOS-specific handling of unused input pins
Caution
Hold CMOS devices at a fixed input level.
Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an
intermediate-level input may be caused by noise. This allows current to flow in the CMOS
device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input
level. Since unused pins may function as output pins at unexpected times, each unused
pin should be separately connected to the VDD or GND pin through a resistor.
If handling of unused pins is documented, follow the instructions in the document.
3
Statuses of all MOS devices at initialization
Caution
The initial status of a MOS device is unpredictable when power is turned on.
Since characteristics of a MOS device are determined by the amount of ions implanted
in molecules, the initial status cannot be determined in the manufacture process. NEC
has no responsibility for the output statuses of pins, input and output settings, and the
contents of registers at power on. However, NEC assures operation after reset and items
for mode setting if they are defined.
When you turn on a device having a reset function, be sure to reset the device first.
39
µPD75P068
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use of
such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use “Standard” quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime
systems, etc.
M4 92. 6
MS-DOS is a trademark of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.