DATA SHEET MOS INTEGRATED CIRCUIT µPD75P336 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The µPD75P336 is a version of the µPD75336 in which the on-chip mask ROM is replaced by one-time PROM. As the µPD75P336 is user-programmable, it is suitable for preproduction in system development, and for short-run and multiple device-production. Detailed function description, etc. are described in the following User's manual. Be sure to read it when designing. µPD75336 User's Manual: IEU-725 FEATURES • µPD75336 compatible • Memory capacity: • PROM : 16256 × 8 bits • RAM : 768 × 4 bits • Operable over same supply voltage range as mask ROM µPD75336 • VDD = 2.7 to 6.0 V • On-chip 8-bits resolution A/D converter (successive approximation type) • On-chip LCD controller/driver ORDERING INFORMATION Ordering Code µ PD75P336GC-3B9 µ PD75P336GK-BE9 Note Package 80-pin plastic QFP ( 14mm) 80-pin plastic TQFP (fine pitch)( 12mm) Quality Grade Standard Standard ★ Pull-up resistor cannot be incorporated by mask option. Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. The information in this document is subject to change without notice. Document No. IC-2980A (O. D. No. IC-8371A) Date Published October 1993P Printed in Japan The mark ★ shows major revised points. © NEC Corporation 1993 2 8 AVREF AVSS A/D CONVERTER BASIC INTERVAL TIMER INTBT TI0/P13 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 TI1/P80 PTO1/P21 TIMER/EVENT COUNTER #1 PROGRAM COUNTER (15) SP(8) CY WATCH TIMER INTW SI/SB1/P03 SO/SB0/P02 SCK/P01 fLCD 4 P00-P03 PORT 1 4 P10-P13 PORT 2 4 P20-P23 PORT 3 4 P30-P33 /MD0-MD3 PORT 4 4 P40-P43 PORT 5 4 P50-P53 PORT 6 4 P60-P63 PORT 7 4 P70-P73 PORT 8 4 P80-P83 12 S12-S23 ALU BANK INTT1 BUZ/P23 PORT0 BLOCK DIAGRAM AN0-AN7* GENERAL REG. PROGRAM MEMORY (ROM) 16256 × 8 BITS DECODE AND CONTROL CLOCKED SERIAL INTERFACE DATA MEMORY (RAM) 768 × 4 BITS INTCSI INT0/P10 INT1/P11 INTERRUPT CONTROL INT2/P12 8 LCD CONTROLLER /DRIVER N SYSTEM CLOCK CLOCK CLOCK GENERATOR STAND BY OUTPUT DIVIDER SUB MAIN CONTROL CONTROL CPU CLOCK fLCD BIT SEQ. BUFFER (16) PCL/P22 XT1 XT2 X1 X2 * AN6/P82, AN7/P83 VPP VDD VSS RESET S24/BP0 –S31/BP7 4 COM0–COM3 3 VLC0–VLC2 BIAS LCDCL/P30 SYNC/P31 µPD75P336 INT4/P00 KR0/P60 –KR3/P63 KR4/P70 –KR7/P73 fX / 2 8 µPD75P336 PIN CONFIGURATION (Top View) S26/BP2 6 7 8 9 * AVREF AVSS AN5 AN4 AN3 VDD XT1 X1 VPP* XT2 RESET X2 P53 P00/INT4 P51 P52 P50 19 20 2122232425 262728 2930 31323334353637383940 COM0 S12 P41 P42 P43 VSS S17 S16 S15 S14 S13 10 11 12 13 14 15 16 17 18 P40 S18 4 5 COM3 BIAS VLC0 VLC1 VLC2 S22 S21 S20 S19 2 3 COM1 COM2 S23 8079787776 757473 7271 70696867666564636261 µ PD75P336GC-3B9 µPD75P336GK-BE9 S25/BP1 S24/BP0 ★ AN2 AN1 AN0 P83/AN7 60 59 58 57 56 55 54 53 52 P33/MD3 P32/MD2 51 50 49 48 47 46 45 44 43 P31/SYNC/MD1 P30/LCDCL/MD0 P23/BUZ P22/PCL P21/PTO1 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 42 41 P10/INT0 P82/AN6 P81 P80/TI1 P03/SI/SB1 P01/SCK P02/SO/SB0 1 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 P73/KR7 S31/BP7 S30/BP6 S29/BP5 S28/BP4 S27/BP3 P72/KR6 P71/KR5 ● 80-pin plastic QFP (■ ■ 14mm) ● 80-pin plastic TQFP (fine pitch) (■ ■ 12mm) In normal operation, VPP should be connected to VDD directly. 3 µPD75P336 PIN NAME P00 to 03 P10 to 13 P20 to 23 P30 to 33 P40 to 43 P50 to 53 P60 to 63 P70 to 73 P80 to 83 BP0 to 7 KR0 to 7 AV REF AV SS AN0 to 7 SCK SI SO MD0 to 3 VPP 4 : : : : : : : : : : : : : : : : : : : Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Bit Port Key Return Analog Reference Analog Ground Analog Input 0 to 7 Serial Clock Serial Input Serial Output Mode Selection Programming/Verifying Power Supply SB0, 1 RESET S12 to 31 COM0 to 3 VLC0 to 2 BIAS LCDCL SYNC TI0, 1 PTO0, 1 BUZ PCL INT0, 1, 4 INT2 X1, 2 XT1, 2 VDD VSS : : : : : : : : : : : : : : : : : : Serial Bus 0,1 Reset Input Segment Output 12 to 31 Common Output 0 to 3 LCD Power Supply 0 to 2 LCD Power Supply Bias Control LCD Clock LCD Synchronization Timer Input 0, 1 Programmable Timer Output 0, 1 Buzzer Clock Programmable Clock External Vectored Interrupt 0, 1, 4 External Test Interrupt 2 Main System Clock Oscillation 1, 2 Subsystem Clock Oscillation 1, 2 Positive Power Supply Ground µPD75P336 CONTENTS 1. PIN FUNCTIONS ......................................................................................................................................... 6 1.1 1.2 PORT PINS ............................................................................................................................................................. 6 OTHER PINS .......................................................................................................................................................... 8 1.3 PIN INPUT/OUTPUT CIRCUITS ...........................................................................................................................10 2. DIFFERENCES BETWEEN µPD75P336 AND µPD75336 ......................................................................... 13 2.1 2.2 PROGRAM MEMORY (PROM) 16256 WORDS × 8 BITS .................................................................................. 14 DATA MEMORY (RAM) 768 WORDS × 4 BITS .................................................................................................. 15 3. INSTRUCTION SET AND INSTRUCTION OPERATIONS ....................................................................... 16 4. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY OPERATIONS .................................. 25 4.1 4.2 4.3 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES ........................................................................... 26 PROGRAM MEMORY WRITE PROCEDURE ....................................................................................................... 27 PROGRAM MEMORY READ PROCEDURE ......................................................................................................... 28 5. ELECTRICAL SPECIFICATIONS ................................................................................................................ 29 6. PACKAGE INFORMATION ........................................................................................................................ 48 7. RECOMMENDED SOLDERING CONDITIONS ......................................................................................... 50 APPENDIX A. LIST OF FUNCTIONS.............................................................................................................. 51 APPENDIX B. DEVELOPMENT TOOLS ......................................................................................................... 52 5 µPD75P336 1. PIN FUNCTIONS 1.1 PORT PINS (1/2) Pin Name Input/Output DualFunction Pin P00 Input INT4 P01 Input/output SCK P02 Input/output SO/SB0 P03 Input/output SI/SB1 P11 4-bit input port (PORT0) Internal pull-up resistor specification by software is possible for P01 to P03 as a 3-bit unit. P12 INT2 P13 TI0 P20 PTO0 PTO1 P21 Input/output P22 PCL P23 BUZ P30 *2 LCDCL MD0 P31 *2 SYNC MD1 Input/output P32 *2 MD2 P33 *2 MD3 After Reset I/O Circuit Type *1 × F -A Input F -B M-C With noise elimination circuit INT1 Input 8-bit I/O B INT0 P10 4-bit input port (PORT1) Internal pull-up resistor specification by software is possible as a 4-bit unit. 4-bit input/output port (PORT2) Internal pull-up resistor specification by software is possible as a 4-bit unit. Programmable 4-bit input/output port (PORT3) Input/output settable bit-wise. Internal pull-up resistor specification by software is possible as a 4-bit unit. × Input B -C × Input E-B × Input E-B P40 to P43 *2 Input/output — N-ch open-drain 4-bit input/output port (PORT 4). Data input/output pins for program memory (PROM) write/verify (low-order 4 bits). Input M-B P50 to P53 *2 Input/output — N-ch open-drain 4-bit input/output port (PORT 5) Data input/output pins for program memory (PROM) write/verify (high-order 4 bits). Input M-B Input F -A Input F -A KR0 P60 P61 * 1. 2. Input/output KR1 P62 KR2 P63 KR3 P70 KR4 P71 6 Function Input/output KR5 P72 KR6 P73 KR7 Programmable 4-bit input/output port (PORT6). Input/output settable bit-wise. Internal pull-up resistor specification by software is possible as a 4-bit unit. 4-bit input/output port (PORT7). Internal pull-up resistor specification by software is possible as a 4-bit unit. : Indicates a Schmitt-triggered input. Direct LED drive capability. µPD75P336 1.1 PORT PINS (2/2) Pin Name Input/Output P80 DualFunction Pin Function 8-bit I/O After Reset TI1 — P81 Input/output P82 AN6 P83 AN7 BP0 S24 I/O Circuit Type E-E 4-bit input/output port (PORT8). Internal pull-up resistor specification by software is possible as a 4-bit unit. × E-B Input Y-B S25 BP1 Output BP2 S26 BP3 S27 BP4 S28 1-bit output port (BIT PORT) Dual function as segment output pins. × * G-C S29 BP5 Output * BP6 S30 BP7 S31 VLCX shown below can be selected for the display outputs. S12 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0 However, display output levels depend on the display outputs and VLCX external circuit. 7 µPD75P336 1.2 OTHER PINS (1/2) Pin Name Input/Output TI0 DualFunction Pin TI1 I/O Circuit Type * B -C External event pulse input pin for timer/event counter. Input P80 PTO0 B -E P20 output PTO1 Timer/event counter output pin Input E-B P21 PCL output P22 Clock output pin Input E-B BUZ output P23 Frequency output pin (for buzzer or system clock trimming) Input E-B SCK Input/output P01 Serial clock input/output pin Input F -A SO/SB0 Input/output P02 Serial data output pin Serial bus input/output pin Input F -B SI/SB1 Input/output P03 Serial data input pin Serial bus input/output pin Input M-C INT4 Input P00 Edge-detected vectored interrupt input pin (both rising and falling edge detection valid). Input Edge-detected vectored interrupt input pin (detected edge selectable) Input B -C Input B -C INT0 P10 Input INT1 8 After Reset P13 Input * Function P11 Edge-detected testable input pin (rising edge detection) B Clocked Asynchronous INT2 Input P12 KR0 to KR3 Input P60 to P63 Parallel falling edge detected testable input pins. Input F -A KR4 to KR7 Input P70 to P73 Parallel falling edge detected testable input pins. Input F -A X1, X2 — — Main system clock oscillation crystal/ceramic resonator inputs. When an external clock is used, the clock is input to X1 and the inverted clock to X2. — — — –– — B Input E-B — — Asynchronous XT1, XT2 — — Subsystem clock oscillation crystal reasonator inputs When an external clock is used, the clock is input to XT1 and the inverted clock toXT2. XT1 can be used as a 1bit input (test) pin. RESET Input — System reset input pin. MD0 to MD3 Input/output P30 to P33 Mode selection pin for program memory (PROM) write/ verify. VPP — — Program voltage application pin for program memory (PROM) write/verify. Applies +12.5 V in program memory write/verify. Directly connected to VDD in normal operation. VDD — — Positive power supply pin — — VSS — — GND potential pin — — : indicates a Schmitt-triggered input. µPD75P336 1.2 OTHER PINS (2/2) Pin Name Input/Output DualFunction Pin After Reset I/O Circuit Type S12 to S23 Output — Segment signal output pins *2 G-A S24 to S31 Output BP0 to 7 Segment signal output pins *2 G-C COM0 to COM3 Output — Common signal output pins *2 G-B VLC0 to VLC2 Input — LCD drive power supply pins — — BIAS Output — External split cutting output pin LCDCL*1 Output P30 External extension driver drive clock output pin Input SYNC *1 Output P31 External extension driver synchronization drive clock output pin Input Function High impedance — AN0 to AN5 AN6 E-B — Input P82 E-B Y A/D converter analog signal input pins Input Y -B AN7 * 1. 2. P83 AVREF Input — A/D converter reference voltage input pin — Z AVSS — — A/D converter GND potential pin — Z Pins provided for future system expansion. Currently used only as pins 30 and 31. VLCX shown below can be selected for the display outputs. S12 to S31: VLC1, COM0 to COM2: VLC2, COM3:VLC0 However, display output levels depend on the display outputs and VLCX external circuit. 9 µPD75P336 1.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuits for each of the pin µPD75P336 are shown below in partially simplified form. TYPE A (For TYPE E-B) TYPE D (For TYPE E-B, F-A) VDD VDD data P-ch OUT P-ch IN N-ch CMOS Standard Input Buffer TYPE B output disable N-ch Push-Pull Output that can be Made High-Impedance Output (P-ch and N-ch OFF) TYPE E-B VDD P.U.R. output disable IN P-ch data IN/OUT Type D output disable Type A P.U.R.:Pull-Up Resistor Schmitt-Trigger Input with Hysteresis Characteristic TYPE B-C TYPE E-E VDD P.U.R. P.U.R. enable VDD P.U.R. P-ch P-ch data P.U.R. enable output disable IN/OUT Type D Type A IN Type B P.U.R. : Pull-Up Resistor Schmitt-Trigger Input with Hysteresis Characteristic 10 P.U.R.:Pull-Up Resistor µPD75P336 TYPE F-A TYPE G-B VDD VLC0 P.U.R. P.U.R. enable P-ch VLC1 P-ch P-ch N-ch data IN/OUT Type D output disable OUT COM data N-ch Type B P-ch VLC2 N-ch P.U.R.:Pull-Up Resistor TYPE F-B TYPE G-C VDD P.U.R. P.U.R. enable VDD P-ch P-ch VLC0 VDD output disable (P) P-ch data output disable VLC1 IN/OUT P-ch SEG data/Bit Port data N-ch output disable (N) OUT N-ch VLC2 N-ch P.U.R.:Pull-Up Resistor TYPE G-A TYPE M-B IN/OUT VLC0 P-ch data VLC1 P-ch SEG data OUT N-ch output disable N-ch VLC2 N-ch Middle-High Voltage Input Buffer 11 µPD75P336 TYPE M-C VDD TYPE Y-B VDD P.U.R. P.U.R. enable P.U.R enable P-ch IN/OUT data data output disable N-ch P-ch output disable IN/OUT Type D Type A Type Y P.U.R.:Pull-Up Resistor P.U.R:Pull-Up Resistor TYPE Y TYPE Z VDD IN P-ch N-ch VDD + Sampling C - AVSS AVSS input enable 12 IN Reference Voltage Reference Voltage (From Series Resistance Voltage Tap) AVSS µPD75P336 2. DIFFERENCES BETWEEN µPD75P336 AND µPD75336 µPD75336 Parameter µPD75P336 Program memory Mask ROM 16256 × 8 bits One-time PROM 16256 × 8 bits Data memory 768 × 4 bits 768 × 4 bits Ports 4, 5 pull-up resistor Incorporation specifiable by mask option No LCD drive power supply split resistor Incorporation specifiable by mask option No Subsystem clock oscillation feedback resistor Incorporation specifiable by mask option Incorporated Pin 69 IC VPP 13 µPD75P336 2.1 PROGRAM MEMORY (PROM) ..... 16256 WORDS × 8 BITS The program memory consists of 16256-byte PROM. The program memory map is shown in Fig. 2-1. Fig. 2-1 Program Memory Map 0000H 7 6 MBE RBE 0 Internal Reset Start Address (High-Order 6 Bits) (Low-Order 8 Bits) 0002H MBE RBE INTBT/INT4 Start Address (High-Order 6 Bits) (Low-Order 8 Bits) 0004H MBE RBE INT0 Start Address (High-Order 6 Bits) (Low-Order 8 Bits) 0006H MBE RBE INT1 Start Address CALLF !faddr Instruction Entry Address (High-Order 6 Bits) (Low-Order 8 Bits) 0008H MBE RBE INTCSI Start Address (High-Order 6 Bits) BRCB !caddr Instruction Branch Address BR !addr Instruction Branch Address (Low-Order 8 Bits) 000AH MBE RBE INTT0 Start Address (High-Order 6 Bits) (Low-Order 8 Bits) 000CH MBE RBE INTT1 Start Address (High-Order 6 Bits) (Low-Order 8 Bits) ≈ ≈ 0020H CALL !addr Instruction Branch Address Branch/Call Address, by GETI GETI Instruction Reference Table 007FH 0080H ≈ ≈ 07FFH 0800H ≈ ≈ ≈ ≈ ≈ ≈ BR $addr Instruction Relative Branch Address (-15 to -1, +2 to +16) 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H ≈ 3F7FH 14 ≈ BRCB !caddr Instruction Branch Address BRCB !caddr Instruction Branch Address BRCB !caddr Instruction Branch Address µPD75P336 Remarks 2.2 In addition to the above, branching is possible with the BR PCDE and BR PCXA instructions to addresses with the low-order 8 bits only of the PC modified. DATA MEMORY (RAM) .......768 WORDS × 4 BITS The configuration of the data memory is shown in Fig. 2-2. The data memory comprises a data area and peripheral hardware area, the data area comprises 768 × 4-bit static RAM. Fig. 2-2 Data Memory Map Data Memory General Register Area Stack Area 000H (32 × 4) 01FH 020H Memory Bank 0 256 × 4 0FFH 100H Data Area Static RAM 768 × 4 Memory Bank 1 Display Data Memory Area 1EBH 1ECH 256 × 4 1FFH 200H (20 × 4) Memory Bank 2 256 × 4 2FFH Not On-Chip F80H Memory Bank 15 Peripheral Hardware Area FFFH 128 × 4 15 µPD75P336 3. INSTRUCTION SET AND INSTRUCTION OPERATIONS (1) Operand identifier and description Operand identifiers and description method operands are written in the operand column for each instruction in accordance with the description method for the operand identifier for that instruction (refer to "RA75X Assembler Package User's Manual Language Volume (EEU-730)" for details). Where multiple items are included in the description method, one of those elements should be selected. Uppercase letters and the symbols + and – are keywords and should be written as they are. In the case of immediate data, an appropriate number or label is written. Description Method Descriptor reg X, A, B, C, D, E, H, L reg1 X, B, C, D, E, H, L rp XA, BC, DE, HL rp1 BC, DE, HL rp2 BC, DE rp' XA, BC, DE, HL, XA', BC', DE' HL' rp'1 BC, DE, HL, XA', BC', DE', HL' rpa HL, HL+, HL–, DE, DL rpa1 DE, DL n4 4-bit immediate date or label n8 8-bit immediate date or label mem 8-bit immediate date or label* bit 2-bit immediate date or label fmem FB0H to FBFH, FF0H to FFFH immediate data or label pmem FC0H to FFFH immediate data or label addr 0000H to 3F7FH immediate data or label caddr 12-bit immediate date or label faddr 11-bit immediate date or label taddr 20H to 7FH immediate date (bit 0 = 0) or label PORTn PORT0 to PORT8 IE××× IEBT, IECSI, IET0, IET1, IE0 to IE2, IE4, IEW RBn RB0 to RB3 MBn MB0, MB1, MB2, MB15 * 16 In 8-bit data processing, only an even address can be specified. µPD75P336 (2) Operation description legend A : A register; 4-bit accumulator B : B register; 4-bit accumulator C D E H : : : : C register; 4-bit accumulator D register; 4-bit accumulator E register; 4-bit accumulator H register; 4-bit accumulator L X XA BC : : : : L register; 4-bit accumulator X register; 4-bit accumulator Register pair (XA); 8-bit accumulator Register pair (BC); 8-bit accumulator DE HL XA' BC' : : : : Register pair (DE); 8-bit accumulator Register pair (HL); 8-bit accumulator Extended register pair (XA') Extended register pair (BC') DE' HL' PC SP : : : : Extended register pair (DE') Extended register pair (HL') Program counter Stack pointer CY PSW MBE RBE : : : : Carry flag; bit accumulator Program status word Memory bank enable flag Register bank enable flag PORTn IME IPS IE××× : : : : Portn (n = 0 to 8) Interrupt master enable flag Interrupt priority selection register Interrupt enable flag RBS MBS PCC . : : : : Register bank selection register Memory bank selection register Processor clock control register Address, bit delimiter (××) ××H : Contents addressed by ×× : Hexadecimal data 17 µPD75P336 (3) Description of addressing area field symbols *1 MB = MBE • MBS *2 MB = 0 *3 MBE = 0 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) MBE = 1 : MB = MBS (MBS = 0, 1, 2, 15) *4 MB = 15, fmem = FB0H to FBFH, FF0H to FFFH *5 MB = 15, pmem = FC0H to FFFH *6 addr = 0000H to 3F7FH *7 addr = (Current PC) –15 to (Current PC) –1 (Current PC) + 2 to (Current PC) + 16 *8 caddr = 0000H to 0FFFH (PC13,12 = 00B) or 1000H to 1FFFH (PC13,12 = 01B) or 2000H to 2FFFH (PC13,12 = 10B) or 3000H to 3FFFH (PC13,12 = 11B) *9 faddr = 0000H to 07FFH *10 taddr = 0020H to 007FH Remarks 1. 2. 3. 4. MBS = 0, 1, 2, 15 Data Memory Addressing Program Memory Addressing MB indicates the accessible memory bank. MB=0 irrespective of MBE and MBS in *2. MB=15 irrespective of MBE and MBS in *4 and *5. *6 to *10 indicate accessible area. (4) Explanation of machine cycle column "S" indicates the number of machine cycles required when an instruction with a skip function performs a skip operation. The value of "s" is as follows: • When a skip is not performed ....................................................................................................................... S = 0 • When the skipped instruction is a 1-byte or 2-byte instruction ................................................................ S = 1 • When the skipped instruction is a 3-byte instruction (BR !addr or CALL !addr) ................................... S = 2 Note A GETI instruction is skipped in one machine cycle. One machine cycle is equivalent to one cycle (=tCY)of the CPU clock cycle Φ : selected according to the PCC setting. 18 any of four times can be Machine Cycles Mnemonic Bytes Note 1 µPD75P336 A, #n4 1 1 A ← n4 reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 Stack A HL, #n8 2 2 HL ← n8 Stack B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @HL+ 1 2+S A ← (HL), then L← L + 1 *1 L=0 A, @HL– 1 2+S A ← (HL), then L← L – 1 *1 L = FH A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A *1 @HL, XA 2 2 (HL) ← XA *1 A, mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A *3 mem, XA 2 2 (mem) ← XA *3 A, reg 2 2 A ← reg XA, rp' 2 2 XA ← rp' reg1, A 2 2 reg1 ← A rp'1, XA 2 2 rp'1 ← XA A, @HL 1 1 A ↔ (HL) *1 A, @HL+ 1 2+S A ↔ (HL), then L← L + 1 *1 L=0 A, @HL– 1 2+S A ↔ (HL), then L← L –1 *1 L = FH A, @rpa1 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A,reg1 1 1 A ↔ reg1 XA, rp' 2 2 XA ↔ rp' XA, @PCDE 1 3 XA ← (PC13–8 + DE)ROM XA, @PCXA 1 3 XA ← (PC13–8 + XA)ROM Operand Transfer MOV Note 2 XCH MOVT Note 1. 2. Operation Addressing Area Skip Condition Stack A Instruction Group Table reference 19 CY, fmem.bit 2 2 CY ← (fmem.bit) *4 CY, pmem.@L 2 2 CY ← (pmem7–2 + L 3–2.bit (L1–0)) *5 CY, @H + mem.bit 2 2 CY ← (H + mem3-0.bit) *1 fmem.bit, CY 2 2 (fmem.bit)← CY *4 pmem.@L, CY 2 2 (pmem7–2 + L 3–2.bit (L1–0)) ← CY *5 @H + mem.bit, CY 2 2 (H + mem3-0.bit) ← CY *1 monic MOV1 ADDS ADDC SUBS Operation Operand Machine Cycles Mne- Bytes Bit transfer Note µPD75P336 SBUC AND OR XOR Addressing Area Skip Condition A, #n4 1 1+S A ← A + n4 carry XA, #n8 2 2+S XA ← XA + n8 carry A, @HL 1 1+S A ← A + (HL) XA, rp' 2 2+S XA ← XA + rp' carry rp'1, XA 2 2+S rp'1← rp'1 + XA carry A, @HL 1 1 A, CY ← A + (HL) + CY XA, rp' 2 2 XA, CY ← XA + rp' + CY rp'1, XA 2 2 rp'1, CY ← rp'1 + XA + CY A, @HL 1 1+S A ← A − (HL) XA, rp' 2 2+S XA ← XA − rp' borrow rp'1, XA 2 2+S rp'1← rp'1 − XA borrow A, @HL 1 1 A , CY← A − (HL) − CY XA, rp' 2 2 XA, CY← XA − rp' − CY rp'1, XA 2 2 rp'1, CY ← rp'1 − XA − CY A, #n4 2 2 A←A ∧ n4 A, @HL 1 1 A←A ∧ (HL) XA, rp' 2 2 XA ← XA rp'1, XA 2 2 rp'1← rp'1 A, #n4 2 2 A←A ∨ n4 A, @HL 1 1 A←A ∨ (HL) XA, rp' 2 2 XA ← XA rp'1, XA 2 2 rp'1← rp'1 A, #n4 2 2 A←A ∨ n4 A, @HL 1 1 A←A ∨ (HL) XA, rp' 2 2 XA ← XA rp'1, XA 2 2 rp'1← rp'1 Note Instruction Group 20 Operation *1 *1 *1 *1 *1 ∧ rp' ∧ XA *1 ∨ rp' ∨ XA ∨ rp' ∨ XA carry *1 borrow Bytes Machine Cycles Note 2 Note 1 µPD75P336 RORC A 1 1 CY ← A0, A3 ← CY, An–1 ← An NOT A 2 2 A←A reg 1 1+S reg ← reg + 1 reg = 0 rp1 1 1+S rp1 ← rp1 + 1 rp1 = 00H @HL 2 2+S (HL) ← (HL) + 1 *1 (HL) = 0 mem 2 2+S (mem) ← (mem) + 1 *3 (mem) = 0 reg 1 1+S reg ← reg – 1 reg = FH rp' 2 2+S rp' ← rp' – 1 rp' = FFH reg, #n4 2 2+S Skip if reg = n4 reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A = reg XA, rp' 2 2+S Skip if XA = rp' XA = rp' SET1 CY 1 1 CY ← 1 CLR1 CY 1 1 CY ← 0 SKT CY 1 1+S NOT1 CY 1 1 Mnemonic Note 3 INCS Operand Note 4 Comparison DECS SKE Note 1. 2. 3. 4. Operation Skip if CY = 1 Addressing Area Skip Condition CY = 1 CY ← CY Instruction Group Accumulator operation Increment and decrement Carry flag manipulation 21 SET1 CLR1 Memory bit manipulation SKT SKF SKTCLR AND1 OR1 Branch XOR1 Machine Cycles Mnemonic Bytes Note µPD75P336 mem.bit 2 2 (mem.bit) ← 1 *3 fmem.bit 2 2 (fmem.bit) ← 1 *4 pmem.@L 2 2 (pmem7–2 + L 3–2.bit (L1–0)) ← 1 *5 @H + mem.bit 2 2 (H + mem3–0.bit) ← 1 *1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem.@L 2 2 (pmem7–2 + L 3–2.bit (L1–0)) ← 0 *5 @H + mem.bit 2 2 (H + mem3–0.bit) ← 0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7–2 + L 3–2.bit (L1–0)) = 1 *5 (pmem.@L) = 1 @H + mem.bit 2 2+S Skip if (H + mem3–0.bit) = 1 *1 (@H + mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@L 2 2+S Skip if (pmem7–2 + L 3–2.bit (L1–0))= 0 *5 (pmem.@L) = 0 @H + mem.bit 2 2+S Skip if (H + mem3–0.bit) = 0 *1 (@H + mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7–2 + L 3–2.bit (L1–0)) = 1 and clear *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H + mem3–0.bit) = 1 and clear *1 (@H + mem.bit) = 1 CY, fmem.bit 2 2 CY ← CY ∧ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∧ (pmem7–2 + L3–2.bit (L1–0)) *5 CY, @H + mem.bit 2 2 CY ← CY ∧ (H + mem3-0.bit) *1 CY, fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∨ (pmem7–2 + L3–2.bit (L1–0)) *5 CY, @H + mem.bit 2 2 CY ← CY ∨ (H + mem3-0.bit) *1 CY, fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY ∨ (pmem7–2 + L3–2.bit (L1–0)) *5 CY, @H + mem.bit 2 2 CY ← CY ∨ (H + mem3-0.bit) *1 *6 *6 Operand BR addr — — PC13–0 ← addr (The assembler selects the optimum instruction from among the BRCB !caddr, and BR $addr instructions.) BR !addr 3 3 PC13–0 ← addr BRCB !caddr 2 2 PC13–0 ← PC BR $addr 1 2 PC13–0 ← addr PCDE 2 3 PC13–0 ← PC 13-8 + DE PCXA 2 3 PC13–0 ← PC 13-8 + XA BR Note 22 Operation Instruction Group 13.12 + caddr11–0 Addressing Area *8 *7 Skip Condition Bytes Machine Cycles Subroutine stack control Note 1 µPD75P336 CALL !addr 3 3 (SP – 4) (SP – 1) (SP – 2) ← PC11–0 (SP – 3) ← MBE, RBE, PC13.12 PC13–0 ← addr, SP ← SP – 4 *6 CALLF !faddr 2 2 (SP – 4) (SP – 1) (SP – 2) ← PC11–0 (SP – 3) ← MBE, RBE, PC13.12 PC13–0 ← 000 + faddr, SP ← SP – 4 *9 1 3 MBE, RBE, PC13.12 ← (SP + 1) PC11–0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 4 MBE, RBE, PC13.12 ← (SP + 1) PC11–0 ← (SP) (SP + 3) (SP + 2) SP ← SP + 4 the skip unconditionally Mnemonic RET 1 3+S RETI 1 3 ×, ×, PC13.12 ← (SP + 1) PC11–0 ← (SP) (SP + 3) (SP + 2) PSW ← (SP + 4) (SP + 5), SP ← SP + 6 rp 1 1 (SP – 1) (SP – 2) ← rp, SP ← SP – 2 BS 2 2 (SP – 1) ← MBS, (SP – 2) ← RBS, SP ← SP – 2 rp 1 1 rp ← (SP + 1) (SP), SP ← SP + 2 BS 2 2 MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2 2 2 IME (IPS.3) ← 1 2 2 IE × × × ← 1 2 2 IME (IPS.3) ← 0 IE× × × 2 2 IE × × × ← 0 A, PORTn 2 2 A ← PORT n XA, PORTn 2 2 XA ← PORTn+1, PORTn (n = 4, 6) PORTn, A 2 2 PORTn ← A (n = 2–8) PORTn, XA 2 2 PORTn+1, PORTn ← XA (n =4, 6) HALT 2 2 Set HALT Mode (PCC.2 ← 1) STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation RBn 2 2 RBS ← n (n = 0–3) MBn 2 2 MBS ← n (n = 0,1,2,15) POP Input/Output Note 2 EI Note 3 Addressing Area Operation RETS PUSH DI IN*1 OUT*1 SEL Special Operand GETI*2 IE× × × taddr 1 3 Skip Condition Unconditional (n = 0–8) • TBR Instruction PC13–0 ← (taddr) 5–0 + (taddr + 1) ----------------------------------------------------------------------• TCALL Instruction (SP – 4) (SP – 1) (SP – 2) ← PC11–0 (SP – 3) ← MBE, RBE, PC13, 12 PC13–0 ← (taddr) 5–0 ← (taddr + 1) SP ← SP – 4 ----------------------------------------------------------------------• Other than TBR and TCALL Instruction Execution of an instruction addressed at (taddr) and (taddr + 1) *10 ----------------------------- ----------------------------Conforms to referenced instruction. 23 µPD75P336 * 1. At IN/OUT instruction execution, MBE = 0 or MBE = 1, MBS = 15 must be set in advance. 2. TBR and TCALL instructions are assembler pseudo-instructions for table definition. Note 24 1. Instruction Group 2. Interruput control 3. CPU control µPD75P336 4. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY OPERATIONS The program memory incorporated in the µPD75P336 is 32640 × 8-bit electrically writable one-time PROM. Write/verify operations on this one-time PROM are executed using the pins shown in the table below. Address updating is performed by means of clock input from the X1 pin rather than by address input. Pin Name Note Function VPP Voltage applecation pin for program memory write/verify (normally VDD potential). X1, X2 Address update clock inputs for program memory write/verify. Inverse of X1 pin signal is input to X2 pin. MD0 to MD3 Operating mode selection pin for program memory write/verify. P40 to P43 (low-order 4 bits) P50 to P53 (high-order 4 bits) 8-bit data input/output pins for progrm memory write/verify. VDD Supply voltage application pin. Applies 2.7 to 6.0 V in normal operation, and 6 V for program memory write/verify. 1. Pins not used in a program memory write/verify operation are handled as follows: • Pins other than XT2 .......... Connect to VSS with a pull-down resistor • XT2 pins ............................. Leave open 2. Since the µPD75P336 is not provided with an erase window, program memory contents cannot be erased with ultra-violet light. 4.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the µPD75P336 enters the program memory write/ verify mode. This mode comprises one of the operating modes shown below according to the setting of pins MD0 to MD3. Operating Mode Setting Operating Mode VPP +12.5 V VDD MD0 MD1 MD2 MD3 H L H L Program memory address zero-clear L H H H Write mode L L H H Verify mode H X H H Program inhibit mode +6V X: L or H 25 µPD75P336 4.2 PROGRAM MEMORY WRITE PROCEDURE The procedure for writing to program memory is as shown below, allowing high-speed writing. (1) Unused pins are connected to VSS with a pull-down resistor. The X1 pin is driven low. (2) 5 V is supplied to the VDD and VPP pins. (3) (4) (5) (6) 10 µ s wait. Program memory address zero-clear mode. 6 V is supplied to VDD, 12.5 V to VPP. Program inhibit mode. (7) (8) (9) (10) Data is written in 1 ms write mode. Program inhibit mode. Verify mode. If write is successful go to (10), otherwise repeat (7) to (9). (Number of times written in (7) to (9): X) × 1 ms additional writes. (11) (12) (13) (14) Program inhibit mode. Program memory address is updated (+1) by inputting 4 pulses to the X1 pin. Steps (7) to (12) are repeated until the last address. Program memory address zero-clear mode. (15) V DD / VPP pin voltage is changed to 5 V. (16) Power-off. Steps (2) to (12) of this procedure are shown in the figure below. Repeated X Times Write ≈ VPP ≈ VDD VDD + 1 VDD VDD Data Input Data Output ≈ P40-P43 P50-P53 ≈ X1 ≈ VPP Additional Write Verify ≈ MD0 (P30) ≈ MD1 (P31) ≈ MD2 (P32) MD3 (P33) 26 Data Input Address Increment µPD75P336 4.3 PROGRAM MEMORY READ PROCEDURE µPD75P336 program memory contents can be read using the following procedure. (1) (2) (3) (4) Unused pins are connected to VSS with a pull-down resistor. The X1 pin is driven low. 5 V is supplied to the VDD and VPP pins. 10 µs wait. Program memory address zero-clear mode. (5) (6) (7) 6 V supplied to VDD, and 12.5 V to VPP. Program inhibit mode. Verify mode. When clock pulses are input to the X1 pin, data is output sequentially, one address per 4-pulse-input cycle. (8) (9) (10) (11) Program inhibit mode. Program memory address zero-clear mode. VDD / VPP pin voltage is changed to 5 V. Power-off. Steps (2) to (9) of this procedure are shown in the figure below. VDD ≈ VPP ≈ VPP VDD + 1 ≈ VDD MD0 (P30) ≈ Data Output ≈ MD1 (P31) Data Output ≈ P40-P43 P50-P53 ≈ X1 ≈ VDD ≈ MD2 (P32) MD3 (P33) 27 µPD75P336 µPD75P336 PD75304B 5. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C) PARAMETER TEST CONDITIONS SYMBOL RATING VDD ★ Power supply voltage Input voltage Output voltage Output current high VPP VI1 Except ports 4, 5 VI2 Ports 4, 5 Open-drain VO IOH V –0.3 to +13.5 V –0.3 to VDD +0.3 V –0.3 to +11 V –0.3 to VDD +0.3 V 1 pin mA All pins –30 mA Peak value 30 mA Effective value 15 mA Peak value 100 mA Effective value 60 mA Peak value 100 mA Effective value 60 mA Total of ports 0, 2, 3, 5, 18 IOL* –0.3 to +7.0 –15 1 pin Output current low UNIT Total of ports 4, 6, 7 Operating temperature Topt –40 to +85 °C Storage temperature Tstg –65 to +150 °C * Rms value is calculated from [effective value] = [peak value] × √duty CAPACITANCE (Ta = 25 °C, VDD = 0 V) PARAMETER Input capacitance 28 SYMBOL TEST CONDITIONS CIN Output capacitance COUT I/O capacitance CIO f = 1 MHz Unmeasured pins returned to 0 V. MIN. TYP. MAX. UNIT 15 pF 15 pF 15 pF µPD75P336 µPD75P336 PD75304B MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) ESONATOR RECOMMENDED CONSTANT PARAMETER TEST CONDITIONS Oscillator frequency (fx)*1 X1 TYP. 1.0 MAX. UNIT 5.0*3 MHz 4 ms 5.0*3 MHz 10 ms 30 ms X1 Ceramic resonator C1 C2 Oscillation stabilization time*2 VDD X1 MIN. Oscillator frequency (fx)*1 X1 Crystal resonator C1 After VDD reached the MIN. of the oscillator voltage range. C2 Oscillation stabilization time*2 1.0 VDD = 4.5 to 6.0 V 4.19 VDD X1 X2 External clock µ PD74HCU04 * X1 input frequency (fx)*1 1.0 5.0*3 MHz X1 input high-/low-level width (tXH, tXL ) 100 500 ns 1. Shows the oscillator characteristics only. For the instruction execution time, see the AC characteristics. 2. Time necessary for oscillation to stabilize after VDD applied or STOP mode released. 3. When the oscillator frequency is “4.19 MHz < fX ≤ 5.0 MHz”, it is impossible to select of “PCC = 0011” with 1 machine cycle of less than 0.95 µs as instruction execution time. 29 µPD75P336 µPD75P336 PD75304B SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) RESONATOR RECOMMENDED CONSTANT XT1 C4 MIN. TYP. MAX. UNIT 32 32.768 35 kHz 1.0 2 s 10 s VDD = 4.5 to 6.0 V R C3 TEST CONDITIONS Oscillator frequency (f XT) XT2 Crystal resonator PARAMETER Oscillation stabilization time VDD XT1 input frequency (f XT) XT1 External clock 32 100 5 15 kHz XT2 Leave Open XT1 input high-/ low-level width µs (tXTH,tXTL) Note When the main system clock and subsystem clock oscillation circuit are used, area inside doted lines in the figure should be wired as follows to prevent influence from the wiring capacitance, etc.. • Wiring should be as short as possible. • Do not cross other signal lines, and do not place the oscillator close to line in which varying high current flows. • Potential at the oscillator capacitor connecting point should always be the same as VDD. Do not connect to the power supply pattern in which high current flows. • Do not fetch signals from the oscillator. In the subsystem clock oscillator, which is designed to be a circuit with low amplification ratio to suppress consumption current, misoperation due to noise occurs more often than in the main system clock oscillator. Therefore, when using the subsystem clock, special care should be taken in the wiring method. 30 µPD75P336 µPD75P336 PD75304B DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) (1/3) PARAMETER Input voltage high Input voltage low SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VIH1 Ports 2, 3, 8 0.7 VDD VDD V VIH2 Ports 0, 1, 6, 7, RESET 0.8 VDD VDD V VIH3 Ports 4 and 5 0.7 VDD 10 V VIH4 X1, X2, XT1 VDD –0.5 VDD V VIL1 Ports 2, 3, 4, 5, 8 0 0.3 VDD V VIL2 Ports 0, 1, 6, 7 RESET 0 0.2 VDD V VIL3 X1, X2, XT1 0 0.4 V VOH1 Ports 0, 2, 3, 6, 7, 8 BIAS Open-drain VDD = 4.5 to 6.0 V IOH = –1 mA VDD –1.0 V Output voltage IOH = –100 µA VDD –0.5 V high VDD = 4.5 to 6.0 V IOH = –100 µA VDD –2.0 V IOH = –50 µA VDD –1.0 V VOH2 BP0 to BP7 (I OH 2 outputs) 31 µPD75P336 µPD75P336 PD75304B DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) (2/3) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT 0.4 2.0 V VDD = 4.5 to 6.0 V IOL = 1.6 mA 0.4 V IOL = 400 µA 0.5 V Open-drain pull-up 0.2 VDD V VDD = 4.5 to 6.0 V IOL = 100 µA 1.0 V IOL = 50 µA 1.0 V Other than below 3 µA X1, X2, XT1 20 µA Ports 4, 5 (when opendrain) 20 µA Other than below –3 µA X1, X2, XT1 –20 µA Other than below 3 µA Ports 4 and 5 (when opendrain) 20 µA –3 µA 80 kΩ Ports 3, 4, 5 VDD = 4.5 to 6.0 V IOL = 15 mA VOL1 Ports 0, 2, 3, 4, 5, 6 7, 8 Output voltage low SB0, 1 resistor ≥ 1 kΩ VOL2 BP0 to BP7 (IOL 2 outputs) ILIH1 VIN = VDD Input leakage current high ILIH2 ILIH3 Input leakage current low VIN = 10 V ILIL1 VIN = 0 V ILIL2 Output leakage current high Output leakage current low Built-in Pull-up resistor LCD drive voltage 32 ILOH1 VOUT = VDD ILOH2 VOUT = 10 V ILOL VOUT = 0 V RL1 Ports 0, 1, 2, 3, 6 7, 8 (Except P00) VIN = 0 V VLCD VDD = 5.0 V ±10% 15 VDD = 3.0 V ±10% 30 300 kΩ 2.5 VDD V 40 µPD75P336 µPD75P336 PD75304B DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) (3/3) PARAMETER SYMBOL TEST CONDITION LCD output voltage deviation*1 (common) VODC I O = ±5 µA LCD output voltage deviation*1 (segment) VODS I O = ±1 µA IDD1 4.19 MHz crystal oscillation C1= C2 = 22 pF*3 VLCD0 = VLCD VLCD1 = VLCD × 2/3 VLCD2 = VLCD × 1/3 2.7 V ≤ VLCD ≤ VDD IDD3 32 kHz crystal oscillation*6 UNIT 0 ±0.2V V 0 ±0.2V V 15 mA VDD = 3 V ±10 %*5 1 3 mA VDD = 5V ±10 % 500 1500 µA VDD = 3V ±10 % 300 900 µA Operat- VDD = 3V ing ±10 % mode 100 300 µA VDD = 3V ±10 % 20 60 µA VDD = 5 V ±10 % 0.5 20 µA VDD = 0.1 10 µA 0.1 5 µA HALT mode IDD4 MAX. 5 mode Power supply current *2 TYP. VDD = 5 V ±10 %*4 HALT IDD2 MIN. XT1 = 0 V STOP mode IDD5 3V ±10 % * Ta = 25 °C 1. The voltage deviation means a difference between the ideal value of segment or common output (VLCDn; n = 0, 1, 2) and the output voltage. 2. Current flowing in the built-in pull-up resistor and the LCD split resistor is not include. 3. Including the case where the subsystem clock is operating. 4. When the processor clock control register (PCC) is set to 0011 and operated in high-speed mode. 5. When PCC is set to 0000 and operated in the low-speed mode. 6. The case where the system clock control register (SCC) is set to 1001, the main system clock oscillatio stopped and the device is operated on the subsystem clock. 33 µPD75P336 µPD75P336 PD75304B A/D CONVERTER CHARACTERISTICS PARAMETER (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V) SYMBOL TEST CONDITION Resolution 2.5 V ≤ AVREF ≤ V DD AVREF ≥ 0.6 VDD Absolute MIN. TYP. MAX. UNIT 8 8 8 bit –10 ≤ Ta ≤ + 85 oC ±1.5 –40 ≤ Ta < –10 oC ±2.0 –10 ≤ Ta ≤ + 85 oC accuracy*1 2.5 V ≤ AVREF ≤ V DD AVREF < 0.6 VDD ±1.5 tCY ≥ 1.91 µs –40 ≤ Ta ≤ – 10 oC LSB ±2.0 –40 ≤ tCY < 1.91 µs Ta ≤ + 85 oC ±3.0 Conversion time tCONV *2 168/fx s Sampling time tSAMP *3 44x s Analog input voltage V IAN AVREF V Analog input impedance R AN 1000 AVREF current I REF 1.0 * AVSS 2.0 1. Absolute accuracy excluding quantization (±1/2LSB) error. 2. Time up to end of conversion (EOC = 1) after execution of the conversion start instruction. (40.1 µs: fx = 4.19 MHz operation) 3. Time up to end of sampling after execution of the conversion start instruction. (10.5 µs: fx = 4.19 MHz operation) 34 MΩ mA µPD75P336 µPD75P336 PD75304B AC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) PARAMETER CPU clock cycle time (minimum instruction execution time = 1 machine cycle)*1 TI0, 1 input frequency TI0, 1 input high/ low level width Interrupt input high/ low level width RESET low level width * 1. SYMBOL tCY TEST CONDITIONS Operated by main system clock VDD = 4.5 to 6.0 V Operated by subsystem clock fTI tTIH, TYP. MAX. UNIT 0.95 64 µs 3.8 64 µs 125 µs 0 1 MHz 0 275 kHz 114 VDD = 4.5 to 6.0 V 122 0.48 µs 1.8 µs INT0 *2 µs INT1, 2, 4 10 µs KR0 to KR7 10 µs 10 µs VDD = 4.5 to 6.0 V tTIL tINTH, tINTL tRSL tcy vs VDD (Operating on Main System Clock) The CPU clock (Φ) cycle time is determined by the oscillator frequency of the connected resonator and the system clock control register (SCC) and the processor clock control register (PCC). The figure below shows the main system clock operation power supply voltage VDD vs cycle time tCY characteristics. Becomes 2tCY or 128/fX depending on the interrupt mode register (IM0) setting. 70 64 30 6 5 Operating Guaranteed Range 4 Cycle Time tcy [µ s] 2. MIN. 3 2 1 0.5 0 1 2 3 4 5 6 Supply Voltage VDD [V] 35 µPD75P336 µPD75P336 PD75304B SERIAL TRANSFER OPERATION 2-wired and 3-wired serial I/O modes (SCK ... Internal clock output) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time TYP. MAX. UNIT 1600 ns 3800 ns tKCY1 /2-50 ns tKCY1 /2-150 ns tKCY1 tKL1 SCK high/low level width MIN. VDD = 4.5 to 6.0 V tKH1 SI setup time (to SCK↑) tSIK1 150 ns SI hold time (from SCK↑) tKSI1 400 ns SO output delay time from SCK↓ tKSO1 RL = 1 kΩ , CL = 100 pF* VDD = 4.5 to 6.0 V 250 ns 1000 ns MAX. UNIT 2-wired and 3-wired serial I/O modes (SCK ... External clock input) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time MIN. TYP. 800 ns 3200 ns 400 ns 1600 ns tKCY2 VDD = 4.5 to 6.0 V SCK high/low level width tKL2 tKH2 SI setup time (to SCK↑) tSIK2 100 ns SI hold time (from SCK ↑) tKSI2 400 ns SO output delay time from SCK↓ * 36 tKSO2 RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V RL and CL are the SO output line load resistance and load capacitance, respectively. 300 ns 1000 ns µPD75P336 µPD75P336 PD75304B SBI mode (SCK ... Internal clock output (master)) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V TYP. MAX. UNIT 1600 ns 3800 ns tKCY3 /2-50 ns tKH3 tKCY3 /2-150 ns SB0,1 setup time (to SCK↑) tSIK3 150 ns SB0,1 hold time (from SCK↑) tKSI3 tKCY3/2 ns SCK cycle time tKCY3 tKL3 SCK high/low level width SB0,1 output delay time from SCK↓ * MIN. tKSO3 VDD = 4.5 to 6.0 V RL = 1 kΩ , CL = 100 pF* VDD = 4.5 to 6.0 V 0 250 ns 0 1000 ns SB0,1 ↓ from SCK↑ tKSB tKCY3 ns SCK from SB0, 1 ↓ tSBK tKCY3 ns SB0,1 low level width tSBL tKCY3 ns SB0,1 high level width tSBH tKCY3 ns RL and CL are the SB0 and SB1 output line load resistance and load capacitance, respectively. 37 µPD75P336 µPD75P336 PD75304B SBI mode (SCK ... External clock input (slave)) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY4 tKL4 SCK high/low level width t KH4 MAX. UNIT 800 ns 3200 ns 400 ns 1600 ns tSIK4 100 ns SB0,1 hold time (from SCK↑) tKSI4 tKCY4/2 ns delay time from SCK↓ 38 TYP. SB0,1 setup time (to SCK↑) SB0,1 output * VDD = 4.5 to 6.0 V MIN. tKSO4 RL = 1 kΩ , CL = 100 pF* VDD = 4.5 to 6.0 V 0 300 ns 0 1000 ns SB0,1 ↓ from SCK↑ tKSB tKCY4 ns SCK↓ from SB0, 1 ↓ tSBK tKCY4 ns SB0,1 low level width tSBL tKCY4 ns SB0,1 high level width tSBH tKCY4 ns RL and CL are the SB0 and SB1 output line load resistance and load capacitance, respectively. µPD75P336 µPD75P336 PD75304B AC Timing Test Point(Exculuding X1 and XT1 Inputs) 0.8 VDD 0.8 VDD Test Points 0.2 VDD 0.2 VDD Clock Timings 1/fX tXL tXH VDD -0.5 V 0.4 V X1 Input 1/fXT tXTL tXTH VDD -0.5 V 0.4 V XT1 Input TI0 Timing 1/fTI tTIL tTIH TI0 39 µPD75P336 µPD75P336 PD75304B Serial Transfer Timing 3-wired serial I/O mode: tKCY1 tKL1 tKH1 SCK tSIK1 tKSI1 Input Data SI tKSO1 SO Output Data 2-wired serial I/O mode: tKCY2 tKL2 tKH2 SCK tSIK2 SB0,1 tKSO2 40 tKSI2 µPD75P336 µPD75P336 PD75304B Serial Transfer Timing Bus release signal transfer: tKL3,4 tKCY3,4 tKH3,4 SCK tKSB tSBL tSBH tSIK3,4 tSBK tKSI3,4 SB0,1 tKSO3,4 Command signal transfer: tKL3,4 tKCY3,4 tKH3,4 SCK tKSB tSIK3,4 tSBK tKSI3,4 SB0,1 tKSO3,4 Interrupt Input Timing tINTL tINTH INT0,1,2,4 KR0-7 RESET Input Timing tRSL RESET 41 µPD75P336 µPD75P336 PD75304B DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DAT RETENTION CHARACTERISTICS (Ta = –40 to 85 °C) PARAMETER SYMBOL Data retention supply voltage VDDDR Data retention supply current*1 IDDDR Release signal set time tSREL Oscillation stabilization wait time*2 tWAIT * TEST CONDITIONS MIN. TYP. 2.0 VDDDR = 2.0 V 0.1 Release by interrupt request UNIT 6.0 V 10 µA µs 0 Release by RESET MAX. 217/fx ms *3 ms 1. Current flng in the built-in pull-up resistor is not included. 2. The oscillation stabilization wait time is the time CPU operation is stopped to prevent unstable operation at start of oscillation. 3. Depends on the basic interval timer mode register (BTM) setting (table below). 42 BTM3 BTM2 BTM1 BTM0 Waite Time (Figures in parentheses are for operation at fxx = 4.19 MHz) — 0 0 0 220/fxx (approx. 250 ms) — 0 1 1 217/fxx (approx. 31.3 ms) — 1 0 1 215/fxx (approx. 7.82 ms) — 1 1 1 213/fxx (approx. 1.95 ms) µPD75P336 µPD75P336 PD75304B Data Retention Timing (STOP Mode Release by RESET) Internal Reset Operation HALT Mode STOP Mode Operating Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) HALT Mode STOP Mode Operating Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT 43 µPD75P336 µPD75P336 PD75304B D/C PROGRAMING CHARACTERISTICS (Ta = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT VIH1 Except X1, X2 0.7VDD VDD V VIH2 X1, X2 VDD -0.5 VDD V VIL1 Except X1, X2 0 0.3VDD V VIL2 X1, X2 0 0.4 V Input leakage current VL1 VIN = VIL or VIH 10 µA Output voltage high VOH IOH = –1 mA Output voltage low VOL IOL = 1.6 mA VDD power supply current IDD VPP power supply current IPP Input voltage high Input voltage low * 1. 2. VDD -1.0 V 0.4 MD0 = VIL , MD1 = VIH V 30 mA 30 mA VPP must not exceed +13.5 V including overshoot. VDD should be applied before VPP and cut after VPP. A/D PROGRAMING CHARACTERISTICS (Ta = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V) (1/2) PARAMETER UNIT *1 Address setup time *2 (to MD0↓) tAS tAS MD1 setup time (to MD0↓) tMIS tOES Data setup time (to MD0↓) tDS tDS 2 µs Address hold time *2 (from MD0↑) tAH tAH 2 µs Data hold time (from MD0↑) tDH tDH 2 µs Data output float delay time from MD0↑ tDF tDF 0 VPP setup time (to MD3↑) tVPS tVPS 2 µs VDD setup time (to MD3↑) tVDS tVCS 2 µs Initial program pulse width tPW tPW 0.95 TEST CONDITION MIN. TYP. MAX. SYMBOL µs 2 µs 2 130 1.0 1.05 µs ms * 1. Symbol of the corresponding µ PD27C256. 2. The internal address signal is incremented (+1) at the rising edge of the forth X1 input. The signal is not connected to pins. 44 µPD75P336 µPD75P336 PD75304B A/D PROGRAMING CHARACTERISTICS (Ta = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V) (2/2) PARAMETER SYMBOL *1 Additional program pulse width tOPW tOPW 0.95 MD0 setup time (to MD1↑) tMOS tCES 2 Data output delay time from MD0↓ tDV tDV MD1 hold time (from MD0↑) tM1H tOEH MD1 recover time (from MD0↓) tM1R Program conuter reset time X1 input TYP. MAX. 21.0 ms µs 1 MD0 = MD1 = VIL UNIT µs 2 µs tOR 2 µs tPCR 10 µs tXH, tXL 0.125 µs fx tI 2 µs MD3 setup time (to MD1↑) tM3S 2 µs MD3 hold time (to MD1↓) tM3H 2 µs MD3 setup time (to MD0 ↓) tM3SR Program memory read 2 µs Data output delay time from address *2 tDAD tACC Program memory read Data output hold time from address *2 t HAD tOH Program memory read 0 tM3HR Program memory read 2 tDFR Program memory read Initial mode set time MD3 hold time (from MD0↑) Data output float delay time from MD3 ↓ * MIN. tM1H + t M1R ≥ 50 µs high/low width X1 input frequency TEST CONDITION 4.19 MHz 2 µs 130 µs µs 2 µs 1. Symbol of the corresponding µPD27C256. 2. The internal address signal is incremented (+1) at the rising edge of the fourth X1 input. The signal is not connected to pins. 45 µPD75P336 µPD75P336 PD75304B Program Memory Write Timing mode: ≈ VDD ≈ tVDS VDD + 1 ≈ VPP ≈ tVPS VPP tXH VDD VDD Data Output tDS tOH tDV tDF ≈ Data Input tDH tDS tAH ≈ tI tXL Data Input ≈ Data Input tAS ≈ P40-P43 P50-P53 ≈ ≈ X1 MD0 tPW tM0S tOPW ≈ ≈ tM1R MD1 tM1H ≈ tM1S ≈ tPCR MD2 tM3H ≈ ≈ tM3S MD3 Program Memory Read Timing mode: tVPS VPP ≈ VPP VDD tVDS VDD ≈ VDD + 1 VDD tXH ≈ X1 tXL tDAD P40-P43 P50-P53 Data Output ≈ Data Output ≈ tHAD tDV tI ≈ MD0 tDFR tM3HR ≈ MD1 ≈ tPCR MD2 ≈ tM3SR MD3 46 µPD75P336 ★ 6. PACKAGE INFORMATION 80 PIN PLASTIC QFP ( 14) A B 60 61 41 40 Q 5°±5° S D C detail of lead end 21 20 F 80 1 G H I M J M P K N L S80GC-65-3B9-3 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 17.2 ± 0.4 0.677 ± 0.016 B 14.0 ± 0.2 0.551+0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.2 ± 0.4 0.677 ± 0.016 F 0.8 0.031 G 0.8 0.031 H 0.30 ± 0.10 0.012+0.004 –0.005 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.6 ± 0.2 0.063 ± 0.008 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.1 ± 0.1 0.004 ± 0.004 S 3.0 MAX. 0.119 MAX. 47 µPD75P336 80 PIN PLASTIC TQFP (FINE PITCH) ( 12) A B 60 41 61 40 21 F 80 1 20 H I M J K M P G R Q S D C detail of lead end N L NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 14.0±0.2 INCHES 0.551 +0.009 –0.008 B 12.0±0.2 0.472 +0.009 –0.008 C 12.0±0.2 0.472 +0.009 –0.008 D 14.0±0.2 0.551 +0.009 –0.008 F 1.25 G 1.25 H 0.22 +0.05 –0.04 0.049 0.049 0.009±0.002 I 0.10 J 0.5 (T.P.) K 1.0±0.2 0.039 +0.009 –0.008 L 0.5±0.2 0.020 +0.008 –0.009 M 0.145 +0.055 –0.045 0.006±0.002 N 0.10 P 1.05 Q 0.05±0.05 R 5°±5° S 1.27 MAX. 0.004 0.020 (T.P.) 0.004 0.041 0.002±0.002 5°±5° 0.050 MAX. P80GK-50-BE9-4 48 µPD75P336 ★ 7. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions in the table below. For detail of recommended soldering conditions, refer to the information document "Surface Mount Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended below, contact our salesman. Table 7-1 Soldering Conditions (1) µPD75P336GC-3B9 : 80-pin plastic QFP ( 14mm) Solderring Method Solderring Conditions Recommended Condition Symbol Wave soldering Solder bath temperature: 260 °C. max., Duration: 10 sec. max., Number of times: Once, Time limit: 2 days* (thereafter 20 hours prebaking required at 125 °C) Preheat temperature: 120 °C max. (package surface temperature) WS60-202-1 Infrared reflow Package Peak temperature: 230 °C, Duration: 30 sec. max., (at 210 °C or above), Number of times: Once, Time limit: 2 days* (thereafter 20 hours prebaking required at 125 °C) IR30-202-1 VPS reflow Package Peak temperature: 215 °C, Duration: 40 sec. max., (at 200 °C or above), Number of times: Once, Time limit: 2 days* (thereafter 20 hours prebaking required at 125 °C) VP15-202-1 Pin part heating Pin part temperature: 300 °C or below, Duration: 3 sec. max. (per device side) (2) µPD75P336GK-BE9 : 80-pin plastic TQFP (fine pitch) ( 12mm) Solderring Method * Solderring Conditions Recommended Condition Symbol Infrared reflow Package Peak temperature: 235 °C, Duration: 30 sec. max., (at 210 °C or above), Number of times: Once, Time limit: 1 day* (thereafter 10 hours prebaking required at 125 °C) IR35-101-1 VPS reflow Package Peak temperature: 215 °C, Duration: 40 sec. max., (at 200 °C or above), Number of times: Once, Time limit: 1 day* (thereafter 10 hours prebaking required at 125 °C) VP15-101-1 Pin part heating Pin part temperature: 300 °C or below, Duration: 3 sec. max. (per device side) For the storage period after dry-pack decapsulation, storage conditions are max. 25 °C, 65 % RH. Note Use of more than one soldering method should be avoided (except in the case of pin part heating). 49 µPD75P336 µPD75P336 µPD75304B PD75304B APPENDIX A. LIST OF FUNCTIONS Name µPD75P336 µPD75336 Item CPU core 75X-Standard 75X-High End ROM (bytes) 16256 (mask ROM) RAM ( × 4 bits) General registers Instruction cycle µPD75328 768 512 4 bits × 8 × 4 banks 4 bits × 8 × 1 bank 0.95 µs, 1.91 µs, 3.81 µs, 15.3 µs (at 4.19 MHz operation) Main system clock 8064 (mask ROM) 16256 (PROM) 0.95 µs, 1.91 µs, 15.3 µs (at 4.19 MHz operation) 122 µs (at 32.768 KHz operation) Subsystem clock CMOS input 8 Internal pull-up resistor specifiable by software CMOS input/output Input/ output ports CMOS output 20 44 Dual function as segment pins 8 (10 V withstand voltage, mask option pull-up capability) N-ch open-drain input/output LCD controller/driver 8 • • 8-bit resolution × 8-ch (successive approximation type) Low-voltage operation capability: VDD = 2.7 to 6.0 V • 8-bit resolution × 6-ch (successive approximation type) • Low-voltage operation capability: VDD = 3.5 to 6.0 V • Basic interval timer × 1 • Timer/event counter × 1 • Watch timer × 1 Timer/counter • Basic interval timer × 1 • Timer/event counter × 2 • Watch timer × 1 Serial Interface • NEC standard serial interface (SBI) • Clocked serial interface Vectored interrupt External: 3 Internal: 4 External: 3 Internal: 3 Test input External: 1 Internal: 1 External: 1 Internal: 1 Clock output (PCL) Φ, 524kHz, 262kHz, 65.5kHz (at 4.19MHz operation) Buzzer output (BUZ) 2kHz, 4kHz, 32kHz 2kHz 8-bit data processing Transfer, addition/subtraction, increment/decrement, comparison Transfer Operating voltage Package On-chip PROM product 50 8 (10 V, withstand voltage mask option pull-up capability) Max.20 × 4 segment drive, variable duty: static, 1/2, 1/3, 1/4 A/D converter ★ Same as at left (but no pull-up resistor) VDD = 2.7 - 6.0 V 80-pin plastic QFP ( 14 mm) 80-pin plastic TQFP (fine pitch) ( µPD75P336 12mm) — µPD75P328 µPD75P336 µµµPD75P336 PD75P336 PD75304B PD75304B APPENDIX B. DEVELOPMENT TOOLS The following support tools are available for system development using the µPD75P336. Language Processor Host Machine RA75X relocatable assembler PC-9800 series IBM PC/AT Remarks OS MS-DOS™ Ver. 3.30 to Ver. 5.00A* PC DOS™ (Ver. 3.1) Supply Medium Ordering Code (Product Name) 3.5-inch 2HD µS5A13RA75X 5-inch 2HD µS5A10RA75X 5-inch 2HC µS7B10RA75X Assembler operation is only guaranteed for the host machines and operating systems quoted above. Hardware PROM Write Tools PG-1500 PROM programmer which enables a single-chip microcomputer with on-chip PROM to be programmed in stand-alone mode or by operations from a host machine by connection of the supplied board and a separately available programmer adapter. Typical PROMs from 256K bits to 4M bits can also be programmed. PA-75P328GC PROM programmer adapter for the µPD75P336GC, used connected to the PG-1500. PA-75P336GK PROM program adapter for the µPD75P336GK, used connect to the PG-1500. Software Controls the PG-1500 on the host machine, with the PG-1500 and host machine connected via a serial or parallel interface. Host Machine PG-1500 controller PC-9800 series IBM PC/AT * OS MS-DOS Ver. 3.30 to Ver. 5.00A* PC DOS (Ver. 3.1) Supply Medium Ordering Code (Product Name) 3.5-inch 2HD µS5A13PG1500 5-inch 2HD µS5A10PG1500 5-inch 2HC µS7B10PG1500 ★ ★ The task-swap function is provided with Ver.5.00/5.00A, but the function cannot be used with this software. Remarks PG-1500 controller operation is only guaranteed for the host machines and operating systems quoted above. 51 µPD75P336 µPD75P336 µPD75304B PD75304B Debugging Tools IE-75000-R*1 Hardware IE-75000-R-EM IE-75001-R EP-75338GC-R EV-9200G-80 EP-75336GK-R The IE-75000-R is an in-circuit emulator which corresponds to the 75X series. For µPD75P336 development the IE-75000-R is used in conjunction with an emulation probe. Efficient debugging is possible by connection to a host machine and PROM programmer. Emulation board for the IE-75000-R and IE-75001-R. Incorporated in the IE-75000-R. Used in conjunction with the IE-75000-R or IE-75001-R to perform µPD75P336 evaluation. The IE-75001-R is an in-circuit emulator which corresponds to 75X series. For µPD75P336 development the IE-75001-R is used in conjunction with an emulation board IE-75000-R-EM*2 and emulation probe. Efficient debugging is possible by connection to a host machine and PROM programer. Emulation probe for µPD75P336GC. Used connect with the IE-75000-R or IE-75001-R, IE-75000-REM. An 80-pin LCC socket (EV-9200GC-80) is also available to simplify connection to the user system. Emulation probe for µPD75336GK. Used connected with the IE-75000-R or IE-75001-R, IE-75000-REM. An 80-pin conversion adapter (EV-9500GK-80 is also available to simplify connection to the user system. EV-9500GK-80 Connects the IE-75000-R or IE-75001-R to the host machine via by RS-232-C and contronix I/F and controls the IE-75000-R or IE-75001-R on the host machine. Software Host Machine IE control program PC-9800 series IBM PC/AT PC DOS (Ver. 3.1) Ordering Code (Product Name) 3.5-inch 2HD µS5A13IE75X 5-inch 2HD µS5A10IE75X 5-inch 2HC µS7B10IE75X Maintenance product IE-75000-R-EM sold sparately 3. The task-swap function is provided with Ver.5.00/5.00A, but the function cannot be used with this software. Remarks 52 MS-DOS Ver. 3.30 to Ver. 5.00A*3 Supply Medium 2. * 1. ★ OS Operations of the IE control program is only guaranteed for the host machines and operating systems quoted above. Development Tools Configuration ★ In-Circuit Emulator IE-75000-R IE-75001-R*1 Centronics I/F RS-232-C Host Machine PC-9800 Series IBM PC/AT (Symbolic Debugging Possible) Emulation Probe EP-75336GC-R EP-75336GK-R IE-75000-R-EM IE Control Program *2 User System PG-1500 Controller Pruducts Incorporating PROM µPD75P336GC µPD75P336GK PROM Programmer PG-1500 Relocatable Assembler + Programmer Adapter * 1. The IE-75001-R does not incorporate the IE-75000-R-EM (Available separately.) PA-75P328GC PA-75P336GK 2. EV-9200GC-80 EV-9500GK-80 µPD75P336 µPD75P336 PD75P336 PD75304B µPD75304B 53 µPD75P336 µPD75P336 µPD75304B PD75304B 54 µPD75P336 µµµPD75P336 PD75P336 PD75304B PD75304B 55 µPD75P336 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Special : Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 MS-DOS is a trademark of MicroSoft Corporation. PC DOS and PC/AT is a trademark of IBM Corporation.