DATA SHEET MOS INTEGRATED CIRCUIT µPD78P083 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD78P083 is a member of the µPD78083 subseries of the 78K/0 series products. It includes an on-chip, 24-Kbyte, one-time PROM or EPROM. Because this device can be programmed by users, it is ideally suited for applications involving the evaluation of systems in development stages, small-scale production of many different products, and rapid development and time-to-market of a new product. Caution The µPD78P083DU does not maintain planned reliability when used in your systems’ mass-produced products. Please use only experimentally or for evaluation purposes during trial manufacture. The details of functions are described in the user’s manuals. Be sure to read the following manuals before designing. µPD78083 Subseries User's Manual 78K/0 Series User's Manual — Instructions : IEU-1407 : IEU-1372 FEATURES • Pin-compatible with mask ROM version (except VPP pin) • Internal PROM: 24 Kbytes Note • µPD78P083DU: Reprogrammable (ideally suited for system evaluation) • µPD78P083CU, µPD78P083GB: One-time programmable (ideally suited for small-scale production) • Internal high-speed RAM: 512 bytes Note • Can be operated in the same supply voltage as the mask ROM version (VDD = 1.8 to 5.5 V) • Corresponding to QTOPTM Microcontrollers Note The internal PROM and internal high-speed RAM capacities can be changed by setting the internal memory size switching register (IMS). Remark QTOP microcontroller is a general term for microcontrollers which incorporate one-time PROM and are totally supported by NEC's programming service (from programming to marking, screening and verification). * Differs from the mask ROM version in the following points The same memory mapping as the mask ROM version is enabled by setting the internal memory size switching register (IMS). In this document, the term PROM is used in parts common to one-time PROM versions and EPROM versions. The information in this document is subject to change without notice. Document No. U11006EJ1V0DS00 (1st edition) (Previous No. IP-3556) Date Published June 1996 P Printed in Japan The mark * shows major revised points. © 1995 µPD78P083 ORDERING INFORMATION Part Number * µPD78P083CU µPD78P083GB-3B4 µPD78P083GB-3BS-MTX µPD78P083DU Package 42-pin 44-pin 44-pin 42-pin plastic shrink DIP (600 mil) plastic QFP (10 x 10 mm) plastic QFP (10 x 10 mm) ceramic shrink DIP Internal ROM One-Time PROM One-Time PROM One-Time PROM EPROM (with window) (600 mil) Caution µPD78P083GB has two kinds of package. (Refer to 9. PACKAGE DRAWINGS). Please refer an NEC’s sales representative for the available package. QUALITY GRADE Part Number Package Quality Grades µPD78P083CU µPD78P083GB-3B4 42-pin plastic shrink DIP (600 mil) 44-pin plastic QFP (10 x 10 mm) Standard Standard µPD78P083GB-3BS-MTX µPD78P083DU 44-pin plastic QFP (10 x 10 mm) 42-pin ceramic shrink DIP (with window) (600 mil) Standard Not applicable Please refer to “Quality grades on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 2 µPD78P083 78K/0 SERIES DEVELOPMENT The following shows the 78K/0 series products development. Subseries names are shown inside frames. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control A timer was added to the µPD78054 and external interface function was enhanced 100-pin µPD78078 µPD78078Y 100-pin µPD78070A µPD78070AY ROM-less versions of the µPD78078 80-pin µPD78058F µPD78058FY EMI noise reduced product of the µPD78054 80-pin µPD78054 µPD78054Y 64-pin µPD78018F µPD78018FY 64-pin µPD78014 µPD78014Y 64-pin µPD780001 64-pin µPD78002 42/44-pin µPD78083 UART and D/A converter were added to the µPD78014 and I/O was enhanced Low-voltage (1.8 V) operation versions of the µPD78014 with several ROM and RAM capacities are available. An A/D converter and 16-bit timer were added to the µPD78002 An A/D converter was added to the µPD78002 µPD78002Y Basic subseries for control On-chip UART, capable of operating at a low voltage (1.8 V) FIPTM drive 78K/0 Series 100-pin µPD780208 The I/O and FIP C/D of the µPD78044A were enhanced. Display output total: 53 80-pin µPD78044A A 6-bit U/D counter was added to the µPD78024. Display output total: 34 64-pin µPD78024 Basic subseries for driving FIP. Display output total: 26 LCD drive 100-pin µPD780308 100-pin µPD78064B 100-pin µPD78064 µPD780308Y The enhanced SIO to the µPD78064 and increased ROM and RAM capacities EMI noise reduced product of the µPD78064 µPD78064Y Subseries for driving LCDs, On-chip UART IEBusTM supported 80-pin µPD78098 The IEBus controller was added to the µPD78054 LV control 64-pin µPD78P0914 On-chip PWM, LV digital code decoder, and Hsync counter 3 µPD78P083 The following table shows the differences among subseries functions. Function Part Number Control µPD78078 ROM Timer Capacity 8-bit 16-bit Watch WDT A/D 32 K to 60 K 4ch µPD78070A 8-bit 1ch 1ch 1ch 8ch 8-bit Serial Interface D/A 2ch Expansion 3ch (UART: 1ch) 88 1.8 V Available 61 2.7 V – 69 16 K to 60 K 2.0 V µPD78018F 8 K to 60 K µPD78014 – LCD drive – 8 K to 16 K µPD780208 32 K to 60 K 2ch 1ch – 1ch 1ch – – 8ch 1ch 1ch 8ch – 1.8 V 39 – 53 Available 1ch (UART: 1ch) 33 1.8 V – 2ch 2.7 V – 3ch (UART: 1ch) 57 1.8 V – 2ch (UART: 1ch) 2.0 V 3ch (UART: 1ch) 69 2.7 V Available 2ch 4.5 V Available 74 µPD78044A 16 K to 40 K 68 µPD78024 54 24 K to 32 K µPD780308 48 K to 60 K 2ch 1ch 1ch 1ch 8ch – µPD78064B 32 K IEBus 53 2.7 V µPD78083 FIP drive 2ch 8 K to 32 K µPD780001 8 K µPD78002 VDD MIN. External Value µPD78058F 48 K to 60 K 2ch µPD78054 I/O µPD78064 16 K to 32 K µPD78098 32 K to 60 K 2ch 1ch 1ch 1ch 8ch 2ch – 1ch 8ch – supported LV control 4 µPD78P0914 32 K 6ch – 54 µPD78P083 FUNCTION DESCRIPTION Item Function Internal memory • PROM: 24 Kbytes Note • RAM Internal high-speed RAM: 512 bytes Note Memory space 64 Kbytes General register 8 bits x 32 registers (8 bits x 8 registers x 4 banks) Instruction cycles Instruction execution time variable function is integrated. 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@5.0-MHz operation with main system clock) Instruction set • 16-bit operation • Multiply/divide (8 bits x 8 bits, 16 bits ÷ 8 bits) • Bit manipulation (set, reset, test, Boolean operation) • BCD adjust, etc. I/O ports Total : 33 • CMOS input : 1 • CMOS input/output : 32 A/D converter • 8-bit resolution x 8 channels Serial interface • 3-wire serial I/O/UART mode selectable: 1 channel Timer • 8-bit timer/event counter: 2 channels • Watchdog timer: 1 channel Timer output 2 pins (8-bit PWM output enable) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, and 5.0 MHz (@ 5.0-MHz operation with main system clock) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, and 9.8 kHz (@ 5.0-MHz operation with main system clock) Vectored Maskable interrupts Internal : 8 interrupts Non-maskable interrupt Internal : 1 Software interrupt Internal : 1 Power supply voltage external : 3 VDD = 1.8 to 5.5 V Operating ambient temperature TA = –40 to +85°C Packages • 42-pin plastic shrink DIP (600 mil) • 44-pin plastic QFP (10 x 10 mm) • 42-pin ceramic shrink DIP (with window) (600 mil) Note Internal PROM and high-speed RAM capacities can be changed by setting the internal memory size switching register (IMS). 5 µPD78P083 PIN CONFIGURATIONS (Top View) (1) Normal operating mode • 42-pin plastic shrink DIP (600 mil) µPD78P083CU • 42-pin ceramic shrink DIP (with window) (600 mil) µPD78P083DU Cautions 1. 2. 3. 6 P55 1 42 VSS P56 2 41 P54 P57 3 40 P53 P30 4 39 P52 P31 5 38 P51 P32 6 37 P50 P33 7 36 P100/TI5/TO5 P34 8 35 P101/TI6/TO6 P35/PCL 9 34 P70/RXD/SI2 P36/BUZ 10 33 P71/TXD/SO2 P37 11 32 P72/ASCK/SCK2 P00 12 31 P17/ANI7 P01/INTP1 13 30 P16/ANI6 P02/INTP2 14 29 P15/ANI5 P03/INTP3 15 28 P14/ANI4 RESET 16 27 P13/ANI3 VPP 17 26 P12/ANI2 X2 18 25 P11/ANI1 P10/ANI0 X1 19 24 VDD 20 23 AVSS AVDD 21 22 AVREF Connect VPP pin directly to V SS. Connect AVDD pin to VDD. Connect AVSS pin to VSS. µPD78P083 NC RESET VPP X2 X1 VDD AVDD AVREF AVSS P12/ANI2 1 44 43 42 41 40 39 38 37 36 35 34 33 P03/INTP3 P13/ANI3 2 32 P02/INTP2 P14/ANI4 3 31 P01/INTP1 P15/ANI5 4 30 P00 P16/ANI6 5 29 P37 P33 P101/TI6/TO6 10 24 P32 P100/TI5/TO5 11 23 12 13 14 15 16 17 18 19 20 21 22 Connect Connect Connect Connect NC P31 P30 P34 25 P57 26 9 P56 8 P70/RXD/SI2 P55 P71/TXD/SO2 VSS P35/PCL P54 P36/BUZ 27 P53 28 7 P52 6 P51 P17/ANI7 P72/ASCK/SCK2 P50 Cautions 1. 2. 3. 4. P10/ANI0 P11/ANI1 • 44-pin plastic QFP (10 x 10 mm) µPD78P083GB-3B4, µPD78P083GB-3BS-MTX VPP pin directly to V SS. AVDD pin to VDD. AVSS pin to VSS. NC pin to VSS for noise protection (It can be left open). 7 µPD78P083 P00 to P03 P10 to P17 : Port 0 : Port 1 PCL BUZ : Programmable Clock : Buzzer Clock P30 to P37 P50 to P57 P70 to P72 P100, P101 : : : : Port Port Port Port X1, X2 RESET ANI0-ANI7 AV DD : : : : Crystal (Main System Clock) Reset Analog Input Analog Power Supply INTP1 to INTP3 TI5, TI6 TO5, TO6 SI2 : : : : Interrupt from Peripherals Timer Input Timer Output Serial Input AV SS AV REF VDD VPP : : : : Analog Ground Analog Reference Voltage Power Supply Programming Power Supply SO2 SCK2 RxD TxD : : : : Serial Output Serial Clock Receive Data Transmit Data VSS NC : Ground : Non-connection ASCK : Asynchronous Serial Clock 8 3 5 7 10 µPD78P083 (2) PROM programming mode • 42-pin plastic shrink DIP (600 mil) µPD78P083CU • 42-pin ceramic shrink DIP (with window) (600 mil) µPD78P083DU Cautions 1. 2. 3. 4. (L): A5 1 42 VSS A6 2 41 A4 A7 3 40 A3 OE 4 39 A2 CE 5 38 A1 PGM 6 37 A0 A8 7 36 A10 (L) 8 35 A11 9 34 A12 10 33 A13 11 32 A14 A9 12 31 D7 (L) 13 30 D6 14 29 D5 15 28 D4 RESET 16 27 D3 VPP 17 26 D2 Open 18 25 D1 (L) 19 24 D0 VDD 20 23 VSS VDD 21 22 VSS Individually connect to VSS via a pull-down resistor. VSS: Connect to GND. RESET: Set to low level. Open: Leave open. 9 µPD78P083 10 RESET (L) VPP Open VDD (L) VDD VSS D6 5 29 D7 6 28 A14 7 27 A13 8 26 A12 9 25 A8 A11 10 24 PGM A10 11 23 12 13 14 15 16 17 18 19 20 21 22 (L) (L) (L) CE OE A9 A7 30 A6 31 4 A5 3 D5 VSS D4 A4 32 4. VSS 2 A3 D3 A2 44 43 42 41 40 39 38 37 36 35 34 33 A1 1 A0 D2 Cautions 1. 2. 3. D0 D1 • 44-pin plastic QFP (10 x 10 mm) µPD78P083GB-3B4, µPD78P083GB-3BS-MTX (L): Individually connect to VSS via a pull-down resistor. VSS: Connect to GND. RESET: Set to low level. Open: Leave open. A0 to A14 D0 to D7 CE : Address Bus : Data Bus : Chip Enable RESET VDD VPP : Reset : Power Supply : Programming Power Supply OE PGM : Output Enable : Program VSS : Ground µPD78P083 BLOCK DIAGRAM P00 P100/TI5/TO5 8-bit TIMER/ EVENT COUNTER 5 PORT 0 P101/TI6/TO6 8-bit TIMER/ EVENT COUNTER 6 PORT 1 P10-P17 PORT 3 P30-P37 PORT 5 P50-P57 PORT 7 P70-P72 PORT 10 P100, P101 WATCHDOG TIMER SI2/RXD/P70 SO2/TXD/P71 SCK2/ASCK/P72 SERIAL INTERFACE 2 ANI0/P10ANI7/P17 AVDD AVSS AVREF A/D CONVERTER INTP1/P01INTP3/P03 INTERRUPT CONTROL BUZ/P36 78K/0 CPU CORE PROM (24 KBytes) DATA MEMORY (512 Bytes) BUZZER OUTPUT RESET SYSTEM CONTROL PCL/P35 CLOCK OUTPUT CONTROL P01-P03 VDD VSS VPP X1 X2 11 µPD78P083 CONTENTS 1. DIFFERENCES BETWEEN THE µPD78P083 AND MASK ROM VERSIONS ··· 13 2. PIN FUNCTIONS ··· 14 2.1 Pins in Normal Operating Mode ··· 14 2.2 2.3 Pins in PROM Programming Mode ··· 16 Pin Input/Output Circuits and Recommended Connection of Unused Pins ··· 16 3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ··· 18 4. PROM PROGRAMMING ··· 19 4.1 4.2 4.3 * * Operating Modes ··· 19 PROM Write Procedure ··· 21 PROM Read Procedure ··· 25 5. PROGRAM ERASURE (µPD78P083DU ONLY) ··· 26 6. OPAQUE FILM ON ERASURE WINDOW (µPD78P083DU ONLY) ··· 26 7. ONE-TIME PROM VERSION SCREENING ··· 26 8. ELECTRICAL SPECIFICATIONS ··· 27 9. PACKAGE DRAWINGS ··· 45 10. RECOMMENDED SOLDERING CONDITIONS ··· 49 APPENDIX A. DEVELOPMENT TOOLS ··· 50 APPENDIX B. RELATED DOCUMENTS ··· 52 12 µPD78P083 1. DIFFERENCES BETWEEN THE µPD78P083 AND MASK ROM VERSIONS The µPD78P083 is a single-chip microcontroller with an on-chip one-time PROM or with an on-chip EPROM which has program write, erasure and rewrite capability. Setting the internal memory size switching register (IMS) makes the functions except the PROM specification identical to the mask ROM versions, that is, the µPD78081 and µPD78082. Differences between the µPD78P083 and mask ROM versions are shown in Table 1-1. Table 1-1. Differences between the µPD78P083 and Mask ROM Versions µPD78P083 Parameter Mask ROM Versions ROM type One-time PROM/EPROM Mask ROM ROM capacity 24 Kbytes µPD78081 : 8 Kbytes µPD78082 : 16 Kbytes µPD78081 : 256 bytes µPD78082 : 384 bytes Internal high-speed RAM capacity Internal ROM and internal high-speed 512 bytes Can be changed Note Can not be changed RAM capacity change by internal memory size switching register IC pin No Yes VPP pin Yes No Electrical specifications Refer to a data sheet of each product Note The internal PROM becomes 24 Kbytes and the internal expansion RAM becomes 512 bytes by the RESET input. 13 µPD78P083 2. PIN FUNCTIONS 2.1 Pins in Normal Operating Mode (1) Port pins Pin Name Input/Output Function After Reset P00 Input Port 0 Input only Input P01 Input/output 4-bit input/output port Input/output is specifiable Input P02 P03 Alternate Function — INTP1 bit-wise. When used as the INTP2 input port, it is possible to INTP3 connect a pull-up resistor by software. P10-P17 Input/output Port 1 Input ANI0-ANI7 8-bit input/output port Input/output is specifiable bit-wise. When used as the input port, it is possible to connect a pull-up resistor by software. P30-P34 Input/output Note Port 3 Input — P35 8-bit input/output port PCL P36 Input/output is specifiable bit-wise. BUZ P37 When used as the input port, it is possible to connect — a pull-up resistor by software. P50-P57 Input/output Port 5 Input — 8-bit input/output port Can drive up to seven LEDs directly. Input/output is specifiable bit-wise. When used as the input port, it is possible to connect a pull-up resistor by software. P70 Input/output P71 P72 Port 7 Input SI2/RxD 3-bit input/output port SO2/TxD Input/output is specifiable bit-wise. SCK2/ASCK When used as the input port, it is possible to connect a pull-up resistor by software. P100 P101 Input/output Port 10 2-bit input/output port Input TI5/TO5 TI6/TO6 Input/output is specifiable bit-wise. When used as the input port, it is possible to connect a pull-up resistor by software. Note When P10/ANI0-P17/ANI7 pins are used as the analog inputs for the A/D converter, set the port 1 to the input mode. The on-chip pull-up resistor is automatically disabled. 14 µPD78P083 (2) Non-port pins Pin Name INTP1 Input/Output Input Function External interrupt input by which the active edge (rising edge, INTP2 After Reset Alternate Function Input P01 falling edge, or both rising and falling edges) can be specified. P02 INTP3 SI2 P03 Input Serial interface serial data input. Input P70/RxD SO2 Output Serial interface serial data output. Input P71/TxD SCK2 Input/Output Serial interface serial clock input/output. Input P72/ASCK RxD Input Asynchronous serial interface serial data input. Input P70/SI2 TxD Output Asynchronous serial interface serial data output. Input P71/SO2 ASCK Input Asynchronous serial interface serial clock input. Input P72/SCK2 TI5 Input External count clock input to 8-bit timer (TM5). Input P100/TO5 P100/TI5 TI6 TO5 External count clock input to 8-bit timer (TM6). P101/TO6 Output 8-bit timer output. Input PCL Output Clock output. (for main system clock trimming) Input P35 BUZ Output Buzzer output. Input P36 Input P10-P17 TO6 P101/TI6 ANI0-ANI7 Input A/D converter analog input. AV REF Input A/D converter reference voltage input. – – – A/D converter analog power supply. Connected to VDD. – – – A/D converter ground potential. Connected to VSS. – – System reset input. – – AV DD AV SS RESET Input X1 Input Main system clock oscillation crystal connection. X2 – VDD – VPP – – – – – Positive power supply. – – High-voltage applied during program write/verification. – – Ground potential. – – Does not internally connected. Connect to VSS. – – Connected directly to VSS in normal operating mode. VSS – NC – (It can be left open) 15 µPD78P083 2.2 Pins in PROM Programming Mode Pin Name Input/Output Function RESET Input PROM programming mode setting When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, this chip is set in the PROM programming mode. VPP Input PROM programming mode setting and high-voltage applied during program write/verification. A0-A14 Input Address bus D0-D7 Input/output Data bus CE Input PROM enable input/program pulse input OE Input Read strobe input to PROM PGM Input Program/program inhibit input in PROM programming mode. VDD — Positive power supply VSS — Ground potential 2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins Types of input/output circuits of the pins and recommeded connection of unused pins are shown in Table 2-1. For the configuration of each type of input/output circuit, see Figure 2-1. Table 2-1. Type of Input/Output Circuit of Each Pin Pin Name Input/Output Input/Output Recommended Connection for Unused Pins Circuit Type P00 2 Input Connect to VSS. P01/INTP1 8-A Input/Output Independently connect to VSS via a resistor. P10/ANI0-P17/ANI7 11 Input/Output Independently connect to VDD or VSS via P30-P32 5-A P33, P34 8-A P35/PCL 5-A P02/INTP2 P03/INTP3 a resistor. P36/BUZ P37 P50-P57 5-A P70/SI2/RxD 8-A P71/SO2/TxD 5-A P72/SCK2/ASCK 8-A P100/TI5/TO5 8-A P101/TI6/TO6 RESET AVREF 16 2 Input – – – Connect to VSS. AVDD Connect to VDD. AVSS Connect to VSS. VPP Connect directly to VSS. NC Connect to VSS (can leave open) µPD78P083 Figure 2-1. Types of Pin Input/Output Circuits Type 2 Type 8-A VDD pull-up enable P-ch IN VDD data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics VDD Type 5-A pull-up enable output disable N-ch VDD Type 11 pull-up enable P-ch P-ch VDD VDD data data IN/OUT P-ch IN/OUT output disable input enable P-ch output disable N-ch P-ch N-ch Comparator + – N-ch VREF (threshold voltage) input enable 17 µPD78P083 3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) This is a register to disable use of part of internal memories by software. By setting this internal memory size switching register (IMS), it is possible to get the same memory mapping as that of the mask ROM versions with a different internal memory (ROM, RAM). IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to 46H. Figure 3-1. Internal Memory Size Switching Register Format Symbol IMS 7 6 5 4 3 2 1 0 Address After Reset R/W RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 FFF0H 46H R/W ROM3 ROM2 ROM1 ROM0 Selection of Internal ROM Capacity 0 0 1 0 8 Kbytes 0 1 0 0 16 Kbytes 0 1 1 0 24 Kbytes Other than above RAM2 RAM1 RAM0 Setting prohibited Selection of Internal High-Speed RAM Capacity 0 1 0 512 bytes 0 1 1 384 bytes 1 0 0 256 bytes Other than above Setting prohibited Table 3-1 shows the setting values of IMS which make the memory mapping the same as that of the mask ROM version. Table 3-1. Internal Memory Size Switching Register Setting Values Target Mask ROM Versions 18 IMS Setting Value µPD78081 82H µPD78082 64H µPD78P083 4. PROM PROGRAMMING The µPD78P083 has an internal 24-Kbyte PROM as a program memory. For programming, set the PROM programming mode with the VPP and RESET pins. For the connection of unused pins, refer to “PIN CONFIGURATIONS (TOP VIEW) (2) PROM programming mode.” Caution Programs must be written in addresses 0000H to 5FFFH (The last address 5FFFH must be specified). They cannot be written by a PROM programmer which cannot specify the write address. 4.1 Operating Modes When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the PROM programming mode is set. This mode will become the operating mode as shown in Table 4-1 when the CE, OE, and PGM pins are set as shown. Further, when the read mode is set, it is possible to read the contents of the PROM. Table 4-1. Operating Modes of PROM Programming Pin RESET VPP VDD CE OE PGM D0 to D7 L +12.5 V +6.5 V H L H Data input Page write H H L High-impedance Byte write L H L Data input Program verify L L H Data output Program inhibit x H H High-impedance x L L L L H Data output Output disable L H x High-impedance Standby H x x High-impedance Operating Mode Page data latch Read +5 V +5 V x : L or H 19 µPD78P083 (1) Read mode Read mode is set if CE = L, OE = L is set. (2) Output disable mode Data output becomes high-impedance, and is in the output disable mode, if OE = H is set. Therefore, it allows data to be read from any device by controlling the OE pin, if multiple µPD78P083s are connected to the data bus. (3) Standby mode Standby mode is set if CE = H is set. In this mode, data outputs become high-impedance irrespective of the OE status. (4) Page data latch mode Page data latch mode is set if CE = H, PGM = H, OE = L are set at the beginning of page write mode. In this mode, 1 page 4-byte data is latched in an internal address/data latch circuit. (5) Page write mode After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active low) to the PGM pin with CE = H, OE = H. Then, program verification can be performed, if CE = L, OE = L are set. If programming is not performed by a one-time program pulse, X times (X ≤ 10) write and verification operations should be executed repeatedly. (6) Byte write mode Byte write is executed when a 0.1-ms program pulse (active low) is applied to the PGM pin with CE = L, OE = H. Then, program verification can be performed if OE = L is set. If programming is not performed by a one-time program pulse, X times (X ≤ 10) write and verification operations should be executed repeatedly. (7) Program verify mode Program verify mode is set if CE = L, PGM = H, OE = L are set. In this mode, check if a write operation is performed correctly after the write. (8) Program inhibit mode Program inhibit mode is used when the OE pin, VPP pin, and D0-D7 pins of multiple µPD78P083s are connected in parallel and a write is performed to one of those devices. When a write operation is performed, the page write mode or byte write mode described above is used. At this time, a write is not performed to a device which has the PGM pin driven high. 20 µPD78P083 4.2 PROM Write Procedure Figure 4-1. Page Program Mode Flow Chart Start Address = G VDD = +6.5 V, VPP = +12.5 V X=0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Address = Address + 1 Latch No X=X+1 X = 10 ? 0.1-ms program pulse Verify 4 bytes Yes Fail Pass No Address = N ? Yes VDD = 4.5 to 5.5 V, VPP = VDD Pass Verify all bytes Fail All Pass Write end Defective product G = Start address N = Program last address 21 µPD78P083 Figure 4-2. Page Program Mode Timing Page Data Latch Page Program Program Verify A2-A14 A0, A1 D0-D7 Data Input VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL 22 Data Output µPD78P083 Figure 4-3. Byte Program Mode Flow Chart Start Address = G VDD = +6.5 V, VPP = +12.5 V X=0 X=X+1 No X = 10 ? 0.1-ms program pulse Yes Address = Address + 1 Fail Verify Pass No Address = N ? Yes VDD = 4.5 to 5.5 V, VPP = VDD Pass Verify all bytes Fail All Pass Write end Defective product G = Start address N = Program last address 23 µPD78P083 Figure 4-4. Byte Program Mode Timing Program Program Verify A0-A14 D0-D7 Data Input Data Output VPP VPP VDD VDD VDD + 1.5 VDD VIH CE VIL VIH PGM VIL VIH OE VIL Cautions 1. 2. 3. 24 VDD should be applied before VPP and removed after VPP. VPP must not exceed +13.5 V including overshoot. Reliability may be adversely affected if removal/reinsertion is performed while +12.5 V is being applied to VPP. µPD78P083 4.3 PROM Read Procedure The contents of PROM are readable to the external data bus (D0-D7) according to the read procedure shown below. (1) Fix the RESET pin at low level, supply +5 V to the VPP pin, and connect all other unused pins as shown in “PIN CONFIGURATIONS (TOP VIEW) (2) PROM programming mode”. (2) Supply +5 V to the VDD and VPP pins. (3) Input address of read data into the A0-A16 pins. (4) Read mode (5) Output data to D0-D7 pins. The timings of the above steps (2) to (5) are shown in Figure 4-5. Figure 4-5. PROM Read Timings A0-A14 Address Input CE (Input) OE (Input) D0-D7 Hi-Z Data Output Hi-Z 25 µPD78P083 * 5. PROGRAM ERASURE (µPD78P083DU ONLY) The µPD78P083DU is capable of erasing (FFH) the data written in a program memory and rewriting. To erase the programmed data, expose the erasure window to light having a wavelength shorter than about 400 nm. Normally, irradiate ultraviolet rays of 254-nm wavelength. The amount of exposure required to completely erase the programmed data is as follows: • UV intensity x erasing time : 30 W•s/cm2 or more • Erasure time: 40 min. or more (When a UV lamp of 12,000 µW/cm2 is used. However, a longer time may be needed because of deterioration in performance of the UV lamp, soiled erasure window, etc.) When erasing the contents of data, set up the UV lamp within 2.5 cm from the erasure window. Further, if a filter is provided for a UV lamp, irradiate the ultraviolet rays after removing the filter. 6. OPAQUE FILM ON ERASURE WINDOW (µPD78P083DU ONLY) To protect from unintentional erasure by rays other than that of the lamp for erasing EPROM contents, or to protect internal circuit other than EPROM from misoperating by rays, cover the erasure window with an opaque film when EPROM contents erasure is not performed. 7. ONE-TIME PROM VERSION SCREENING The one-time PROM version (µPD78P083CU, 78P083GB-3B4, 78P083GB-3BS-MTX) cannot be tested completely by NEC before it is shipped, because of its structure. It is recommended to perform screening to verify PROM after writing necessary data and performing high-temperature storage under the condition below. * Storage Temperature Storage Time 125°C 24 hours NEC offers for an additional fee one-time PROM writing to marking, screening, and verify for products designated as "QTOP Microcontroller". Please contact an NEC sales representative for details. 26 µPD78P083 8. ELECTRICAL SPECIFICATIONS * Absolute Maximum Ratings (T A = 25°C) Parameter Symbol Ratings Unit Supply voltage VDD –0.3 to +7.0 V VPP –0.3 to +13.5 V AVDD –0.3 to VDD + 0.3 V AVREF –0.3 to VDD + 0.3 V AVSS –0.3 to +0.3 V –0.3 to VDD + 0.3 V Input voltage Test Conditions VI1 VI2 A9 PROM programming mode –0.3 to +13.5 Analog input pins Output voltage VO Analog input voltage VAN P10-P17 –0.3 to VDD + 0.3 Output current, high IOH V V AVSS – 0.3 to AVREF + 0.3 V Per pin –10 mA Total for P10-P17, P50-P54, P70-P72, –15 mA –15 mA P100, P101 Total for P01-P03, P30-P37, P55-P57 Output current, low IOL Note Per pin Peak value 30 mA 15 mA r.m.s. value Total for P50-P54 Peak value 100 r.m.s. value Total for P55-P57 70 Peak value 100 r.m.s. value 70 mA mA mA mA Total for P10-P17, P70-P72, P100, Peak value 50 mA P101 r.m.s. value 20 mA Total for P01-P03, P30-P37 Peak value 50 mA 20 mA r.m.s. value Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Note The r.m.s. value should be calculated as follows: [r.m.s. value] = [Peak value] x Duty Caution If the absolute maximum rating of even one of the above parameters is exceeded, the quality of the product may be degraded. The absolute maximum ratings are therefore the rated values that may, if exceeded, physically damage the product. Be sure to use the product with all the absolute maximum ratings observed. Remark Unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics. 27 µPD78P083 Capacitance (TA = 25°C, VDD = VSS = 0 V) Parameter Symbol Test Conditions Input capacitance CIN f = 1 MHz, Unmeasured pins returned to 0 V. 15 pF I/O capacitance CIO f = 1 MHz, P01-P03, P10-P17, P30-P37, 15 pF Unmeasured pins P50-P57, P70-P72, P100, returned to 0 V. P101 Remark MIN. TYP. MAX. Unit Unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics. Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Resonator Recommended Parameter Test Conditions MIN. Oscillation frequency VDD = Oscillation voltage 1.0 (fX) Note 1 range Oscillation stabilization After VDD came to MIN. TYP. MAX. Unit 5.0 MHz 4 ms 5.0 MHz 10 ms Circuit Ceramic VPP X2 X1 resonator C2 C1 time Crystal VPP X2 X1 resonator C1 X2 Oscillation stabilization X1 1.0 Note 1 time External clock of oscillation voltage range Oscillation frequency (fX) C2 Note 2 VDD = 4.5 to 5.5 V Note 2 X1 input frequency 30 1.0 5.0 MHz 85 500 ns (fX) Note 1 µ PD74HCU04 X1 input high- and low-level widths (tXH, tXL) Notes 1. Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Characteristics. 2. Time required for oscillation to stabilize after a reset or the STOP mode has been released. Caution When using the oscillation circuit of the main system clock, wire the portion enclosed in broken lines in the figures as follows to avoid adverse influences on the wiring capacitance: • Keep the wiring length as short as possible. • Do not cross the wiring over other signal lines. • Do not route the wiring in the vicinity of lines through which a high fluctuating current flows. • Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VSS. • Do not connect the power source pattern through which a high current flows. • Do not extract signals from the oscillation circuit. 28 µPD78P083 DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Input voltage, high Symbol VIH1 Test Conditions P10-P17, P30-P32, V DD = 2.7 to 5.5 V MAX. Unit 0.7VDD MIN. TYP. VDD V 0.8VDD VDD V 0.8VDD VDD V 0.85VDD VDD V VDD–0.5 VDD V P35-P37, P50-P57, P71 VIH2 P00-P03, P33, P34, V DD = 2.7 to 5.5 V P70, P72, P100, P101, RESET VIH3 X1, X2 V DD = 2.7 to 5.5 V VIL1 P10-P17, P30-P32, V DD = 2.7 to 5.5 V VDD–0.2 Input voltage, low VDD V 0 0.3V DD V 0 0.2V DD V 0 0.2V DD V 0 0.15VDD V 0 0.4 V 0 0.2 V P35-P37, P50-P57, P71 VIL2 P00-P03, P33, P34, V DD = 2.7 to 5.5 V P70, P72, P100, P101, RESET Output voltage, high Output voltage, low VIL3 X1, X2 VOH V DD = 4.5 to 5.5 V, IOH = –1 mA VDD–1.0 V IOH = –100 µA VDD–0.5 V VOL P50-P57 V DD = 2.7 to 5.5 V V DD = 2.0 to 4.5 V, 0.8 V 2.0 V 0.4 V IOL = 10 mA V DD = 4.5 to 5.5 V, 0.4 IOL = 15 mA P01-P03, P10-P17, Input-leak current, high ILIH1 V DD = 4.5 to 5.5 V, P30-P37, P70-P72, IOL = 1.6 mA P100, P101 IOL = 400 µA V IN = VDD P00-P03, P10-P17, 0.5 V 3 µA P30-P37, P50-P57, P70-P72, P100, P101, RESET ILIH2 Input-leak current, low ILIL1 V IN = 0 V X1, X2 20 µA P00-P03, P10-P17, –3 µA P30-P37, P50-P57, P70-P72, P100, P101, RESET –20 µA Output leak current, high ILOH V OUT = V DD 3 µA Output leak current, low ILOL V OUT = 0 V –3 µA Software pull-up resistor R V IN = 0 V 90 kΩ ILIL2 X1, X2 P01-P03, P10-P17, 15 40 P30-P37, P50-P57, P70-P72, P100, P101 Remark Unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics. 29 µPD78P083 DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Supply current Note 1 Symbol IDD1 Test Conditions MAX. Unit 5.4 16.2 mA Note 4 oscillation operating V DD = 3.0 V ± 10% Note 5 0.8 2.4 mA mode (fXX = 2.5 MHz) Note 2 V DD = 2.0 V ± 10% Note 5 0.45 1.35 mA 5.0-MHz crystal oscil- V DD = 5.0 V ± 10% Note 4 9.5 28.5 mA lation operating mode V DD = 3.0 V ± 10% Note 5 1.0 3.0 mA Note 3 5.0-MHz crystal oscil- V DD = 5.0 V ± 10% 1.4 4.2 mA lation HALT mode V DD = 3.0 V ± 10% 0.5 1.5 mA V DD = 2.0 V ± 10% 280 840 µA (fXX = 2.5 MHz) Note 2 5.0-MHz crystal oscil- V DD = 5.0 V ± 10% 1.6 4.8 mA lation HALT mode V DD = 3.0 V ± 10% 0.65 1.95 mA (fXX = 5.0 MHz) IDD3 TYP. V DD = 5.0 V ± 10% (fXX = 5.0 MHz) IDD2 MIN. 5.0-MHz crystal Note 3 STOP mode V DD = 5.0 V ± 10% 0.1 30 µA V DD = 3.0 V ± 10% 0.05 10 µA V DD = 2.0 V ± 10% 0.05 10 µA Notes 1. Not including AVREF, AVDD currents or port currents (including current flowing into internal pull-up resistors). 2. fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H). 3. fXX = fX operation (when oscillation mode selection register (OSMS) is set to 01H). 4. High-speed mode operation (when processor clock control register (PCC) is set to 00H). 5. Low-speed mode operation (when processor clock control register (PCC) is set to 04H). Remark fxx: Main system clock frequency (fx or f x/2) fx: Main system clock oscillation frequency 30 µPD78P083 AC Characteristics (1) Basic Operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Symbol Cycle time Test Conditions fXX = fX /2 TCY Note1 MIN. fXX = fX Note2 TI5, TI6 tTIH, low-level widths tTIL Interrupt input high-/ tINTH, low-level widths tINTL RESET low-level width tRSL µs 2.0 64 µs 0.4 32 µs 2.7 V ≤ VDD < 3.5 V 0.8 32 µs 0 4 MHz 0 275 kHz input frequency TI5, TI6 input high-/ Unit 64 3.5 V ≤ VDD ≤ 5.5 V VDD = 4.5 to 5.5 V fTI MAX. 0.8 (minimum instruction execution time) TYP. VDD = 2.7 to 5.5 V VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V 100 ns 1.8 µs 10 µs 20 µs 10 µs 20 µs Notes 1. When oscillation mode selection register (OSMS) is set to 00H. 2. When OSMS is set to 01H. Remark fxx: Main system clock frequency (fx or f x/2) fx: Main system clock oscillation frequency TCY vs VDD (Main System Clock f xx = fx/2 Operation) TCY vs VDD (Main System Clock fxx = fx Operation) 60 10 Cycle Time TCY [µ s] Cycle Time TCY [µ s] 60 Operation Guaranteed Range 2.0 1.0 0.5 0.4 0 10 Operation Guaranteed Range 2.0 1.0 0.5 0.4 1 2 3 4 5 6 Power Supply Voltage VDD [V] 0 1 2 3 4 5 6 Power Supply Voltage VDD [V] 31 µPD78P083 (2) Serial Interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (SCK2 ··· internal clock output) Parameter SCK2 cycle time SCK2 high-/low-level width Symbol tKCY1 tKH1, Test Conditions tSIK1 (to SCK2 ↑) SI2 hold time TYP. MAX. Unit 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns VDD = 4.5 to 5.5 V tKCY1/2–50 ns tKCY1/2–100 ns 4.5 V ≤ VDD ≤ 5.5 V 100 ns 2.7 V ≤ VDD < 4.5 V 150 ns 2.0 V ≤ VDD < 2.7 V 300 ns 400 ns 400 ns tKL1 SI2 setup time MIN. 4.5 V ≤ VDD ≤ 5.5 V tKSI1 (from SCK2 ↑) SCK2 ↓ → SO2 tKSO1 C = 100 pFNote 300 ns MAX. Unit output delay time Note C is the SCK2, SO2 output line load capacitance. (b) 3-wire serial I/O mode (SCK2 ··· external clock input) Parameter SCK2 cycle time SCK2 high-/low-level width SI2 setup time Symbol tKCY2 Test Conditions TYP. 4.5 V ≤ VDD ≤ 5.5 V 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns 400 ns tKH2, 4.5 V ≤ VDD ≤ 5.5 V tKL2 2.7 V ≤ VDD < 4.5 V 800 ns 2.0 V ≤ VDD < 2.7 V 1600 ns 2400 ns tSIK2 VDD = 2.0 to 5.5 V (to SCK2 ↑) SI2 hold time MIN. tKSI2 100 ns 150 ns 400 ns (from SCK2 ↑) SCK2 ↓ → SO2 tKSO2 C = 100 pFNote output delay time SCK2 rise, fall time tR2, tF2 Note C is the SO2 output line load capacitance. 32 VDD = 2.0 to 5.5 V 300 ns 500 ns 1000 ns µPD78P083 (c) UART mode (Dedicated baud rate generator output) Parameter Symbol Transfer rate (d) MAX. Unit 4.5 V ≤ VDD ≤ 5.5 V Test Conditions MIN. TYP. 78125 bps 2.7 V ≤ VDD < 4.5 V 39063 bps 2.0 V ≤ VDD < 2.7 V 19531 bps 9766 bps MAX. Unit UART mode (External clock input) Parameter ASCK cycle time ASCK high-/low-level width Symbol tKCY3 MIN. TYP. 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns tKH3 , 4.5 V ≤ VDD ≤ 5.5 V 400 ns tKL3 2.7 V ≤ VDD < 4.5 V 800 ns 2.0 V ≤ VDD < 2.7 V 1600 ns 2400 ns Transfer rate ASCK rise, fall time Test Conditions 4.5 V ≤ VDD ≤ 5.5 V tR3, 4.5 V ≤ VDD ≤ 5.5 V 39063 bps 2.7 V ≤ VDD < 4.5 V 19531 bps 2.0 V ≤ VDD < 2.7 V 9766 bps 6510 bps 1000 ns tF3 33 µPD78P083 AC Timing Test Point (Excluding X1 Input) 0.8 VDD 0.2 VDD 0.8 VDD Test Points 0.2 VDD Clock Timing 1/fx tXL tXH VDD – 0.5 V X1 Input 0.4 V TI Timing 1/fTI tTIL TI5, TI6 34 tTIH µPD78P083 Serial Transfer Timing 3-wire serial I/O mode: tKCY1, 2 tKH1, 2 tKL1, 2 tR2 tF2 SCK2 tSIK1, 2 tKSI1, 2 Input Data SI2 tKSO1, 2 Output Data SO2 UART mode (external clock input): tKCY3 tKL3 tKH3 tR3 tF3 ASCK 35 µPD78P083 A/D Converter Characteristics (T A = –40 to +85°C, AVDD = VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Test Conditions Resolution Total error MIN. TYP. 8 8 2.7 V ≤ AVREF ≤ AVDD Note Conversion time tCONV 19.1 Sampling time tSAMP 12/fxx Analog input voltage VIAN AVSS Reference voltage AVREF 2.7 AVREF-AVSS resistance RAIREF 4 36 fxx: Main system clock frequency (fx or f x/2) fx: Main system clock oscillation frequency Unit 8 bit 1.4 % 200 µs µs AVREF AVDD 14 Note Excluding quantization error (±1/2 LSB). Shown as a percentage of the full scale value. Remark MAX. V V kΩ µPD78P083 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C) Parameter Symbol Data retention supply voltage VDDDR Data retention supply current IDDDR Release signal set time tSREL Oscillation stabilization wait tWAIT time Test Conditions MIN. TYP. 1.8 V DDDR = 1.8 V 0.1 MAX. Unit 5.5 V 10 µA µs 0 Release by RESET 2 17/f x ms Note ms Release by interrupt Note 212/fxx or 214/fxx-217/fxx can be selected by bit 0-bit 2 (OSTS0-OSTS2) of oscillation stabilization time selection register (OSTS). Remark fxx: Main system clock frequency (fx or f x/2) fx: Main system clock oscillation frequency Data Retention Timing (STOP mode released by RESET) Internal reset operation HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby release signal: STOP mode released by interrupt signal) HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 37 µPD78P083 Interrupt Input Timing tINTL tINTH INTP1-INTP3 RESET Input Timing tRSL RESET 38 µPD78P083 PROM Programming Characteristics DC Characteristics (1) PROM Write Mode (TA = 25 ±5˚C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V) Parameter Symbol SymbolNote Test Conditions Input voltage, high VIH V IH Input voltage, low VIL VIL Output voltage, high VOH V OH IOH = –1 mA Output voltage, low VOL VOL IOL = 1.6 mA Input leakage current ILI ILI 0 ≤ VIN ≤ VDD VPP supply voltage VPP VPP VDD supply voltage VDD VCC VPP supply current IPP IPP VDD supply current IDD ICC MAX. Unit 0.7VDD MIN. TYP. VDD V 0 0.3V DD V VDD – 1.0 V 0.4 V +10 µA 12.2 12.5 12.8 V 6.25 6.5 6.75 V 50 mA 50 mA –10 PGM = V IL (2) PROM Read Mode (TA = 25 ±5˚C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V) Parameter Symbol SymbolNote MAX. Unit Input voltage, high VIH VIH 0.7VDD VDD V Input voltage, low VIL VIL 0 0.3V DD V Output voltage, high Test Conditions MIN. TYP. VOH1 VOH1 IOH = –1 mA VDD – 1.0 V VOH2 VOH2 IOH = –100 µA VDD – 0.5 V Output voltage, low VOL VOL IOL = 1.6 mA 0.4 V Input leakage current ILI ILI 0 ≤ VIN ≤ VDD –10 +10 µA Output leakage current ILO ILO 0 ≤ VOUT ≤ VDD, OE = VIH –10 +10 µA VPP supply voltage VPP VPP VDD – 0.6 VDD V DD + 0.6 V VDD supply voltage VDD VCC 4.5 5.0 5.5 V VPP supply current IPP IPP VPP = VDD 100 µA VDD supply current IDD ICCA1 CE = VIL, VIN = VIH 50 mA Note Corresponding µPD27C1001A symbol. 39 µPD78P083 AC Characteristics (1) PROM Write Mode (a) Page program mode (TA = 25 ±5˚C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V) Parameter Symbol Symbol Note Test Conditions MIN. TYP. MAX. Unit Address setup time (to OE ↓) tAS tAS 2 µs OE setup time tOES tOES 2 µs CE setup time (to OE ↓) tCES tCES 2 µs Input data setup time (to OE ↓) tDS tDS 2 µs Address hold time (from OE ↑) tAH tAH 2 µs tAHL tAHL 2 µs tAHV tAHV 0 µs Input data hold time (from OE ↑) tDH tDH 2 OE ↑ → Data output float tDF tDF 0 VPP setup time (to OE ↓) tVPS tVPS 1.0 ms VDD setup time (to OE ↓) tVDS tVCS 1.0 ms Program pulse width 0.095 µs 250 ns delay time tPW tPW OE ↓ → Valid data delay time tOE tOE 0.1 0.105 ms 1 OE pulse width during data tLW tLW 1 µs µs PGM setup time tPGMS tPGMS 2 µs CE hold time tCEH tCEH 2 µs OE hold time tOEH tOEH 2 µs latching (b) Byte program mode (TA = 25 ±5˚C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V) Parameter Symbol Symbol Note Test Conditions MIN. TYP. MAX. Unit Address setup time (to PGM ↓) tAS tAS 2 µs OE set time tOES tOES 2 µs CE setup time (to PGM ↓) tCES tCES 2 µs Input data setup time (to PGM ↓) tDS tDS 2 µs Address hold time (from OE ↑) tAH tAH 2 µs Input data hold time tDH tDH 2 µs tDF tDF 0 VPP setup time (to PGM ↓) tVPS tVPS 1.0 ms VDD setup time (to PGM ↓) tVDS tVCS 1.0 ms Program pulse width 0.095 (from PGM ↑) OE ↑ → Data output float 250 ns delay time tPW tPW OE ↓ → Valid data delay time tOE tOE OE hold time — Note 40 tOEH Corresponding µPD27C1001A symbol. 0.1 0.105 1 2 ms µs µs µPD78P083 (2) PROM Read Mode (T A = 25 ±5˚C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V) Parameter Symbol Symbol Note MAX. Unit tACC tACC CE = OE = VIL 800 ns CE ↓ → Data output delay time tCE tCE OE = VIL 800 ns OE ↓ → Data output delay time tOE tOE CE = VIL 200 ns OE ↑ → Data output float tDF tDF CE = VIL 0 60 ns tOH tOH CE = OE = VIL 0 Address → Data output Test Conditions MIN. TYP. delay time delay time Address → Data hold time ns Note Corresponding µPD27C1001A symbol. (3) PROM Programming Mode (TA = 25˚C, VSS = 0 V) Parameter PROM programming mode Symbol tSMA Test Conditions MIN. 10 TYP. MAX. Unit µs setup time 41 µPD78P083 PROM Write Mode Timing (page program mode) Page Data Latch Page Program Program Verify A2-A14 tAS tAHL tDS tDH tAHV A0, A1 D0-D7 Hi-Z tDF Hi-Z tVPS Data Input Hi-Z tPGMS Data tAH tOE Output VPP VPP VDD tVDS VDD+1.5 VDD VDD tOEH tCES VIH CE VIL tCEH tPW VIH PGM VIL tLW VIH OE VIL 42 tOES µPD78P083 PROM Write Mode Timing (byte program mode) Program Program Verify A0-A14 tAS D0-D7 tDF Hi-Z Hi-Z Data Input tDS Hi-Z Data Output tDH tAH VPP VPP VDD VDD+1.5 VDD VDD tVPS tVDS tOEH VIH CE VIL tCES tPW VIH PGM VIL tOES tOE VIH OE VIL Cautions 1. 2. 3. VDD should be applied before VPP, and removed after VPP. VPP must not exceed +13.5 V including overshoot. Reliability may be adversely affected if removal/reinsertion is performed while + 12.5 V is being applied to VPP. PROM Read Mode Timing Effective Address A0-A14 VIH CE VIL tCE VIH OE VIL tACCNote 1 D0-D7 Hi-Z tOENote 1 tDFNote 2 tOH Data Output Hi-Z Notes 1. If you want to read within the range of tACC, make the OE input delay time from the fall of CE a maximum of tACC– tOE. 2. tDF is the time from when either OE or CE first reaches VIH. 43 µPD78P083 PROM Programming Mode Setting Timing VDD VDD 0 RESET VDD VPP 0 tSMA A0-A14 44 Effective Address µPD78P083 9. PACKAGE DRAWINGS 42PIN PLASTIC SHRINK DIP (600 mil) 42 22 1 21 A K H G J I L F B D N R M C M NOTES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM MILLIMETERS INCHES A 39.13 MAX. 1.541 MAX. B 1.78 MAX. 0.070 MAX. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K L 15.24 (T.P.) 13.2 0.520 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15° 0.600 (T.P.) 0~15° P42C-70-600A-1 Remark The shape and material of ES versions are the same as those of mass-produced versions. 45 µPD78P083 µPD78P083GB-3B4 44 PIN PLASTIC QFP ( 10) A B 23 22 33 34 detail of lead end C D S R Q 12 11 44 1 F G J H I M K M P N L NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 13.6±0.4 0.535 +0.017 –0.016 B 10.0±0.2 0.394 +0.008 –0.009 C 10.0±0.2 0.394 +0.008 –0.009 D 13.6±0.4 0.535 +0.017 –0.016 F 1.0 0.039 G 1.0 0.039 H 0.35±0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P) K 1.8±0.2 0.071 +0.008 –0.009 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N P Q R S 0.10 2.7 0.1±0.1 5°±5° 3.0 MAX. 0.004 0.106 0.004±0.004 5°±5° 0.119 MAX. P44GB-80-3B4-3 Remark The shape and material of ES versions are the same as those of mass-produced versions. 46 µPD78P083 µPD78P083GB-3BS-MTX 44 PIN PLASTIC QFP ( 10) A B 23 22 33 34 detail of lead end C D S R Q 12 11 44 1 F J G H I M K M P N L NOTE Each lead centerline is located within 0.16 mm (0.007 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 13.2±0.2 0.520 +0.008 –0.009 B 10.0±0.2 0.394 +0.008 –0.009 C 10.0±0.2 0.394 +0.008 –0.009 D 13.2±0.2 0.520 +0.008 –0.009 F 1.0 0.039 G 1.0 0.039 H 0.37 +0.08 –0.07 0.015 +0.003 –0.004 I 0.16 0.007 J 0.8 (T.P.) 0.031 (T.P.) K 1.6±0.2 0.063±0.008 L 0.8±0.2 0.031 +0.009 –0.008 M 0.17 +0.06 –0.05 0.007 +0.002 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.125±0.075 R 3° +7° –3° 0.005±0.003 3° +7° –3° S 3.0 MAX. 0.119 MAX. S44GB-80-3BS Remark The shape and material of ES versions are the same as those of mass-produced versions. 47 µPD78P083 42PIN CERAMIC SHRINK DIP (WINDOW) (600 mil) X 22 1 21 Y 42 A K Z H G J I L F D B N M C M 0°~15° P42DW-70-600A NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) 48 Item "K" to center of leads when formed parallel. ITEM MILLIMETERS INCHES A 38.25 MAX. 1.506 MAX. B 1.345 MAX. 0.053 MAX. C 1.778 (T.P.) 0.07 (T.P.) D 0.46 ± 0.05 0.018 ± 0.002 F 0.85 MIN. 0.033 MIN. G 3.5 ± 0.3 0.138 ± 0.012 H 1.02 MIN. 0.040 MIN. I 3.026 0.119 J 5.282 MAX. 0.208 MAX. K 15.24 (T.P.) 0.600 (T.P.) L 14.99 0.590 M 0.25 ± 0.05 0.010 –0.003 N 0.25 0.01 X 12.0 0.472 Y 6.0 0.236 Z 4-R3.0 4-R0.118 +0.002 µPD78P083 10. RECOMMENDED SOLDERING CONDITIONS * It is recommended that the µPD78P083 be soldered under the following conditions. For details on the recommended soldering conditions, refer to information document "Semiconductor Device Mounting Technology Manual" (C10535E). For soldering methods and conditions other than those recommended, please contact your NEC sales representative. Table 10-1. Soldering Conditions for Surface Mount Types µPD78P083GB-3B4 : 44-pin plastic QFP (10 x 10 mm) µPD78P083GB-3BS-MTX : 44-pin plastic QFP (10 x 10 mm) Soldering Method Soldering Conditions Symbol Infrared ray reflow Package peak temperature: 235˚C, Reflow time: 30 seconds or less (at 210˚C or higher), Number of reflow processes: 2 or less < Cautions > (1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) Do not perform flux cleaning with water after the first reflow. IR35-00-2 VPS Package peak temperature: 215˚C, Reflow time: 40 seconds or less (at 200˚C or higher), Number of reflow processes: 2 or less < Cautions > (1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) Do not perform flux cleaning with water after the first reflow. VP15-00-2 Wave soldering Solder temperature: 260˚C or below, Flow time: 10 seconds or less, Number of flow processes: 1, Preheating temperature: 120˚C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300˚C or below, Flow time: 3 seconds or less (per pin row) — Caution Do not use different soldering methods together (except for partial heating method). Table 10-2. Soldering Condition for Hole-Through Types µPD78P083CU : 42-pin plastic shrink DIP (600 mil) µPD78P083DU : 42-pin ceramic shrink DIP (with window) (600 mil) Soldering Method Soldering Conditions Wave Soldering (only pins) Solder temperature: 260°C or below, Flow time: 10 seconds or less Partial heating Pin temperature: 300°C or below, Flow time: 3 seconds or less (per pin) Caution Apply wave soldering only to the pins and be careful so as not to bring solder into direct contact with the package. 49 µPD78P083 * APPENDIX A. DEVELOPMENT TOOLS The following development tools are available to support development of systems using the µPD78P083. Language Processing Software RA78K/0 Notes 1, 2, 3, 4 Assembler package common to the 78K/0 series CC78K/0 Notes 1, 2, 3, 4 C compiler package common to the 78K/0 series DF78083 Notes 1, 2, 3, 4 Device file used for the µPD78083 subseries CC78K/0–L Notes 1, 2, 3, 4 C compiler library source file common to the 78K/0 series PROM Writing Tools PG-1500 PROM programmer PA-78P083CU Programmer adapter connected to the PG-1500 PA-78P083GB PG-1500 Controller Notes 1, 2 Control program for the PG-1500 Debugging Tools IE-78000-R In-circuit emulator common to the 78K/0 series IE-78000-R-A Note 8 In-circuit emulator common to the 78K/0 series (for integrated debugger) IE-78000-R-BK Break board common to the 78K/0 series IE-78078-R-EM Emulation board common to the µPD78078 subseries EP-78083CU-R Emulation probe for the µPD78083 subseries EP-78083GB-R EV-9200G-44 SM78K0 ID78K0 Socket mounted on the target system board prepared for 44-pin plastic QFP Notes 5, 6, 7 Notes 4, 5, 6, 7, 8 System simulator common to the 78K/0 series Integrated debugger for IE-78000-R-A SD78K/0 Notes 1, 2 Screen debugger for the IE-78000-R DF78083 Notes 1, 2, 5, 6, 7 Device file used for the µPD78083 subseries Notes 1. Based on PC-9800 series (MS-DOSTM) 2. Based on IBM PC/ATTM and its compatibles (PC DOSTM/IBM DOSTM/MS-DOS) 3. Based on HP9000 series 300TM (HP-UXTM) 4. 5. 6. 7. Based on HP9000 series 700TM (HP-UX), SPARCstationTM (SunOSTM), and EWS4800 series (EWS-UX/V) Based on PC-9800 series (MS-DOS + WindowsTM) IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS + Windows) Based on NEWSTM (NEWS-OSTM) 8. Under development Remarks 50 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on the third party development tools. 2. Use the RA78K/0, CC78K/0, SM78K0, ID78K0, and SD78K/0 in combination with the DF78083. µPD78P083 Fuzzy Inference Development Support System FE9000 Note 1 FT9080 Note 1 FI78K0 /FE9200 Note 2 Fuzzy knowledge data creation tool /FT9085 Note 3 Translator Notes 1, 3 FD78K0 Notes 1, 3 Fuzzy inference module Fuzzy inference debugger Notes 1. Based on PC-9800 series (MS-DOS) 2. Based on IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS+Windows) 3. Based on IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS) Remark Please refer to the 78K/0 Series Selection Guide (U11126E) for information on the third party development tools. 51 µPD78P083 * APPENDIX B. RELATED DOCUMENTS Documents Related to Devices Document Name Document No. Japanese µPD78083 Subseries User’s Manual English IEU-886 IEU-1407 78K/0 Series User’s Manual—Instructions IEU-849 IEU-1372 78K/0 Series Instruction Table U10903J — 78K/0 Series Instruction Set U10904J — µPD78083 Subseries Special Function Register Table 78K/0 Series Application Note IEM-5599 Basic (III) IEA-767 — U10182E Documents Related to Development Tools (User's Manual) Document Name Document No. Japanese RA78K Series Assembler Package EEU-809 EEU-1399 Language EEU-815 EEU-1404 EEU-817 EEU-1402 Operation EEU-656 EEU-1280 Language EEU-655 EEU-1284 Programming EEA-618 EEA-1208 RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler CC78K/0 C Compiler Application Note English Operation know-how CC78K Series Library Source File EEU-777 PG-1500 PROM Programmer EEU-651 EEU-1335 PG-1500 Controller PC-9800 Series (MS-DOS) Based EEU-704 EEU-1291 PG-1500 Controller IBM PC Series (PC DOS) Based EEU-5008 U10540E IE-78000-R EEU-810 EEU-1398 IE-78000-R-A U10057J U10057E IE-78000-R-BK EEU-867 EEU-1427 IE-78078-R-EM U10775J EEU-1504 EP-78083 EEU-5003 EEU-1529 Reference EEU-5002 U10181E Third party’s user U10092J U10092E SM78K0 System Simulator SM78K Series System Simulator — open interface specifications SD78K/0 Screen Debugger Introduction EEU-852 — PC-9800 Series (MS-DOS) Based Reference U10952J — SD78K/0 Screen Debugger Introduction EEU-5024 EEU-1414 IBM PC/AT (PC DOS) Based Reference EEU-993 EEU-1413 Caution 52 The contents of the documents listed above are subject to change without prior notice. Make sure to use the latest edition when starting design. µPD78P083 Documents Related to Embedded Software (User’s Manual) Document Name Document No. Japanese 78K/0 Series OS MX78K0 Basic Fuzzy Knowledge Data Creation Tool English EEU-5010 — EEU-829 EEU-1438 78K/0, 78K/II, and 87AD Series Fuzzy Inference Development Support System Translator EEU-862 EEU-1444 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module EEU-858 EEU-1441 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger EEU-921 EEU-1458 Other Documents Document Name Document No. Japanese English Semiconductor Device Package Manual IEI-635 IEI-1213 Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices IEI-620 IEI-1209 NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 IEI-1201 Guide to Quality Assurance for Semicoductor Devices MEI-603 MEI-1202 Microcontroller-Related Product Guide – Third Party Products – MEI-604 — Caution The contents of the documents listed above are subject to change without prior notice. Be sure to use the latest edition when starting design. 53 µPD78P083 [MEMO] 54 µPD78P083 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. FIP, IEBus, and QTOP are trademarks of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation. HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. 55 µPD78P083 The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representive. License not needed : µPD78P083DU The customer must judge the need for license : µPD78P083CU, 78P083GB-3B4, 78P083GB-3BS-MTX No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: “Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11