DATA SHEET MOS INTEGRATED CIRCUIT µPD75P316B 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The µPD75P316B is a product of the µPD75316B with its built-in ROM having been replaced with the onetime PROM. It is most suitable for test production during system development and for production in small amounts since it can operate under the same supply voltage as mask products. The one-time PROM product is capable of writing only once and is effective for production of many kinds of sets in small quantities and early startup. The EPROM product allows programs to be written and rewritten, making it ideal for system evaluation. Functions are described in detail in the following User'S Manual, which should be read when carrying out design work. µPD75308 User's Manual: IEM-5016 FEATURES • Compatible (excluding mask option) with the µ PD75312B/75316B (mask products) • Memory capacity • Program memory (PROM) : 16256 × 8 bits • Data memory (RAM) : 1024 × 4 bits • Ideal for small set as camera, etc. ORDERING INFORMATION * Ordering Code µ PD75P316BGC-3B9 Package 80-pin plastic QFP (■ ■ 14 mm) Internal ROM One-time PROM Quality Grade Standard µ PD75P316BGK-BE9 µ PD75P316BKK-T* 80-pin plastic QFP (fine pitch) (■ ■ 12 mm) 80-pin ceramic WQNF (LCC with window) One-time PROM Standard EPROM Not applicable (for function evaluation) Under Development Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. The µPD75P316B EPROM product does not provide a level of reliability suitable for use as a volume production product for customers' devices. The EPROM product should be used solely for function evaluation in experiments or preproduction. In descriptions common to one-time PROM products and EPROM products in this document, the term "PROM" is used. The information in this document is subject to change without notice. Document No. IC-3189 (O.D. No. IC-8696) Date Published January 1994P Printed in Japan The mark ★ shows the major revised points. © NEC Corporation 1994 µPD75P316B PIN CONFIGURATION (Top View) 1 S17 6 7 8 9 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P72/KR6 P73/KR7 4 5 µPD75P316BGC-3B9 µPD75P316BGK-BE9 µPD75P316BKK-T S20 10 11 12 13 14 15 16 17 18 S21 S22 S23 S24/BP0 S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 In normal operation, VPP input should be the VDD level. P53 P00/INT4 P51 P52 P50 P41 P42 P43 VSS P40 COM3 BIAS VLC0 VLC1 VLC2 COM0 COM1 COM2 19 20 2122232425 262728 2930 31323334353637383940 S31/BP7 2 S3 S2 2 3 S18 S19 * S8 S7 S6 S5 S4 8079787776 757473 7271 70696867666564636261 P60/KR0 X2 X1 VPP* 60 59 58 57 56 55 54 53 52 P33/MD3 P32/MD2 51 50 49 48 47 46 45 44 43 P31/SYNC/MD1 P30/LCDCL/MD0 P23/BUZ P22/PCL P21 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 42 41 P10/INT0 XT2 XT1 VDD P03/SI/SB1 P01/SCK P02/SO/SB0 S12 S13 S14 S15 S16 S10 S9 S11 • 80-pin plastic TQFP (fine pitch)(■ ■ 12 mm) • 80-pin ceramic WQFN (LCC with window) S1 S0 RESET • 80-pin plastic QFP (■ ■ 14 mm) P00-03 : Port 0 VLC0-2 : LCD Power Supply 0-2 P10-13 P20-23 P30-33 P40-43 : : : : Port Port Port Port BIAS LCDCL SYNC TI0 : : : : LCD Power Supply Bias Control LCD Clock LCD Synchronization Timer Input 0 P50-53 P60-63 P70-73 BP0-7 : : : : Port 5 Port 6 Port 7 Bit Port PTO0 BUZ PCL INT0, 1, 4 : : : : Programmable Timer Output 0 Buzzer Clock Programmable Clock External Vectored Interrupt 0, 1, 4 KR0-7 SCK SI SO : : : : Key Return Serial Clock Serial Input Serial Output INT2 X1, 2 XT1, 2 MD0-3 : : : : External Test Input 2 Main System Clock Oscillation 1, 2 Subsystem Clock Oscillation 1, 2 Mode Selection SB0, 1 RESET S0-31 COM0-3 : : : : Serial Bus 0, 1 Reset Input Segment Output 0-31 Common Output 0-3 VDD VSS VPP : Positive Power Supply : Ground : Programing/Verifying Power 1 2 3 4 INTBT PROGRAM COUNTER (14) SP(8) 4 P00-P03 PORT1 4 P10-P13 PORT2 4 P20-P23 PORT3 4 P30-P33 /MD0-MD3 PORT4 4 P40-P43 PORT5 4 P50-P53 PORT6 4 P60-P63 PORT7 4 P70-P73 24 S0-S23 CY ALU TIMER/EVENT COUNTER #0 INTT0 TI0/P13 PTO0/P20 PORT0 BANK WATCH TIMER BUZ/P23 m INTW fLCD GENERAL REG. PROGRAM MEMORY DECODE AND CONTROL (PROM) SI/SB1/P03 SO/SB0/P02 SCK/P01 SERIAL BUS INTERFACE BLOCK DIAGRAM BASIC INTERVAL TIMER 16256 × 8 BITS DATA MEMORY (RAM) 1024 × 4 BITS INTCSI INT0/P10 INT1/P11 INTERRUPT CONTROL INT2/P12 INT4/P00 KR0/P60 –KR7/P73 LCD CONTROLLER /DRIVER N 8 BIT SEQ. BUFFER (16) fX / 2 SYSTEM CLOCK CLOCK CLOCK GENERATOR STAND BY OUTPUT DIVIDER SUB MAIN CONTROL CONTROL XT1 XT2 X1 X2 fLCD VPP VDD VSS RESET S24/BP0 –S31/BP7 4 COM0–COM3 3 VLC0–VLC2 BIAS LCDCL/P30 SYNC/P31 3 µPD75P316B PCL/P22 CPU CLOCK 8 µPD75P316B CONTENTS 1. PIN FUNCTIONS ......................................................................................................................................... 5 1.1 1.2 1.3 PORT PINS ........................................................................................................................................................... 5 OTHER PINS ......................................................................................................................................................... 7 PIN INPUT/OUTPUT CIRCUITS ......................................................................................................................... 9 2. DIFFERENCES BETWEEN PRODUCTS IN SERIES ................................................................................ 11 3. DATA MEMORY (RAM) ............................................................................................................................ 12 4. PROGRAM MEMORY WRITE AND VERIFY ............................................................................................ 14 4.1 4.2 4.3 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES ....................................................................... 14 PROGRAM MEMORY WRITING PROCEDURE ............................................................................................... 15 PROGRAM MEMORY READING PROCEDURE ............................................................................................... 16 4.4 ERASURE PROCEDURE(µPD75P316BKK-T-ONLY) ........................................................................................ 17 5. ELECTRICAL SPECIFICATIONS ............................................................................................................... 18 6. PACKAGE INFORMATION ....................................................................................................................... 39 7. RECOMMENDED SOLDERING CONDITIONS ........................................................................................ 42 APPENDIX A. DEVELOPMENT TOOLS ......................................................................................................... 43 APPENDIX B. RELATED DOCUMENTS ........................................................................................................ 44 4 µPD75P316B 1. PIN FUNCTIONS 1.1 PORT PINS (1/2) Pin Name Input/Output Dual-Function Pin P00 Input INT4 P01 Input/output SCK Input/output SO/SB0 P03 Input/output SI/SB1 P11 INT1 P12 INT2 P13 TI0 P20 PTO0 — P21 Input/output P22 PCL P23 BUZ P30 *2 LCDCL P31 *2 SYNC MD1 Input/output MD2 P33 *2 MD3 Input/output P60 P61 * 1. 2. × F -A Input F -B M-C 4-bit input port (PORT1) Internal pull-up resistor specification by software is possible as a 4-bit unit. × Input B -C 4-bit input/output port (PORT2) Internal pull-up resistor specification by software is possible as a 4-bit unit. × Input E-B Programmable 4-bit input/output port (PORT3) Input/output settable bit-wise. Internal pull-up resistor specification by software is possible as a 4-bit unit. × Input E-B — N-ch open-drain 4-bit input/output port (PORT 4). Data input/output pins for program memory (PROM) write/verify (low-order 4 bits). High impedance M-A — N-ch open-drain 4-bit input/output port (PORT 5) Data input/output pins for program memory (PROM) write/verify (high-order 4 bits). High impedance M-A Programmable 4-bit input/output port (PORT6). Input/output settable bit-wise. Internal pull-up resistor specification by software is possible as a 4-bit unit. Input F -A 4-bit input/output port (PORT7). Internal pull-up resistor specification by software is possible as a 4-bit unit. Input F -A KR0 Input/output KR1 P62 KR2 P63 KR3 P70 KR4 P71 I/O Circuit Type*1 MD0 P32 *2 Input/output Afer Reset With noise elimination circuit Input P50 to P53 *2 4-bit input port (PORT0) Internal pull-up resistor specification by software is possible for P01 to P03 as a 3-bit unit. INT0 P10 8-bit I/O B P02 P40 to P43*2 Function Input/output KR5 P72 KR6 P73 KR7 : Indicates a Schmitt-triggered input. Direct LED drive capability. 5 µPD75P316B 1.1 PORT PINS (2/2) Pin Name Input/Output BP0 DualFunction Pin Function 8-bit I/O After Reset I/O Circuit TYPE × * G-C S24 BP1 S25 Output ★ BP2 S26 BP3 S27 BP4 S28 BP5 1-bit output port (BIT PORT) Dual-function as segment output pins. S29 Output BP6 S30 BP7 S31 * For BP0 to BP7, VLC1 is selected as the input source. The output level depends on BP0 to BP7 and the VLC1 external circuit, however. 6 µPD75P316B 1.2 OTHER PINS Input/Output DualFunction Pin TI0 Input P13 External event pulse input pin for timer/event counter. PTO0 output P20 PCL Input/output BUZ SCK Pin Name After Reset I/O Circuit Type *1 — B -C Timer/event counter output pin Input E-B P22 Clock output pin Input E-B Input/output P23 Fixed frequency output pin (for buzzer or system clock trimming) Input E-B Input/output P01 Serial clock input/output pin Input F -A Input F -B Input M-C Function SO/SB0 Input/output P02 Serial data output pin Serial bus input/output pin SI/SB1 Input/output P03 Serial data input pin Serial bus input/output pin INT4 Input P00 Edge-detected vectored interrupt input pin (rising or falling edge detection). — B Edge-detected vectored interrupt input pin (detection edge selectable) — B -C Edge-detected testable input pin (rising edge detection) — B -C INT0 Input INT1 P10 P11 INT2 Input P12 KR0 to KR3 Input/output P60 to P63 Testable Input/output pins (parallel falling edge detection) Input F -A KR4 to KR7 Input/output P70 to P73 Testable Input/output pins (parallel falling edge detection) Input F -A S0 to S23 Output — Segment signal output pins *3 G-A S24 to S31 Output BP0 to 7 Segment signal output pins *3 G-A COM0 to COM3 Output — Common signal output pins *3 G-B VLC0 to VLC2 — — LCD drive power supply pins — — BIAS — — External split cutting output pin High impedance — LCDCL*2 Input/output P30 External extension driver drive clock output pin Input E-B SYNC*2 Input/output P31 External extension driver synchronization clock output pin Input E-B X1, X2 Input — Main system clock oscillation crystal/ceramic connection pins. When an external clock is used, the clock is input to X1 and the inverted clock to X2. — — XT1, XT2 Input — Subsystem clock oscillation crystal connection pins When an external clock is used, the clock is input to XT1 and the inverted clock toXT2. XT1 can be used as a 1-bit input (test) pin. — — RESET Input — System reset input pin (low-level active). — B MD0 to MD3 Input/output P30 to P33 Input E-B — — Mode selection pin for program memory (PROM) write/ verify. VPP — — Program voltage application pin for program memory (PROM) write/verify . Connected to VDD in normal operation. Applies +12.5 V in program memory write/ verify. VDD — — Positive power supply pin — — VSS — — GND potential pin — — 7 µPD75P316B * 1. : Indicates a Schmitt-triggered input. 2. Pins provided for future system expansion. Currently used only as pins 30 and 31. 3. VLCX shown below can be selected for display outputs. S0 to S31: VLC1, COM0 to COM2: VLC2 , COM3: VLC0 However, display output levels depend on the display output and VLCX external circuit. 8 µPD75P316B 1.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuits for each of the pin µPD75P316B are shown below in partially simplified form. TYPE D (For TYPE E-B, F-A) TYPE A (For TYPE E-B) VDD VDD data P-ch OUT P-ch IN output disable N-ch N-ch Push-pull output that can be made high-impedance output CMOS Standard Input Buffer TYPE B (P-ch and N-ch OFF) TYPE E-B VDD P.U.R. P.U.R. enable P-ch data IN IN/OUT Type D output disable Type A P.U.R.:Pull-Up Resistor Schmitt-Trigger Input with Hysteresis Characteristic TYPE B-C TYPE F-A VDD P.U.R. VDD P.U.R. enable P.U.R. P-ch P.U.R. enable P-ch data IN/OUT Type D output disable IN Type B P.U.R. : Pull-Up Resistor P.U.R.:Pull-Up Resistor 9 µPD75P316B TYPE F-B TYPE G-O ★ VDD VDD P.U.R. P.U.R. enable P-ch P-ch VLC0 VDD output disable (P) P-ch VLC1 IN/OUT data P-ch output disable SEG data/ Bit Port data N-ch OUT N-ch output disable (N) VLC2 N-ch P.U.R.:Pull-Up Resistor TYPE G-A TYPE M-A IN/OUT VLC0 P-ch N-ch (+10 V Withstand Voltage) data VLC1 output disable P-ch SEG data OUT N-ch VLC2 N-ch Middle-High Voltage Input Buffer (+10 V Withstand Voltage) TYPE G-B TYPE M-C VDD VLC0 P.U.R. P-ch P.U.R. enable VLC1 P-ch P-ch N-ch IN/OUT OUT COM data data N-ch output disable N-ch P-ch VLC2 N-ch P.U.R.:Pull-Up Resistor 10 µPD75P316B 2. DIFFERENCES BETWEEN PRODUCTS IN SERIES The µPD75P316B is a version of the µPD75316B with its built-in mask ROM replaced with the one-time PROM or EPROM. When performing debugging or preproduction of an application system using PROM and then volume production using a mask ROM product, etc., these differences should be taken into account in the transition. Table 2-1 shows the differences from the other products in series. For the details of the CPU functions and the built-in hardware, please refer to the µPD75308 User's Manual (IEM-5016). Table 2-1 Differences between Products in Series Product Name Comparison Item Program memory (bytes) µPD75P316A µPD75P316B • EPROM/one-time PROM • 16256 • One-time PROM • EPROM • 16256 Data memory (x 4 bits) • Mask ROM • 12160/16256 1024 Pull-up resistors of ports 4 and 5 None Incorporation specifiable by mask option LCD driving power supplying split resistor None Incorporation specifiable by mask option No.50 to 55 Pin connection Power supply voltage range Package Other P30/MD0 to P33/MD3 P30 to P33 VPP IC No.57 Electrical specifications * µPD75312B/75316B ★ The mask ROM products and PROM products have different consumption currents, etc. See the Electrical Specifications section in the relevant Data Sheets for details. 2.7 to 6.0 V • 80-pin plastic QFP (14 × 20 mm) • 80-pin ceramic WQNF (LCC with window) ★ 2.0 to 5.5 V • 80-pin plastic QFP (■ ■ 14 mm) • 80-pin plastic TQFP (fine pitch)(■ ■ 12 mm) • 80-pin ceramic QWFN (LCC with window) • 80-pin plastic QFP (■ ■ 14 mm) • 80-pin plastic TQFP (fine pitch)(■ ■ 12 mm) The mask ROM products and PROM products have different circuit scales and mask layouts, and therefore differ in terms of noise resistance and noise radiation. ★ ★ Noise resistance and noise radiation differs between the PROM products and mask ROM products. When investigating a switch from PROM product to mask PROM product in the transition from preproduction to volume production, thorough evaluation should be carried out with the mask ROM CS product (not the ES product). 11 µPD75P316B 3. DATA MEMORY (RAM) Fig. 3-1 shows the data memory configuration. It consists of a data area and a peripheral hardware area. The data area consists of memory banks 0 to 3 with each bank consisting of 256 words x 4 bits. Peripheral hardware has been assigned to the area of memory bank 15. (1) Data area The data area comprises a static RAM. It is used to store program data and as a subroutine, interrupt execution stack memory. Even if the CPU operation is stopped in the standby mode, it is possible to hold the memory content for a long time by battery backup, etc. The data area is operated by memory manipulation instructions. The static RAM has been mapped to memory banks 0, 1, 2 and 3 by 256 x 4 bits each. Bank 0 has been mapped as a data area but is also available as a general register area (000H to 007H) and a stack area (000H to 0FFH) (banks 1, 2 and 3 are available only as a data area). In the static RAM, 1 address consists of 4 bits. It can be operated in units of 8 bits by 8-bit memory manipulation instructions or in bits by bit manipulation instructions, however. In an 8-bit manipulation instruction, an even address should be specified. (a) General register area The general register area can be operated either by general register operation instructions or by memory manipulation instructions. Up to eight 4-bit registers are available. That part of the 8 general registers which is not used in the program is available as a data area or a stack area. (b) Stack area The stack area is set by an instruction. It is available as a subroutine execution or interrupt service execution save area. (2) Peripheral hardware area The peripheral hardware area has been mapped to F80H to FFFH of memory bank 15. It is operated by memory manipulation instructions just as the static RAM. In the peripheral hardware, however, the operable bit unit differs from one address to another. An address to which peripheral hardware has not been assigned is inaccessible since no data memory is built in. 12 µPD75P316B Fig. 3-1 Data Memory Map Data Memory General Register Area Memory Bank 000H (8 × 4) 007H Stack Area 008H 0 256 × 4 0FFH 100H Data Area Static RAM (1024 × 4) 256 × 4 1 256 × 4 2 256 × 4 3 1FFH 200H 2FFH 300H 3FFH Not On-Chip F80H 128 × 4 Peripheral Hardware Area 15 FFFH 13 µPD75P316B 4. PROGRAM MEMORY WRITE AND VERIFY The ROM built into the µPD75P316B is a 16256 x 8-bit electrically writable one-time PROM. The table below shows the pins used to program this PROM. There is no address input; instead, a method to update the address by the clock input via the X1 pin is adopted. Pin Name Function VPP Voltage applecation pin for program memory write/verify (normally VDD potential). X1, X2 Address update clock inputs for program memory write/ verify. Inverse of X1 pin signal is input to X2 pin. MD0 to MD3 Operating mode selection pin for program memory write/ verify. P40 to P43 (low-order 4 bits) 8-bit data input/output pins for progrm memory write/ P50 to P53 (high-order 4 bits) verify. Supply voltage application pin. Applies 2.0 to 5.5 V in normal operation, and 6 V for program memory write/verify. VDD 4.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES The µPD75P316B assumes the program memory write/verify mode when +6 V and +12.5 V are applied respectively to the VDD and VPP pins. The table below shows the operating modes available by the MD0 to MD3 pin setting in this mode. All the remaining pins are at the VSS potential by the pull-down resistor. Operating Mode Setting Operating Mode VPP +12.5 V X: L or H 14 VDD MD0 MD1 MD2 MD3 H L H L Program memory address zero-clear L H H H Write mode L L H H Verify mode H X H H Program inhibit mode +6 V µPD75P316B 4.2 PROGRAM MEMORY WRITING PROCEDURE The program memory writing procedure is shown below. High-speed write is possible. (1) Pull down a pin which is not used to VSS via the resistor. The X1 pin is at the low level. (2) (3) (4) (5) Supply 5 V to the VDD and VPP pins. 10 µs wait. The program memory address 0 clear mode. Supply 6 V and 12.5 V respectively to VDD and VPP. (6) (7) (8) (9) The program inhibit mode. Write data in the 1-ms write mode. The program inhibit mode. The verify mode. If written, proceed to (10); if not written, repeat (7) to (9). (10) (11) (12) (13) (Number of times written in (7) to (9): X) x 1-ms additional write. The program inhibit mode. Update (+1) the program memory address by inputting 4 pulses to the X1 pin. Repeat (7) to (12) up to the last address. (14) The program memory address 0 clear mode. (15) Change the VDD and VPP pins voltage to 5 V. (16) Power off. The diagram below shows the procedure of the above (2) to (12). Repeated X Times Write Verify Additional Write Address Increment VPP VPP VDD VDD + 1 VDD VDD X1 P40-P43 P50-P53 Data Input Data Output Data Input MD0 (P30) MD1 (P31) MD2 (P32) MD3 (P33) 15 µPD75P316B 4.3 PROGRAM MEMORY READING PROCEDURE The µPD75P316B can read the content of the program memory in the following procedure. It reads in the verify mode. (1) (2) (3) (4) Pull down a pin which is not used to VSS via the resistor. The X1 pin is at the low level. Supply 5 V to the VDD and VPP pins. 10 µs wait. The program memory address 0 clear mode. (5) Supply 6 V and 12.5 V respectively to VDD and VPP. (6) The program inhibit mode. (7) The verify mode. If clock pulses are input to the X1 pin, data is output sequentially 1 address at a time at the period of inputting 4 pulses. (8) (9) (10) (11) The program inhibit mode. The program memory address 0 clear mode. Change the VDD and VPP pins voltage to 5 V. Power off. The diagram below shows the procedure of the above (2) to (9). VPP VPP VDD VDD + 1 VDD VDD X1 P40-P43 P50-P53 Data Output MD0 (P30) MD1 (P31) MD2 (P32) MD3 (P33) 16 "L" Data Output µPD75P316B 4.4 ERASURE PROCEDURE (µPD75P316BKK-T ONLY) The data programmed in the µPD75P316B can be erased by exposure to ultraviolet radiation through the window in the top of the package. Erasure is possible using ultraviolet light with a wavelength of approximately 250 nm. The exposure required for complete erasure is 15 W.s/cm2 (UV intensity x erasure time). Erasure takes aproximately 15 to 20 minutes using a commercially available UV lamp (254 nm wavelength, 12 mW/cm2 intensity). Note 1. 2. Remarks Program contents may also be erased by extended exposure to direct sunlight or fluorescent light. The contents should therefore be protected by masking the window in the top of the package with light-shielding film. The light-shielding film provided with NEC's UV EPROM products should be used. Erasure should normally be carried out at a distance of 2.5 cm or less from the UV lamp. The erasure time may be increased due to deterioration of the UV lamp or dirt on the package window. 17 µPD75P316B 5. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C) PARAMETER SYMBOL Supply voltage TEST CONDITIONS RATING UNIT –0.3 to + 7.0 V –0.3 to VDD + 0.3 V –0.3 to + 11 V –0.3 to VDD + 0.3 V 1 pin –15 mA All pins –30 mA Peak value 30 mA R.m.s. value 15 mA 100 mA 60 mA 100 mA 60 mA VDD Input voltage VI1 Except ports 4 & 5 VI2 Ports 4 & 5 Output voltage VO Output current high IOH 1 pin IOH* Output current low Total for ports 0, 2, 3, 5 Peak value R.m.s. value Total for ports 4, 6, 7 Peak value R.m.s. value * Operating temperature Topt –40 to + 85 °C Storage temperature Tstg –65 to + 150 °C The r.m.s. value should be calculated as follows [R.m.s. value] = [Peak value] x Duty Note Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. CAPACITANCE (Ta = 25 °C, VDD = 0 V) PARAMETER Input capacitance Output capacitance I/O capacitance 18 SYMBOL TEST CONDITIONS CIN COUT CIO f=1 MHz Unmeasured pins returned to 0 V. MIN. TYP. MAX. UNIT 15 pF 15 pF 15 pF µPD75B316B MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85°C, VDD = 2.0 to 6.0 V) RESONATOR RECOMENDED CONSTANT X1 Ceramic resonator*3 X2 TEST CONDITIONS PARAMETER Oscillation frequency 1.0 C2 C1 X1 X2 Oscillation stabilization After VDD has reached MIN. time*2 of oscillation voltage range. Oscillation frequency MHz 4 ms 5.0*3 MHz 10 ms 30 ms 1.0 5.0*3 MHz 100 500 ns 1.0 (fXX)*1 C2 C1 VDD Oscillation stabilization VDD=4.5 to 6.0 V time*2 X1 input frequency X1 X2 External clock µPD74HCU04 * 5.0*3 (fXX)*1 VDD Crystal*3 MIN. TYP. MAX. UNIT (fX)*1 X1 input high-/low-level width (tXH, tXL) 4.19 1. The oscillation frequency and X1 input frequency are only indications of the oscillator characteristics. See the AC characteristics for instruction execution times. 2. The oscillation stabilization time is the time required for oscillation to stabilize after VDD reaches the MIN. value of the oscillation voltage range, or the STOP mode is released. 3. When the oscillation frequency is 4.19 MHz < fXX <= 5.0MHz, PCC = 0011 should not be selected as the instruction execution time. If PCC = 0011 is selected, one machine cycle will be less than 0.95 us, and the MIN. value of 0.95 us in the specification will not be achieved. Note When the main system clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. • The wiring should be kept as short as possible. • No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current. • The oscillator capacitor grounding point should always be at the same potential as VDD. Do not connect to a ground pattern carrying a high current. • A signal should not be taken from the oscillator. 19 µPD75P316B SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85°C, VDD = 2.0 to 6.0 V) RESONATOR RECOMENDED CONSTANT XT1 XT2 R Crystal resonator C2 C1 VDD PARAMETER Oscillation frequency External clock XT2 MIN. TYP. 32 32.768 35 kHz 1.0 2 s 10 s 32 100 kHz 5 15 µs (fXT) Oscillation stabilization VDD=4.5 to 6.0 V time* XT1 input frequency XT1 TEST CONDITIONS (fXT) MAX. UNIT Open XT1 input high-/lowlevel width (tXTH, tXTL) * This is the time required for oscillation to stabilize after VDD reaches the MIN. value of the oscillation voltage range. Note When the subsystem clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. • The wiring should be kept as short as possible. • No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current. • The oscillator capacitor grounding point should always be at the same potential as VDD. Do not connect to a ground pattern carrying a high current. • A signal should not be taken from the oscillator. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to misoperation due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. 20 µPD75B316B (1) VDD=2.7 to 6.0 V DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) PARAMETER Input voltage high Input voltage low SYMBOL TEST CONDITIONS VDD V VIH2 Ports 0, 1, 6, 7 and RESET 0.8 VDD VDD V VIH3 Ports 4 and 5 0.7 VDD 10 V VIH4 X1, X2, XT1 VDD –0.5 VDD V VIL1 Ports 2, 3, 4, 5 0 0.3 VDD V VIL2 Ports 0, 1, 6, 7 and RESET 0 0.2 VDD V VIL3 X1, X2, XT1 0 0.4 V VOH1 Ports 0, 2, 3, 6, 7, and BIAS BP0 to BP7 (with 2 IOH outputs) Ports 0, 2, 3, 4, 5, 6, 7 VOL1 Output voltage low SB0, 1 VOL2 BP0 to BP7 (with 2 IOL outputs) IL1H1 VDD = 4.5 to 6.0 V IOH = –1 mA VDD –1.0 V IOH = -100 µA VDD –0.5 V VDD = 4.5 to 6.0 V IOH = –100 µA VDD –2.0 V VDD –1.0 V IOH = –30 µA 2.0 V VDD = 4.5 to 6.0 V IOL = 1.6 mA 0.4 V IOL = 400 µA 0.5 V Open–drain pull-up resistor ≥ 1 kΩ 0.2 VDD V 1.0 V 1.0 V Other than below 3 µA X1, X2, XT1 20 µA Ports 4 and 5 20 µA Other than below –3 µA X1, X2, XT1 –20 µA VDD = 4.5 to 6.0 V IOL = 100 µA IOL = 50 µA 0.7 VIN = VDD ILIH2 ILIH3 Output leakage current low UNIT 0.7 VDD Ports 3, 4, 5 VDD = 4.5 to 6.0 V IOL = 15 mA Output leakage current high MAX. Ports 2 and 3 VOH2 Input leakage current low TYP. VIH1 Output voltage high Input leakage current high MIN. VIN = 10 V ILIL1 VIN = 0 V ILIL2 ILOH1 VOUT = VDD Other than below 3 µA ILOH2 VOUT = 10 V Ports 4 and 5 20 µA ILOL VOUT = 0 V –3 µA 21 µPD75P316B DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) PARAMETER Internal pull-up resistor SYMBOL RL TEST CONDITIONS Ports 0, 1, 2, 3, 6, 7 (Except P00) VIN = 0 V LCD drive voltage VLCD LCD output voltage deviation*1 (common) VODC IO = ±5 µA LCD output voltage deviation (segment) VODS IO = ±1 µA IDDI 4.19 MHz*3 crystal oscillation C1 = C2 = 22 pF IDD2 Supply current*2 IDD3 IDD4 32 kHz*6 crystal oscillation MIN. XT1 = 0 V STOP mode MAX. UNIT 40 80 kΩ VDD = 5.0 V ±10% 15 VDD = 3.0 V ±10% 30 200 kΩ 2.0 VDD V 0 ±0.2 V 0 ±0.2 V VLCD0 = VLCD VLCD1 = VLCD × 2/3 VLCD2 = VLCD × 1/3 2.7 V ≤ VLCD ≤ VDD VDD = 5 V ±10%*4 4.0 12 mA VDD = 3 V ±10%*5 0.5 1.5 mA VDD = 5 V ±10% 1 3 mA VDD = 3 V ±10% 300 900 µA VDD = 3 V ±10% 30 90 µA HALT mode 7 21 µA 1 25 µA 0.5 15 µA 0.5 5 µA HALT mode VDD = 3 V ±10% VDD = 5 V ±10% IDD5 TYP. VDD = 3 V ±10% Ta = 25 °C * 1. The voltage deviation is the difference between the output voltage and the ideal value of the common output (VLCDn; n = 0, 1, 2). 2. Excluding the current flowing in the internal pull-up resistor. 3. 4. 5. 6. Including the case where the subsystem clock is oscillated. When the processor clock control register (PCC) is set to 0011 for operation in high-speed mode. When PCC is set to 0000 for operation in low-speed mode. When the system clock control register (SCC) is set to 1001, main system clock oscillation is stopped, and the device is operated on the subsystem clock. 22 µPD75B316B AC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) PARAMETER SYMBOL CPU clock cycle time*1 (minimum instruction execution time = 1 machine cycle) tCY TI0 input frequency fTI TI0 input high-/lowlevel width tTIH, tTIL Interrupt input high-/low-level width RESET low-level width tINTH, tINTL TEST CONDITIONS Operating on main system clock MIN. VDD = 4.5 to 6.0 V TYP. MAX. UNIT 0.95 64 µs 3.8 64 µs 125 µs Operating on subsystem clock 114 VDD = 4.5 to 6.0 V 0 1 MHz 0 275 kHz 122 0.48 µs 1.8 µs INT0 *2 µs INT1, 2, 4 10 µs KR0 to KR7 10 µs 10 µs VDD = 4.5 to 6.0 V tRSL * 1. The CPU clock (Φ) cycle time (minimum instruction execution time) is determined by the oscillation frequency of the connected resonator, the system clock control register (SCC), and the processor control register (PCC). interrupt mode register (IM0). 70 64 30 6 Guaranteed 5 Operation Range 4 Cycle Time tCY [µs] The graph on the right shows the characteristic of the cycle time tCY against the supply current VDD in the case of main system clock operation. 2. 2tCY or 128/fX depending on the setting of the tCY vs VDD (Operating on Main System Clock) 3 2 1 0.5 0 1 2 3 4 5 6 Supply Voltage VDD [V] 23 µPD75P316B SERIAL TRANSFER OPERATIONS 2-Wired and 3-Wired Serial I/O Modes (SCK ... Internal clock output): (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time MIN. TYP. MAX. UNIT 1600 ns 3800 ns tKCY1/2-50 ns tKCY1/2-150 ns tKCY1 VDD = 4.5 to 6.0 V SCK high-/low-level width tKL1 tKH1 SI setup time (to SCK↑) tSIK1 150 ns SI hold time (from SCK↑) tKSI1 400 ns SO output delay time from SCK↓ tKSO1 * RL = 1 kΩ, CL = 100 pF VDD = 4.5 to 6.0 V 250 ns 1000 ns 2-Wired and 3-Wired Serial I/O Modes (SCK ... External clock input): (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time MIN. TYP. MAX. UNIT 800 ns 3200 ns 400 ns 1600 ns tKCY2 VDD = 4.5 to 6.0 V SCK high-/low-level width tKL2 tKH2 SI setup time (to SCK↑) tSIK2 100 ns SI hold time (from SCK ↑) tKSI2 400 ns SO output delay time from SCK↓ tKSO2 * 24 * RL = 1 kΩ, CL = 100 pF VDD = 4.5 to 6.0 V RL and CL are the SO output line load resistance and load capacitance. 300 ns 1000 ns µPD75B316B SBI Mode (SCK ... Internal clock output (Master)): (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time MIN. TYP. MAX. UNIT 1600 ns 3800 ns tKCY3/2-50 ns tKCY3/2-150 ns tKCY3 VDD = 4.5 to 6.0 V SCK high-/low-level width tKL3 tKH3 SB0, 1 setup time (to SCK ↑) tSIK3 150 ns SB0, 1 hold time (from SCK ↑) tKSI3 tKCY3/2 ns SB0, 1 output delay time from SCK ↓ tKSO3 SB0, 1 ↓ from SCK ↑ tKSB tKCY3 ns SCK from SB0, 1 ↓ tSBK tKCY3 ns SB0, 1 low-level width tSBL tKCY3 ns SB0, 1 high-level width tSBH tKCY3 ns RL = 1 kΩ, CL = 100 pF * VDD = 4.5 to 6.0 V 0 250 ns 0 1000 ns SBI Mode (SCK ... External clock input (Slave)): (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time * MIN. TYP. MAX. UNIT 800 ns 3200 ns 400 ns 1600 ns tKCY4 VDD = 4.5 to 6.0 V SCK high-/low-level width tKL4 tKH4 SB0, 1 setup time (to SCK ↑) tSIK4 100 ns SB0, 1 hold time (from SCK ↑) tKSI4 tKCY4/2 ns SB0, 1 output delay time from SCK ↓ tKSO4 SB0, 1 ↓ from SCK ↑ tKSB tKCY4 ns SCK ↓ from SB0, 1 ↓ tSBK tKCY4 ns SB0, 1 low-level width tSBL tKCY4 ns SB0, 1 high-level width tSBH tKCY4 ns RL = 1 kΩ, CL = 100 pF * VDD = 4.5 to 6.0 V 0 300 ns 0 1000 ns RL and CL are the SB0, 1 output line load resistance and load capacitance. 25 µPD75P316B (2) VDD=2.7 to 6.0 V DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) PARAMETER Input voltage high Input voltage low SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VIH1 Ports 2 and 3 0.8 VDD VDD V VIH2 Ports 0, 1, 6, 7 and RESET 0.8 VDD VDD V VIH3 Ports 4 and 5 0.8VDD 10 V VIH4 X1, X2, XT1 VDD –0.3 VDD V VIL1 Ports 2, 3, 4, 5 0 0.2 VDD V VIL2 Ports 0, 1, 6, 7 and RESET 0 0.2 VDD V VIL3 X1, X2, XT1 0 0.25 V VOH1 Ports 0, 2, 3, 6, 7 and BIAS IOH = –100 µA VDD –0.5 V VOH2 BP0 to BP7 (with 2 IOH outputs) IOH = –10 µA VDD –0.4 V Ports 0, 2, 3, 4, 5 6, 7 IOL = 400 µA SB0, 1 Open–drain, pull-up resistor ≥ 1 kΩ BP0 to BP7 (with 2 IOL outputs) IOL = 10 µA Output voltage high 0.5 V 0.2 VDD V 0.4 V Other than below 3 µA X1, X2, XT1 20 µA Ports 4 and 5 20 µA Other than below –3 µA X1, X2, XT1 –20 µA 3 µA 20 µA –3 µA 50 600 kΩ 2.0 VDD V VOL1 Output voltage low VOL2 ILIH1 Input leakage current high VIN = VDD ILIH2 ILIH3 Input leakage current low VIN = 10 V ILIL1 VIN = 0 V ILIL2 ILOH1 VOUT = VDD Other than below ILOH2 VOUT = 10 V Ports 4 and 5 Output leadage current low ILOL VOUT = 0 V Internal pull-up resistor RL Ports 0, 1, 2, 3, 6, 7 (Except P00) VIN = 0 V Output leakage current high LCD drive voltage 26 VLCD VDD = 2.5 V ±10% µPD75B316B DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS LCD output voltage deviation *1 (common) VODC IO = ±5 µA LCD output voltage deviation (segment) VODS IO = ±1 µA IDDI 4.19 MHz*3 crystal oscillation C1 = C2 = 22 pF low-speed mode VLCDO = VLCD VLCD1 = VLCD × 2/3 VLCD2 = VLCD × 1/3 2.0 V ≤ V LCD ≤ V DD Supply current*2 32 kHz*5 crystal oscillation MAX. UNIT 0 ±0.2 V 0 ±0.2 V 0.5 1.5 mA VDD = 2.5 V ±10%*4 0.4 1.2 mA HALT VDD = 3 V ±10% 300 900 µA mode VDD = 2.5 V ±10% 200 600 µA VDD = 3 V ±10% 40 90 µA VDD = 2.5 V ±10% 25 75 µA HALT VDD = 3 V ±10% 7 21 µA mode VDD = 2.5 V ±10% 4 12 µA 0.5 15 µA 0.5 5 µA 0.4 15 µA 0.4 5 µA IDD4 VDD = 3 V ±10% IDD5 TYP. VDD = 3 V ±10%*4 IDD2 IDD3 MIN. Ta = 25°C XT1 = 0 V STOP mode VDD = 2.5 V ±10% Ta = 25°C * 1. The voltage deviation is the difference between the output voltage and the ideal value of the common output (V LCDn; n = 0, 1, 2). 2. Excluding the current flowing in the internal pull-up resistor. 3. Including the case where the subsystem clock is oscillated. 4. When PCC is set to 0000 for operation in low-speed mode. 5. When the system clock control register (SCC) is set to 1001, main system clock oscillation is stopped, and the device is operated on the subsystem clock. 27 µPD75P316B AC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDD = 2.7 to 6.0 V 3.8 64 µs VDD = 2.0 to 6.0 V 5 64 µs 3.4 64 µs 125 µs 275 kHz CPU clock cycle time (minimum instruction execution time = 1 machine cycle)*1 tCY TI0 input frequency fTI 0 TI0 input high-/lowlevel width tTIH, tTIL 1.8 µs INT0 *2 µs Interrupt input high-/low-level width tINTH, tINTL INT1, 2, 4 10 µs KR0 to KR7 10 µs 10 µs RESET low-level width Operating on main system clock Ta = –40 to + 60 °C VDD = 2.2 to 6.0 V Operating on subsystem clock 114 tRSL * 1. The CPU clock (Φ ) cycle time (minimum instruction execution time) is determined by the oscillation frequency of the connected resonator, tCY vs VDD (Operating on Main System Clock) 70 64 30 the system clock control register (SCC), and the processor clock control register (PCC). The graph on the right shows the characteristic of the cycle time tCY against the supply current 6 5 Cycle Time t CY [µs] VDD in the case of main system clock operation. 2. 2t CY or 128/fX depending on the setting of the interrupt mode register (IMO). 122 Guaranteed 4 Operation Range 3 2 1 0.5 0 1 2 3 4 5 Supply Voltage VDD [V] 28 6 µPD75B316B SERIAL TRANSFER OPERATIONS 2-Wired and 3-Wired Serial I/O Mode (SCK ... Internal clock output): (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time MIN. TYP. MAX. UNIT 1600 ns 3800 ns tKCY1/2-50 ns tKCY1/2-150 ns tKCY1 VDD = 4.5 to 6.0 V SCK high-/lowlevel width tKL1 tKH1 SI setup time (to SCK ↑) tSIK1 250 ns SI hold time (from SCK ↑) tKSI1 400 ns SO output delay time from SCK ↓ tKSO1 VDD = 4.5 to 6.0 V RL = 1 kΩ, CL = 100 pF* 250 ns 1000 ns 2-Wired and 3-Wired Serial I/O Mode (SCK ... External clock input): (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time * MIN. TYP. MAX. UNIT 800 ns 3200 ns 400 ns 1600 ns tKCY2 VDD = 4.5 to 6.0 V SCK high-/lowlevel width tKL2 tKH2 SI setup time (to SCK↑) tSIK2 100 ns SI hold time (from SCK↑) tKSI2 400 ns SO output delay time from SCK↓ tKSO2 RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V 300 ns 1000 ns RL and CL are the SO output line load resistance and load capacitance. 29 µPD75P316B SBI Mode (SCK ... Internal clock output (Master)): (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time MIN. TYP. MAX. UNIT 1600 ns 3800 ns tKCY3/2-50 ns tKCY3/2-150 ns tKCY3 VDD = 4.5 to 6.0 V SCK high-/lowlevel width tKL3 tKH3 SB0, 1 setup time (to SCK↑) tSIK3 250 ns SB0, 1 hold time (from SCK↑) tKSI3 tKCY3/2 ns SB0, 1 output delay time from SCK↓ tKSO3 SB0, 1 ↓ from SCK↑ tKSB tKCY3 ns SCK from SB0, 1 ↓ tSBK tKCY3 ns SB0, 1 low-level width tSBL tKCY3 ns SB0, 1 high-level width tSBH tKCY3 ns VDD = 4.5 to 6.0 V RL = 1 kΩ, CL = 100 pF* 0 250 ns 0 1000 ns SBI Mode (SCK ... External clock input (Slave)): (Ta = –40 to +85 °C, VDD = 2.0 to 6.0 V) PARAMETER SCK cycle time SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V MIN. TYP. MAX. UNIT 800 ns 3200 ns 400 ns 1600 ns tKCY4 VDD = 4.5 to 6.0 V SCK high-/lowlevel width tKL4 tKH4 SB0, 1 setup time (to SCK ↑) tSIK4 100 ns SB0, 1 hold time (from SCK ↑) tKSI4 tKCY4/2 ns SB0, 1 output delay time from SCK ↓ tKSO4 SB0, 1 ↓ from SCK ↑ tKSB tKCY4 ns SCK↓ from SB0, 1 ↓ tSBK tKCY4 ns SB0, 1 low-level width tSBL tKCY4 ns SB0, 1 high-level width tSBH tKCY4 ns * 30 RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V RL and CL are the SBO, 1 output line load resistance and load capacitance. 0 300 ns 0 1000 ns µPD75B316B AC Timing Test Points (Except X1 and XT1 inputs) 0.8 VDD 0.8 VDD Test Points 0.2 VDD 0.2 VDD Clock Timings 1/fX tXL tXH VDD -0.5 V 0.4 V X1 Input 1/fXT tXTL tXTH VDD -0.5 V 0.4 V XT1 Input TI0 Timing 1/fTI tTIL tTIH TI0 31 µPD75P316B Serial Transfer Timing 3-wired serial I/O mode: tKCY1 tKL1 tKH1 SCK tKSI1 tSIK1 Input Data SI tKSO1 SO Output Data 2-wired serial I/O mode: tKCY2 tKL2 tKH2 SCK tSIK2 SB0,1 tKSO2 32 tKSI2 µPD75B316B Serial Transfer Timing Bus release signal transfer: tKL3,4 tKCY3,4 tKH3,4 SCK tKSB tSBL tSBH tSIK3,4 tSBK tKSI3,4 SB0,1 tKSO3,4 Command signal transfer: tKL3,4 tKCY3,4 tKH3,4 SCK tKSB tSIK3,4 tSBK tKSI3,4 SB0,1 tKSO3,4 Interrupt Input Timing tINTL tINTH INT0,1,2,4 KR0-7 RESET Input Timing tRSL RESET 33 µPD75P316B DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to +85 °C) PARAMETER SYMBOL Data retention supply voltage VDDDR Data retention supply current*1 IDDDR Release signal setting time tSREL Oscillation stabilization wait time*2 tWAIT TEST CONDITIONS MIN. TYP. 2.0 VDDDR = 2.0 V 0.3 MAX. UNIT 6.0 V 15 µA µs 0 Release by RESET Release by interrupt request 217/fx ms *3 ms * 1. Excluding current flowing in the internal pull-up resistor. 2. The oscillation stabilization time is the time during which the CPU operation is stopped to prevent unstable operation when oscillation is started. 3. Depends on the basic interval timer mode register (BTM) setting ( see table below). 34 BTM3 BTM2 BTM1 BTM0 WAIT TIME (Figure in ( ) is for fx = 4.19 MHz) — 0 0 0 220/fx (Approx. 250 ms) — 0 1 1 217/fx (Approx. 31.3 ms) — 1 0 1 215/fx (Approx. 7.82 ms) — 1 1 1 213/fx (Approx. 1.95 ms) µPD75B316B Data Retention Timing (STOP mode release by RESET) Internal Reset Operation HALT Mode STOP Mode Operating Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution RESET tWAIT Data Retention Timing (Standby release signal: STOP mode release by interrupt signal) HALT Mode STOP Mode Operating Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT 35 µPD75P316B DC PROGRAMMING CHARACTERISTICS (Ta = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V) PARAMETER Input voltage high Input voltage low Input leakage current SYMBOL TEST CONDITIONS MAX. UNIT Except X1, X2 0.7 VDD VDD V VIH2 X1, X2 VDD –0.5 VDD V VIL1 Except X1, X2 0 0.3 VDD V VIL2 X1, X2 0 0.4 V 10 µA IL1 VIN = V IL or VIH VOH IOH = –1 mA Outputvoltage low VOH IOL = 1.6 mA VDD supply current IDD VDD supply current IPP 36 TYP. VIH1 Output voltage high Note MIN. MD0 = V IL, MDI = VIH 1. Ensure that VPP does not exeed +13.5 V including overshoot. 2. VDD must be applied before VPP, and cut after VPP. VDD –1.0 V 0.4 V 30 mA 30 mA µPD75B316B DC PROGRAMMING CHARACTERISTICS (Ta = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, V PP = 12.5 ± 0.3 V, VSS = 0 V) PARAMETER SYMBOL *1 TEST CONDITIONS MIN. Address setup time*2 (to MD0↓) tAS tAS 2 µs MD1 setup time (to MD0↓) tM1S tOES 2 µs Data setup time (to MD0↓) tDS tDS 2 µs Address hold time*2 (from MD0↑) tAH tAH 2 µs Data hold time (from MD0↑) tDH tDH 2 µs Data output float delay time from MD0↑ tDF tDF 0 VPP setup time (to MD3↑) tVPS tVPS 2 µs VDD setup time (to MD3↑) tVDS tVCS 2 µs Initial program pulse width tPW tPW 0.95 Additional program pulse width tOPW tOPW 0.95 MD0 setup time (to MD1↑) tMOS tCES 2 Data output delay time from MD0↓ tDV tDV MD1 hold time (from MD0↑) tM1H tOEH MD1 recovery time (from MD0↓) tM1R tOR Program counter reset time tPCR X1 input high-/low-level width tXH, tXL X1 input frequency fX Initial mode setting time tI 2 µs MD3 setup time (to MD1↑) tM3S 2 µs MD3 hold time (from MD1↓) tM3H 2 µs MD3 setup time (to MD0↓) tM3SR Program memory read 2 µs Data output delay time from address*2 tDAD tACC Program memory read 2 µs Data output hold time from address*2 tHAD tOH Program memory read 0 MD3 hold time (from MD0↑) tM3HR Program memory read 2 µs Data output float delay time from MD3↓ tDFR Program memory read 2 µs MD0=MD1=VIL tM1H +tM1R ≥ 50 µs TYP. MAX. 130 1.0 UNIT ns 1.05 ms 21.0 ms µs 1 µs 2 µs 2 µs 10 µs 0.125 µs 4.19 130 MHz µs * 1. Symbol of corresponding µPD27C256A 2. The internal address signal is incremented by 1 on the 4th rise of the X1 input, and is not connected to a pin. 37 µPD75P316B Program Memory Write Timing tVPS VPP VPP VDD VDD tVDS VDD + 1 VDD tXH X1 tXL P40 - P43 P50 - P53 Data Input tDS t1 Data Output tDH tDV Data Input tDS tDF Data Input tDH tAH tAS MD0 tPW tM1R tM0S tOPW MD1 tPCR tM1S tM1H MD2 tM3H tM3S MD3 Program Memory Read Timing tVPS VPP VPP VDD tVDS VDD + 1 VDD VDD tXH X1 tDAD tHAD tXL P40 - P43 P50 - P53 Data Output tDV t1 MD0 MD1 tPCR MD2 tM3SR MD3 38 Data Output tDFR tM3HR µPD75P316B 6. PACKAGE INFORMATION 80 PIN PLASTIC QFP ( 14) A B 41 40 60 61 Q 5°±5° S D C detail of lead end 21 20 F 80 1 G H I M J M P K N L S80GC-65-3B9-3 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 17.2 ± 0.4 0.677 ± 0.016 B 14.0 ± 0.2 0.551+0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.2 ± 0.4 0.677 ± 0.016 F 0.8 0.031 G 0.8 0.031 H 0.30 ± 0.10 0.012+0.004 –0.005 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.6 ± 0.2 0.063 ± 0.008 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006+0.004 –0.003 N 0.10 0.004 P 2.7 0.106 Q 0.1 ± 0.1 0.004 ± 0.004 S 3.0 MAX. 0.119 MAX. 39 µPD75P316B 80 PIN PLASTIC TQFP (FINE PITCH) ( 12) A B 60 41 61 40 21 F 80 1 20 H I M J K M P G R Q S D C detail of lead end N L NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 14.0±0.2 INCHES 0.551 +0.009 –0.008 B 12.0±0.2 0.472 +0.009 –0.008 C 12.0±0.2 0.472 +0.009 –0.008 D 14.0±0.2 0.551 +0.009 –0.008 F 1.25 G 1.25 H 0.22 +0.05 –0.04 0.049 0.049 0.009±0.002 I 0.10 J 0.5 (T.P.) K 1.0±0.2 0.039 +0.009 –0.008 L 0.5±0.2 0.020 +0.008 –0.009 M 0.145 +0.055 –0.045 0.006±0.002 N 0.10 P 1.05 Q 0.05±0.05 R 5°±5° S 1.27 MAX. 0.004 0.020 (T.P.) 0.004 0.041 0.002±0.002 5°±5° 0.050 MAX. P80GK-50-BE9-4 40 µPD75P316B 80 PIN CERAMIC WQFN A Q K B D 80 S W C U1 T H U 1 I M R G F J Z X80KW-65A-1 NOTE Each lead centerline is located within 0.06 mm (0.003 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 14.0 ± 0.2 0.551 ± 0.008 B 13.6 0.535 C 13.6 0.535 D 14.0 ± 0.2 0.551 ± 0.008 F 1.84 0.072 G 3.6 MAX. 0.142 MAX. H 0.45 ± 0.10 0.018+0.004 –0.005 I 0.06 0.003 J 0.65 (T.P.) 0.024 (T.P.) K 1.0 ± 0.15 0.039+0.007 –0.006 Q C 0.3 C 0.012 R 0.825 0.032 S 0.825 0.032 T R 2.0 R 0.079 U 9.0 0.354 U1 2.1 0.083 W 0.75 ± 0.15 0.030+0.006 –0.007 Z 0.10 0.004 41 µPD75P316B 7. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions for the surface mounting type, refer to the information document "Surface Mount Technology Manual (IEI 1207)". For soldering methods and conditions other than those recommended below, contact our salesman. Table 7-1 Recommended Soldering Conditions µ PD75P316BGC-3B9: 80-Pin Plastic QFP (■ ■ 14 mm) Soldering Method Infrared reflow Pin part heating Recommended Soldering Conditions Package peak temperature: 230°C; Duration: 30 sec. max. (at 210°C or above); Number of times: once; Recommended Condition Symbol IR35-00-1 Pin part temperature: 300°C max.; Duration: 3 sec. max. (per device side) µPD75P316BGK-ΒΕ9: 80-Pin Plastic QFP (■ ■ 12 mm) Soldering Method Recommended Soldering Conditions Package peak temperature: 235°C; Duration: 30 sec. max. (at 210°C or above); Infrared reflow Number of times: once; Timelimit: 7 days*(thereafter 10 hours prebaking required at 125°C) Pin part heating * IR35-00-1 Pin part temperature: 300°C max.; Duration: 3 sec. max. (per device side) For the storage period after dry-pack decapsulation, storage conditions are max. 25°C, 65% RH. Note 42 Recommended Condition Symbol Use of more than one soldering method should be avoided (except in the case of pin part heating). µPD75P316B APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the µPD75P316B. IE-75000-R*1 75X series in-circuit emulator Hardware IE-75001-R IE-7500-R-EM*2 Emulation board for IE-75000-R and IE-75001-R EP-75308BGC-R Emulation probe for µPD75P316BGC. EV-9200GC-80 EP-75308BGK-R EV-9500GK-80 Software PG-1500 * Provided with EV-9200GC-80, 80-pin conversion socket. µPD75P316BGK emulation probe. Provided with EV-9200GK-80, 80-pin conversion socket. PROM programmer PA-75P316BGC µPD75P316BGC programmer adapter. Connected with PG-1500. PA-75P316BGK µPD75P316BGK programmer adapter. Connected with PG-1500. IE control program Host Machine PG-1500 controller PC-9800 series (MS-DOS™ Ver.3.30 to Ver.5.00A*3) RA75X relocatable assembler IBM PC/AT™ (PC DOS™ Ver.3.1) 1. Maintenance product 2. Not incorporated in the IE-75001-R. ★ 3. The task swap function, which is provided with Ver.5.00/5.00A, is not available with this software. 43 µPD75P316B APPENDIX B. RELATED DOCUMENTS Device Related Documents Document Name Document Number User's Manual IEM-5016 Instruction Application Table IEM-994 IEM-5035 Application Note IEM-5041 75X Series Selection Guide IF-151 Development Tools Documents Software Hardware Document Name Document Number IE-75000-R/IE-75001-R User's Manual EEU-846 IE-75000-R-EM User's Manual EEU-673 EP-75308BGC-R User's Manual EEU-825 EP-75308BGK-R User's Manual EEU-838 PG-1500 User's Manual EEU-651 RA75X Assembler Package User's Manual Operation EEU-731 Language EEU-730 PG-1500 Controller User's Manual EEU-704 Other Documents Document Name Document Number Package Manual IEI-635 Surface Mount Technology Manual IEI-1207 Quality Grande on NEC Semiconductor Device IEI-1209 NEC Semiconductor Device Reliability & Quality Control IEM-5068 Electrostatic Discharge(ESD) Test MEM-539 Semiconductor Devices Quality Guarantee Guide MEI-603 Microcomputer Related Products Guide Other Manufacturers Volume MEI-604 * 44 The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc. µPD75P316B 45 µPD75P316B [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6