NEC UPD75P0116GB-3BS-MTX

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P0116
4-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µ PD75P0116 replaces the µPD750108’s internal mask ROM with a one-time PROM and features expanded
ROM capacity.
Because the µ PD75P0116 supports programming by users, it is suitable for use in prototype testing for system
development using the µ PD750104, 750106, or 750108 products, and for use in small-lot production.
Detailed information about product features and specifications can be found in the following document
µPD750108 User's Manual: U11330E
FEATURES
• Compatible with µ PD750108
• Memory capacity:
• PROM : 16384 × 8 bits
• RAM
: 512 × 4 bits
• Can operate in same power supply voltage as the mask ROM version µPD750108
• VDD = 1.8 to 5.5 V
ORDERING INFORMATION
Part number
Package
ROM (× 8 bits)
µ PD75P0116CU
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
16384
µ PD75P0116GB-3BS-MTX
44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)
16384
Caution On-chip pull-up resistors by mask option cannot be provided.
The information in this document is subject to change without notice.
Document No. U12603EJ1V0DS00 (1st edition)
Date Published June 1997 N
Printed in Japan
©
1997
µPD75P0116
FUNCTION LIST
Item
Function
• 4, 8, 16, 64 µs (main system clock: at 1.0 MHz operation)
• 2, 4, 8, 32 µs (main system clock: at 2.0 MHz operation)
• 122 µs (subsystem clock: at 32.768 kHz operation)
Instruction execution time
On-chip memory
PROM
16384 × 8 bits
RAM
512 × 4 bits
• In 4-bit operation: 8 × 4 banks
General register
• In 8-bit operation: 4 × 4 banks
I/O port
CMOS input
CMOS I/O
N-ch open drain I/O
8
Connection of on-chip pull-up resistor specifiable by software: 7
18
Direct LED drive capability
Connection of on-chip pull-up resistor specifiable by software: 18
8
Direct LED drive capability
13 V withstand voltage
Total
Timer
34
4 channels
•
•
•
•
2
8-bit timer/event counter: 1 channel
8-bit timer counter: 1 channel (with watch timer output function)
Basic interval timer/watchdog timer: 1 channel
Watch timer: 1 channel
Serial interface
• 3-wire serial I/O mode ... Switching of MSB/LSB-first
• 2-wire serial I/O mode
• SBI mode
Bit sequential buffer (BSB)
16 bits
Clock output (PCL)
• Φ, 125, 62.5, 15.6 kHz (main system clock: at 1.0 MHz operation)
• Φ, 250, 125, 31.3 kHz (main system clock: at 2.0 MHz operation)
Buzzer output (BUZ)
• 2, 4, 32 kHz (subsystem clock: at 32.768 kHz operation)
• 0.488, 0.977, 7.813 kHz (main system clock: at 1.0 MHz operation)
• 0.977, 1.953, 15.625 kHz (main system clock: at 2.0-MHz operation)
Vectored interrupt
External: 3 Internal: 4
Test input
External: 1 Internal: 1
System clock oscillation circuit
• Main system clock oscillation RC oscillation circuit (with external resistor and capacitor)
• Subsystem clock oscillation crystal oscillation circuit
Standby function
STOP/HALT mode
Operating ambient temperature
TA = –40 to +85 ˚C
Supply voltage
VDD = 1.8 to 5.5 V
Package
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)
µPD75P0116
TABLE OF CONTENTS
1.
PIN CONFIGURATION (Top View) .................................................................................................... 4
2.
BLOCK DIAGRAM ............................................................................................................................. 6
3.
PIN FUNCTIONS ................................................................................................................................ 7
4.
3.1
3.2
Port Pins ..................................................................................................................................................... 7
Non-port Pins ............................................................................................................................................. 8
3.3
3.4
I/O Circuits for Pins ................................................................................................................................... 9
Handling of Unused Pins ........................................................................................................................ 11
SWITCHING BETWEEN MK I AND MK II MODES .......................................................................... 12
4.1
4.2
Differences between Mk I Mode and Mk II Mode ................................................................................... 12
Setting of Stack Bank Selection (SBS) Register ................................................................................... 13
5.
DIFFERENCES BETWEEN µPD75P0116 AND µPD750104, 750106, AND 750108 ...................... 14
6.
MEMORY CONFIGURATION ........................................................................................................... 15
7.
INSTRUCTION SET .......................................................................................................................... 17
8.
ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 28
9.
8.1
8.2
Operation Modes for Program Memory Write/Verify ............................................................................ 28
Steps in Program Memory Write Operation .......................................................................................... 29
8.3
8.4
Steps in Program Memory Read Operation ........................................................................................... 30
One-Time PROM Screening .................................................................................................................... 31
ELECTRICAL SPECIFICATIONS ..................................................................................................... 32
10. CHARACTERISTIC CURVES (REFERENCE VALUE) .................................................................... 46
11. RC OSCILLATION FREQUENCY CHARACTERISTICS EXAMPLES (REFERENCE VALUE) ...... 47
12. PACKAGE DRAWINGS .................................................................................................................... 49
13. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 51
APPENDIX A. FUNCTION LIST OF µPD750008, 750108, AND 75P0116 ............................................. 52
APPENDIX B. DEVELOPMENT TOOLS ................................................................................................. 54
APPENDIX C. RELATED DOCUMENTS ................................................................................................ 58
3
µPD75P0116
1. PIN CONFIGURATION (Top View)
• 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
µPD75P0116CU
XT1
1
42
VSS
XT2
2
41
P40/D0
RESET
3
40
P41/D1
CL1
4
39
P42/D2
CL2
5
38
P43/D3
P33/MD3
6
37
P50/D4
P32/MD2
7
36
P51/D5
P31/MD1
8
35
P52/D6
P30/MD0
9
34
P53/D7
P81
10
33
P60/KR0
P80
11
32
P61/KR1
P03/SI/SB1
12
31
P62/KR2
P02/SO/SB0
13
30
P63/KR3
P01/SCK
14
29
P70/KR4
P00/INT4
15
28
P71/KR5
P13/TI0
16
27
P72/KR6
P12/INT2
17
26
P73/KR7
P11/INT1
18
25
P20/PTO0
P10/INT0
19
24
P21/PTO1
VPPNote
20
23
P22/PCL
VDD
21
22
P23/BUZ
Note Directly connect VPP to VDD in the normal operation mode.
P71/KR5
P70/KR4
P63/KR3
P62/KR2
P61/KR1
P60/KR0
P53/D7
P52/D6
P51/D5
P12/INT2
NC
VPPNote
P10/INT0
P11/INT1
P13/TI0
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI/SB1
P80
P81
P30/MD0
P31/MD1
P32/MD2
11
23
12 13 14 15 16 17 18 19 20 21 22
P33/MD3
NC
P43/D3
P42/D2
P41/D1
P40/D0
VSS
P50/D4
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
CL1
CL2
P72/KR6
XT1
XT2
RESET
µPD75P0116GB-3BS-MTX
P73/KR7
P20/PTO0
P21/PTO1
P22/PCL
P23/BUZ
VDD
• 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)
Note Directly connect VPP to VDD in the normal operation mode.
4
µPD75P0116
PIN NAMES
BUZ
: Buzzer Clock
P70-P73
: Port7
CL1, CL2
: Main System Clock (RC)
P80, P81
: Port8
D0-D7
: Data Bus 0-7
PCL
: Programmable Clock
INT0, 1, 4
: External Vectored Interrupt 0, 1, 4
PTO0, PTO1
: Programmable Timer Output 0, 1
INT2
: External Test Input 2
RESET
: Reset
KR0-KR7
: Key Return 0-7
SB0, SB1
: Serial Data Bus 0, 1
MD0-MD3
: Mode Selection 0-3
SCK
: Serial Clock
NC
: No Connection
SI
: Serial Input
P00-P03
: Port0
SO
: Serial Output
P10-P13
: Port1
TI0
: Timer Input 0
P20-P23
: Port2
VDD
: Positive Power Supply
P30-P33
: Port3
VPP
: Programming Power Supply
P40-P43
: Port4
VSS
: Ground
P50-P53
: Port5
XT1, XT2
: Subsystem Clock (Crystal)
P60-P63
: Port6
5
µPD75P0116
2. BLOCK DIAGRAM
BIT SEQ.
BUFFER (16)
BASIC INTERVAL
TIMER/
WATCHDOG
TIMER
INTBT
RESET
PROGRAM
COUNTER (14)
SP (8)
CY
8-BIT
TIMER/EVENT
COUNTER #0
TI0/P13
PTO0/P20
INTT0
BANK
CLOCKED
SERIAL
INTERFACE
SO/SB0/P02
SCK/P01
P00-P03
PORT1
4
P10-P13
PORT2
4
P20-P23
PORT3
4
P30/MD0-P33/MD3
PORT4
4
P40/D0-P43/D3
PORT5
4
P50/D4-P53/D7
PORT6
4
P60-P63
PORT7
4
P70-P73
PORT8
2
P80, P81
GENERAL
REGISTER
INTT1
SI/SB1/P03
4
TOUT0
8-BIT TIMER
COUNTER
#1
PTO1/P21
PORT0
SBS
ALU
PROGRAM
MEMORY
(PROM)
16384 × 8 BITS
DECODE
AND
CONTROL
DATA
MEMORY
(RAM)
512 × 4 BITS
TOUT0
INTCSI
INT0/P10
INT1/P11
INTERRUPT
CONTROL
INT2/P12
INT4/P00
KR0/P60KR7/P73
8
fx/2N
BUZ/P23
WATCH
TIMER
INTW
CLOCK
CLOCK
OUTPUT DIVIDER
CONTROL
PCL/P22
6
CPU CLOCK
Φ
SYSTEM CLOCK
GENERATOR
SUB
MAIN
XT1 XT2
CL1 CL2
STAND BY
CONTROL
VPP VDD VSS RESET
µPD75P0116
3. PIN FUNCTIONS
3.1 Port Pins
Pin name
I/O
Shared by
Function
8-bit
I/O
When
reset
I/O circuit
type Note 1
This is a 4-bit input port (PORT0).
For P01 to P03, on-chip pull-up resistor connections
are software-specifiable in 3-bit units.
×
Input
<B>
P00
I
INT4
P01
I/O
SCK
P02
I/O
SO/SB0
<F>-B
P03
I/O
SI/SB1
<M>-C
P10
I
INT0
P11
INT1
P12
INT2
P13
TI0
P20
I/O
PTO0
P21
PTO1
P22
PCL
P23
BUZ
P30
I/O
MD0
P31
MD1
P32
MD2
P33
MD3
P40 Note 2
I/O
D0
P41 Note 2
D1
P42 Note 2
D2
P43 Note 2
D3
P50 Note 2
I/O
D4
P51 Note 2
D5
P52 Note 2
D6
P53 Note 2
D7
P60
I/O
KR0
P61
KR1
P62
KR2
P63
KR3
P70
I/O
KR4
P71
KR5
P72
KR6
P73
KR7
P80
P81
I/O
—
—
<F>-A
This is a 4-bit input port (PORT1).
On-chip pull-up resistor connections are softwarespecifiable in 4-bit units.
P10/INT0 can select noise elimination circuit.
×
Input
<B>-C
This is a 4-bit I/O port (PORT2).
On-chip pull-up resistor connections are softwarespecifiable in 4-bit units.
×
Input
E-B
This is a programmable 4-bit I/O port (PORT3).
Input and output can be specified in single-bit
units. On-chip pull-up resistor connections are
software-specifiable in 4-bit units.
×
Input
E-B
This is an N-ch open-drain 4-bit I/O port (PORT4).
In the open-drain mode, withstands up to 13 V.
Highimpedance
M-E
This is an N-ch open-drain 4-bit I/O port (PORT5).
In the open-drain mode, withstands up to 13 V.
Highimpedance
M-E
This is a programmable 4-bit I/O port (PORT6).
Input and output can be specified in single-bit units.
On-chip pull-up resistor connections are softwarespecifiable in 4-bit units.
Input
<F>-A
This is a 4-bit I/O port (PORT7).
On-chip pull-up resistor connections are softwarespecifiable in 4-bit units.
Input
<F>-A
Input
E-B
This is a 2-bit I/O port (PORT8).
On-chip pull-up resistor connections are softwarespecifiable in 2-bit units.
×
Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs.
2. Low-level input current leakage increases when input instructions or bit manipulation instructions are executed.
7
µPD75P0116
3.2 Non-port Pins
Pin name
I/O
Shared by
Function
When
reset
I/O circuit
type Note 1
TI0
I
P13
External event pulse input to timer/event counter
Input
<B>-C
PTO0
O
P20
Timer/event counter output
Input
E-B
P21
Timer counter output
Input
<F>-A
PTO1
PCL
P22
Clock output
BUZ
P23
Outputs any frequency (for buzzer or system clock trimming)
P01
Serial clock I/O
SO/SB0
P02
Serial data output
Serial data bus I/O
<F>-B
SI/SB1
P03
Serial data input
Serial data bus I/O
<M>-C
SCK
I/O
INT4
I
P00
Edge-triggered vectored interrupt input
(Detects both rising and falling edges).
INT0
I
P10
<B>
INT1
P11
Edge-triggered vectored interrupt input With noise eliminator
(detected edge is selectable).
/asynch selectable
INT0/P10 can select noise elimination
circuit.
Asynchronous
INT2
P12
Rising edge-triggered testable input
Input
<B>-C
Asynchronous
KR0-KR3
I
P60-P63
Falling edge-triggered testable input
Input
<F>-A
KR4-KR7
I
P70-P73
Falling edge-triggered testable input
Input
<F>-A
—
Resistor (R) and capacitor (C) connection for main system
clock oscillation. External clock cannot be input.
—
—
—
Crystal resonator connection for subsystem clock.
If using an external clock, input it to XT1 and input the inverted clock to X2. XT1 can be used as a 1-bit (test) input.
—
—
CL1
—
CL2
—
XT1
I
XT2
—
RESET
I
—
System reset input (low level active)
—
<B>
MD0-MD3
I
P30-P33
Mode selection for program memory (PROM) write/verify.
Input
E-B
I/O
P40-P43
Data bus pin for program memory (PROM) write/verify.
Input
M-E
D0-D3
D4-D7
P50-P53
VPP Note 2
—
—
Programmable voltage supply in program memory (PROM)
write/verify mode.
In normal operation mode, connect directly to VDD.
Apply +12.5 V in PROM write/verify mode.
—
—
VDD
—
—
Positive power supply
—
—
VSS
—
—
Ground potential
—
—
Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs.
2. During normal operation, the VPP pin will not operate normally unless connected to VDD pin.
8
µPD75P0116
3.3 I/O Circuits for Pins
The I/O circuits for the µPD75P0116’s pin are shown in schematic diagrams below.
(1/2)
TYPE A
TYPE D
VDD
VDD
Data
P-ch
OUT
P-ch
IN
Output
disable
N-ch
CMOS standard input buffer
TYPE B
N-ch
Push-pull output that can be set to high impedance output
(with both P-ch and N-ch OFF).
TYPE E-B
VDD
P.U.R.
P.U.R.
enable
IN
P-ch
Data
IN/OUT
Type D
Output
disable
Type A
Schmitt trigger input with hysteresis characteristics.
P.U.R. : Pull-Up Resistor
TYPE B-C
TYPE F-A
VDD
VDD
P.U.R.
P-ch
P.U.R.
P.U.R.
enable
P.U.R.
enable
P-ch
Data
IN/OUT
Type D
IN
Output
disable
P.U.R. : Pull-Up Resistor
Type B
P.U.R. : Pull-Up Resistor
9
µPD75P0116
(2/2)
TYPE F-B
TYPE M-E
VDD
IN/OUT
P.U.R.
P.U.R.
enable
output
disable
(P)
P-ch
data
output
disable
VDD
VDD
P-ch
IN/OUT
Input
instruction
data
P-ch
P.U.R.Note
output
disable
N-ch
Voltage
limitation
(+13 V)
circuit
output
disable
(N)
Note
P.U.R. : Pull-Up Resistor
TYPE M-C
VDD
P.U.R.
P.U.R.
enable
P-ch
IN/OUT
data
N-ch
output
disable
P.U.R. : Pull-Up Resistor
10
N-ch
(+13 V)
Pull-up resistor that operates only when an input
instruction has been executed. (Current flows
from VDD to the pins when at low level)
µPD75P0116
3.4 Handling of Unused Pins
Table 3-1. Handling of Unused Pins
Pin
Recommended connection
P00/INT4
Connect to VSS or VDD
P01/SCK
Individually connect to VSS or VDD via resistor
P02/SO/SB0
P03/SI/SB1
Connect to VSS
P10/INT0-P12/INT2
Connect to VSS or VDD
P13/TI0
P20/PTO0
P21/PTO1
Input mode
: individually connect to VSS or VDD
via resistor
Output mode : open
P22/PCL
P23/BUZ
P30/MD0-P33/MD3
P40/D0-P43/D3
Connect to VSS
P50/D4-P53/D7
P60/KR0-P63/KR3
P70/KR4-P73/KR7
Input mode
: individually connect to VSS or VDD
via resistor
Output mode : open
P80, P81
XT1Note
Note
Connect to VSS or VDD
XT2
Open
VPP
Make sure to connect directly to VDD
Note When the subsystem clock is not used, set SOS. 0 to 1 (not to use the internal feedback resistor).
11
µPD75P0116
4. SWITCHING BETWEEN MK I AND MK II MODES
Setting a stack bank selection (SBS) register for the µPD75P0116 enables the program memory to be switched
between the Mk I mode and the Mk II mode. This capability enables the evaluation of the µPD750104, 750106, or 750108
using the µPD75P0116.
When the SBS bit 3 is set to 1: sets Mk I mode (corresponds to Mk I mode of µPD750104, 750106, and 750108)
When the SBS bit 3 is set to 0: sets Mk II mode (corresponds to Mk II mode of µPD750104, 750106, and 750108)
4.1 Differences between Mk I Mode and Mk II Mode
Table 4-1 lists the differences between the Mk I mode and the Mk II mode of the µPD75P0116.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Item
Mk I mode
Mk II mode
Program counter
PC13-0
Program memory (bytes)
16384
Data memory (bits)
512 × 4
Stack
Stack bank
Selectable from memory banks 0 and 1
Stack bytes
2 bytes
3 bytes
Instruction
BRA !addr1
CALLA !addr1
None
Provided
Instruction
CALL !addr
3 machine cycles
4 machine cycles
execution time CALLF !faddr
2 machine cycles
3 machine cycles
Supported mask ROM versions and
mode
Mk I mode of µPD750104, 750106, and
750108
Mk II mode of µPD750104, 750106, and
750108
Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This
mode enhances the software compatibility with products which have more than 16K bytes.
When the Mk II mode is selected, the number of stack bytes (usable area) used in execution of a
subroutine call instruction increases by 1 per stack compared to the Mk I mode. Furthermore, when
a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle.
Therefore, when more importance is attached to RAM utilization or throughput than software
compatibility, use the Mk I mode.
12
µPD75P0116
4.2 Setting of Stack Bank Selection (SBS) Register
Use the stack bank selection register to switch between the Mk I mode and the Mk II mode. Figure 4-1 shows the format
for doing this.
The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode,
be sure to initialize the stack bank selection register to 100×B Note at the beginning of the program. When using the Mk
II mode, be sure to initialize it to 000×B Note.
Note Set the desired value for ×.
Figure 4-1. Format of Stack Bank Selection Register
Address
F84H
3
2
1
0
SBS3
SBS2
SBS1
SBS0
Symbol
SBS
Stack area specification
0
0
Memory bank 0
0
1
Memory bank 1
1
0
1
1
0
Setting prohibited
Be sure to set 0 for bit 2.
Mode selection specification
0
Mk II mode
1
Mk I mode
Caution SBS3 is set to “1” after RESET input, and consequently the CPU operates in the Mk I mode. When using
instructions for the Mk II mode, set SBS3 to “0” to enter the Mk II mode before using the instructions.
13
µPD75P0116
5. DIFFERENCES BETWEEN µPD75P0116 AND µPD750104, 750106, AND 750108
The µPD75P0116 replaces the internal mask ROM in the µPD750104, 750106, and 750108 with a one-time PROM
and features expanded ROM capacity. The µPD75P0116’s Mk I mode supports the Mk I mode in the µPD750104, 750106,
and 750108 and the µPD75P0116’s Mk II mode supports the Mk II mode in the µPD750104, 750106, and 750108.
Table 5-2 lists differences among the µPD75P0116 and the µPD750104, 750106, and 750108. Be sure to check the
differences between corresponding versions beforehand, especially when a PROM version is used for debugging or
prototype testing of application systems and later the corresponding mask ROM version is used for full-scale production.
Please refer to the µPD750108 User's Manual (U11330E) for details on CPU functions and on-chip hardware.
Table 5-1. Differences between µPD75P0116 and µPD750104, 750106, and 750108
µPD750104
Item
µPD750106
Program counter
12-bit
13-bit
Program memory (bytes)
Mask ROM
4096
Mask ROM
6144
Data memory (× 4 bits)
512
Mask options
Yes (On-chip/not on-chip can be specified.)
Pin connection
Pull-up resistor for
port 4 and port 5
µPD750108
µPD75P0116
14-bit
Mask ROM
8192
One-time PROM
16384
No (On-chip not
possible)
Wait time when
Yes (29/fCC or none) Note
releasing STOP mode
by interrupt generation
No (fixed at 29/fCC) Note
Feedback resistor
for subsystem clock
Yes (can select usable or unusable.)
No (usable)
Pins 6-9 (CU)
P33-P30
P33/MD3-P30/MD0
IC
VPP
P53-P50
P53/D7-P50/D4
P43-P40
P43/D3-P40/D0
Pins 23-26 (GB)
Pin 20 (CU)
Pin 38 (GB)
Pins 34-37 (CU)
Pins 8-11 (GB)
Pins 38-41 (CU)
Pins 13-16 (GB)
Other
Noise resistance and noise radiation may differ due to the different circuit complexities and
mask layouts.
Note 29/fCC : 256 µs at 2.0 MHz, 512 µs at 1.0 MHz
Caution Noise resistance and noise radiation are different in PROM version and mask ROM versions. If using
a mask ROM version instead of the PROM version for processes between prototype development and
full production, be sure to fully evaluate the CS of the mask ROM version (not ES).
14
µPD75P0116
6. MEMORY CONFIGURATION
Figure 6-1. Program Memory Map
0000H
7
6
MBE
RBE
0
Internal reset start address (higher 6 bits)
Internal reset start address (lower 8 bits)
0002H
MBE
RBE
INTBT/INT4 start address (higher 6 bits)
INTBT/INT4 start address (lower 8 bits)
0004H
MBE
RBE
INT0 start address (higher 6 bits)
CALLF
!faddr instruction
entry address
INT0 start address (lower 8 bits)
0006H
MBE
RBE
INT1 start address (higher 6 bits)
INT1 start address (lower 8 bits)
0008H
MBE
RBE
INTCSI start address (higher 6 bits)
BRCB
!caddr instruction
branch address
INTCSI start address (lower 8 bits)
000AH
MBE
RBE
INTT0 start address (higher 6 bits)
INTT0 start address (lower 8 bits)
000CH
MBE
RBE
INTT1 start address (higher 6 bits)
INTT1 start address (lower 8 bits)
Branch address for
the following instructions
• BR BCDE
• BR BCXA
• BR !addr
• CALL !addr
• BRA !addr1Note
• CALLA !addr1 Note
Branch/call
address
by GETI
0020H
Reference table for GETI instruction
007FH
0080H
BR $addr instruction
relative branch address
(–15 to –1,
+2 to +16)
07FFH
0800H
0FFFH
1000H
BRCB
!caddr instruction
branch address
1FFFH
2000H
BRCB
!caddr instruction
branch address
2FFFH
3000H
BRCB
!caddr instruction
branch address
3FFFH
Note Can be used only at Mk II mode.
Remark
For instructions other than those noted above, the “BR PCDE” and “BR PCXA” instructions can be used to
branch to addresses with changes in the PC’s lower 8 bits only.
15
µPD75P0116
Figure 6-2. Data Memory Map
Data memory
General
register
area
Memory bank
000H
(32 × 4)
01FH
020H
Stack area Note
256 × 4
0
(224 × 4)
Data area
static RAM
(512 × 4)
0FFH
100H
256 × 4
1
1FFH
Unimplemented
F80H
128 × 4
Peripheral hardware area
FFFH
Note For the stack area, one memory bank can be selected from memory bank 0 or 1.
16
15
µPD75P0116
7. INSTRUCTION SET
(1) Representation and coding formats for operands
In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s
operand representations (for further description, refer to the RA75X Assembler Package User’s Manual - Language
(EEU-1363)). When there are several codes, select and use just one. Upper-case letters, and + and – symbols are key
words that should be entered as they are.
For immediate data, enter an appropriate numerical value or label.
Instead of mem, fmem, pmem, bit, etc, a register flag symbol can be described as a label descriptor. (For further
description, refer to the µPD750108 User's Manual (U11330E)) Labels that can be entered for fmem and pmem are
restricted.
Representation
Coding format
reg
X, A, B, C, D, E, H, L
reg1
X, B, C, D, E, H, L
rp
XA, BC, DE, HL
rp1
BC, DE, HL
rp2
BC, DE
rp’
XA, BC, DE, HL, XA’, BC’, DE’, HL’
rp’1
BC, DE, HL, XA’, BC’, DE’, HL’
rpa
HL, HL+, HL–, DE, DL
rpa1
DE, DL
n4
4-bit immediate data or label
n8
8-bit immediate data or label
mem
8-bit immediate data or label Note
bit
2-bit immediate data or label
fmem
FB0H-FBFH, FF0H-FFFH immediate data or label
pmem
FC0H-FFFH immediate data or label
addr
0000H-3FFFH immediate data or label
addr1
0000H-3FFFH immediate data or label (in Mk II mode only)
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H-7FH immediate data (however, bit0 = 0) or label
PORTn
PORT0-PORT8
IEXXX
IEBT, IECSI, IET0, IET1, IE0-IE2, IE4, IEW
RBn
RB0-RB3
MBn
MB0, MB1, MB15
Note When processing 8-bit data, only even addresses can be specified.
17
µPD75P0116
(2) Operation legend
A
: A register; 4-bit accumulator
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
X
: X register
XA
: Register pair (XA); 8-bit accumulator
BC
: Register pair (BC)
DE
: Register pair (DE)
HL
: Register pair (HL)
XA’
: Expansion register pair (XA’)
BC’
: Expansion register pair (BC’)
DE’
: Expansion register pair (DE’)
HL’
: Expansion register pair (HL’)
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag; bit accumulator
PSW
: Program status word
MBE
: Memory bank enable flag
RBE
: Register bank enable flag
PORTn : Port n (n = 0 to 8)
18
IME
: Interrupt master enable flag
IPS
: Interrupt priority select register
IE×××
: Interrupt enable flag
RBS
: Register bank select register
MBS
: Memory bank select register
PCC
: Processor clock control register
.
: Delimiter for address and bit
(××)
: Contents of address ××
××H
: Hexadecimal data
µPD75P0116
(3) Description of symbols used in addressing area
MB = MBE • MBS
*1
MBS = 0, 1, 15
*2
MB = 0
MBE = 0
: MB = 0 (000H-07FH)
MB = 15 (F80H-FFFH)
*3
MBE = 1
Data memory
addressing
: MB = MBS
MBS = 0, 1, 15
*4
MB = 15, fmem = FB0H-FBFH, FF0H-FFFH
*5
MB = 15, pmem = FC0H-FFFH
*6
addr = 0000H-3FFFH
addr, addr1 = (Current PC) –15 to (Current PC) –1
*7
(Current PC) +2 to (Current PC) +16
caddr = 0000H-0FFFH (PC13, 12 = 00B) or
1000H-1FFFH (PC13, 12 = 01B) or
*8
Program memory
addressing
2000H-2FFFH (PC13, 12 = 10B) or
3000H-3FFFH (PC13, 12 = 11B)
*9
faddr = 0000H-07FFH
*10
taddr = 0020H-007FH
*11
addr1 = 0000H-3FFFH (Mk II mode only)
Remarks 1. MB indicates access-enabled memory banks.
2. In area *2, MB = 0 for both MBE and MBS.
3. In areas *4 and *5, MB = 15 for both MBE and MBS.
4. Areas *6 to *11 indicate corresponding address-enabled areas.
19
µPD75P0116
(4) Description of machine cycles
S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as
shown below.
• No skip .......................................................................... S = 0
• Skipped instruction is 1-byte or 2-byte instruction ......... S = 1
• Skipped instruction is 3-byte instruction Note ................. S = 2
Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1
Caution
The GETI instruction is skipped for one machine cycle.
One machine cycle equals one cycle (= tCY) of the CPU clock Φ. Use the PCC setting to select among four cycle times.
20
µPD75P0116
Group
Transfer
Mnemonic
MOV
XCH
Table
reference
MOVT
Operand
No. of Machine
bytes cycle
Operation
Addressing
area
Skip
condition
A, # n4
1
1
A ← n4
reg1, # n4
2
2
reg1 ← n4
XA, # n8
2
2
XA ← n8
String-effect A
HL, # n8
2
2
HL ← n8
String-effect B
rp2, # n8
2
2
rp2 ← n8
A, @HL
1
1
A ← (HL)
A, @HL+
1
2 + S A ← (HL), then L ← L + 1
*1
L=0
A, @HL–
1
2 + S A ← (HL), then L ← L – 1
*1
L = FH
A, @rpa1
1
1
A ← (rpa1)
*2
XA, @HL
2
2
XA ← (HL)
*1
@HL, A
1
1
(HL) ← A
*1
@HL, XA
2
2
(HL) ← XA
*1
A, mem
2
2
A ← (mem)
*3
XA, mem
2
2
XA ← (mem)
*3
mem, A
2
2
(mem) ← A
*3
mem, XA
2
2
(mem) ← XA
*3
A, reg
2
2
A ← reg
XA, rp’
2
2
XA ← rp’
reg1, A
2
2
reg1 ← A
rp’1, XA
2
2
rp’1 ← XA
A, @HL
1
1
A ↔ (HL)
A, @HL+
1
2 + S A ↔ (HL), then L ← L + 1
*1
L=0
A, @HL–
1
2 + S A ↔ (HL), then L ← L – 1
*1
L = FH
A, @rpa1
1
1
A ↔ (rpa1)
*2
XA, @HL
2
2
XA ↔ (HL)
*1
A, mem
2
2
A ↔ (mem)
*3
XA, mem
2
2
XA ↔ (mem)
*3
A, reg1
1
1
A ↔ reg1
XA, rp’
2
2
XA ↔ rp’
XA, @PCDE
1
3
XA ← (PC13-8 + DE)ROM
XA, @PCXA
1
3
XA ← (PC13-8 + XA)ROM
XA, @BCDE
1
3
XA ← (BCDE)ROM Note
*6
3
XA ←
*6
XA, @BCXA
1
(BCXA)ROM Note
String-effect A
*1
*1
Note As for the B register, only the lower 2 bits are valid.
21
µPD75P0116
Group
Bit transfer
Operation
Mnemonic
MOV1
ADDS
ADDC
SUBS
SUBC
AND
OR
XOR
22
Operand
No. of Machine
bytes cycle
Operation
Addressing
area
Skip
condition
CY, fmem.bit
2
2
CY ← (fmem.bit)
*4
CY, [email protected]
2
2
CY ← (pmem7-2 + L3-2.bit(L1-0))
*5
CY, @H + mem.bit
2
2
CY ← (H + mem3-0.bit)
*1
fmem.bit, CY
2
2
(fmem.bit) ← CY
*4
[email protected], CY
2
2
(pmem7-2 + L3-2.bit(L1-0)) ← CY
*5
@H + mem.bit, CY
2
2
(H + mem3-0.bit) ← CY
*1
A, #n4
1
1 + S A ← A + n4
carry
XA, #n8
2
2 + S XA ← XA + n8
carry
A, @HL
1
1 + S A ← A + (HL)
XA, rp’
2
2 + S XA ← XA + rp’
carry
rp’1, XA
2
2 + S rp’1 ← rp’1 + XA
carry
A, @HL
1
1
A, CY ← A + (HL) + CY
XA, rp’
2
2
XA, CY ← XA + rp’ + CY
rp’1, XA
2
2
rp’1, CY ← rp’1 + XA + CY
A, @HL
1
1 + S A ← A – (HL)
XA, rp’
2
2 + S XA ← XA – rp’
borrow
rp’1, XA
2
2 + S rp’1 ← rp’1 – XA
borrow
A, @HL
1
1
A, CY ← A – (HL) – CY
XA, rp’
2
2
XA, CY ← XA – rp’ – CY
rp’1, XA
2
2
rp’1, CY ← rp’1 – XA – CY
A, #n4
2
2
A ← A ^ n4
A, @HL
1
1
A ← A ^ (HL)
XA, rp’
2
2
XA ← XA ^ rp’
rp’1, XA
2
2
rp’1 ← rp’1 ^ XA
A, #n4
2
2
A ← A v n4
A, @HL
1
1
A ← A v (HL)
XA, rp’
2
2
XA ← XA v rp’
rp’1, XA
2
2
rp’1 ← rp’1 v XA
A, #n4
2
2
A ← A v n4
A, @HL
1
1
A ← A v (HL)
XA, rp’
2
2
XA ← XA v rp’
rp’1, XA
2
2
rp’1 ← rp’1 v XA
*1
carry
*1
*1
*1
*1
*1
*1
borrow
µPD75P0116
Group
Mnemonic
Operand
No. of Machine
bytes cycle
Operation
Addressing
area
Skip
condition
Accumulator
RORC
A
1
1
CY ← A0, A3 ← CY, An-1 ← An
manipulate
NOT
A
2
2
A←A
Increment/
INCS
reg
1
1 + S reg ← reg + 1
reg = 0
rp1
1
1 + S rp1 ← rp1 + 1
rp1 = 00H
@HL
2
2 + S (HL) ← (HL) + 1
*1
(HL) = 0
mem
2
2 + S (mem) ← (mem) + 1
*3
(mem) = 0
reg
1
1 + S reg ← reg – 1
reg = FH
rp’
2
2 + S rp’ ← rp’ – 1
rp’ = FFH
reg, #n4
2
2 + S Skip if reg = n4
reg = n4
@HL, #n4
2
2 + S Skip if (HL) = n4
*1
(HL) = n4
A, @HL
1
1 + S Skip if A = (HL)
*1
A = (HL)
XA, @HL
2
2 + S Skip if XA = (HL)
*1
XA = (HL)
A, reg
2
2 + S Skip if A = reg
A = reg
XA, rp’
2
2 +S
XA = rp’
decrement
DECS
Compare
SKE
Skip if XA = rp’
Carry flag
SET1
CY
1
1
CY ← 1
manipulate
CLR1
CY
1
1
CY ← 0
SKT
CY
1
NOT1
CY
1
1 + S Skip if CY = 1
1
CY = 1
CY ← CY
23
µ PD75P0116
Group
Memory bit
Mnemonic
SET1
manipulate
CLR1
SKT
SKF
SKTCLR
AND1
OR1
XOR1
24
Operand
No. of Machine
bytes cycle
Operation
Addressing
area
mem.bit
2
2
(mem.bit) ← 1
*3
fmem.bit
2
2
(fmem.bit) ← 1
*4
[email protected]
2
2
(pmem7-2 + L3-2.bit(L1-0)) ← 1
*5
@H + mem.bit
2
2
(H + mem3-0.bit) ← 1
*1
mem.bit
2
2
(mem.bit) ← 0
*3
fmem.bit
2
2
(fmem.bit) ← 0
*4
[email protected]
2
2
(pmem7-2 + L3-2.bit(L1-0)) ← 0
*5
@H + mem.bit
2
2
(H + mem3-0.bit) ← 0
*1
Skip
condition
mem.bit
2
2 + S Skip if(mem.bit) = 1
*3
(mem.bit) = 1
fmem.bit
2
2 + S Skip if(fmem.bit) = 1
*4
(fmem.bit) = 1
[email protected]
2
2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 1
*5
([email protected]) = 1
@H + mem.bit
2
2 + S Skip if(H + mem3-0.bit) = 1
*1
(@H + mem.bit) = 1
mem.bit
2
2 + S Skip if(mem.bit) = 0
*3
(mem.bit) = 0
fmem.bit
2
2 + S Skip if(fmem.bit) = 0
*4
(fmem.bit) = 0
[email protected]
2
2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 0
*5
([email protected]) = 0
@H + mem.bit
2
2 + S Skip if(H + mem3-0.bit) = 0
*1
(@H + mem.bit) = 0
fmem.bit
2
2 + S Skip if(fmem.bit) = 1 and clear
*4
(fmem.bit) = 1
[email protected]
2
2 + S Skip if(pmem7-2 + L3-2.bit (L1-0)) = 1 and clear
*5
([email protected]) = 1
@H + mem.bit
2
2 + S Skip if(H + mem3-0 .bit) = 1 and clear
*1
(@H + mem.bit) = 1
CY, fmem.bit
2
2
CY ← CY ^ (fmem.bit)
*4
CY, [email protected]
2
2
CY ← CY ^ (pmem7-2 + L3-2.bit(L1-0))
*5
CY, @H + mem.bit
2
2
CY ← CY ^ (H + mem3-0.bit)
*1
CY, fmem.bit
2
2
CY ← CY v (fmem.bit)
*4
CY, [email protected]
2
2
CY ← CY v (pmem 7-2 + L3-2.bit(L1-0))
*5
CY, @H + mem.bit
2
2
CY ← CY v (H + mem 3-0.bit)
*1
CY, fmem.bit
2
2
CY ← CY v (fmem.bit)
*4
CY, [email protected]
2
2
CY ← CY v (pmem 7-2 + L3-2.bit(L1-0))
*5
CY, @H + mem.bit
2
2
CY ← CY v (H + mem 3-0.bit)
*1
µPD75P0116
Group
Branch
Mnemonic
BR Note 1
Operand
No. of Machine
bytes cycle
Operation
Addressing
area
addr
—
—
PC13-0 ← addr
Assembler selects the most
appropriate instruction among
the following:
• BR !addr
• BRCB !caddr
• BR $addr
*6
addr1
—
—
PC13-0 ← addr1
Assembler selects the most
appropriate instruction among
the following:
• BRA !addr1
• BR !addr
• BRCB !caddr
• BR $addr1
*11
!addr
3
3
PC13-0 ← addr
*6
$addr
1
2
PC13-0 ← addr
*7
$addr1
1
2
PC13-0 ← addr1
PCDE
2
3
PC13-0 ← PC13-8 + DE
PCXA
2
3
PC13-0 ← PC13-8 + XA
BCDE
2
3
PC13-0 ← BCDE Note 2
*6
BCXA
2
3
PC13-0 ← BCXA Note 2
*6
BRA Note 1
!addr1
3
3
PC13-0 ← addr1
*11
BRCB
!caddr
2
2
PC13-0 ← PC13, 12 + caddr11-0
*8
Skip
condition
Notes 1. Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.
2. As for the B register, only the lower 2 bits are valid.
25
µPD75P0116
Group
Subroutine
Mnemonic
Operand
CALLA Note !addr1
No. of Machine
bytes cycle
3
3
Operation
(SP – 5) ← 0, 0, PC13,12
Addressing
area
Skip
condition
*11
(SP – 6)(SP – 3)(SP – 4) ← PC11-0
stack control
(SP – 2) ← ×, ×, MBE, RBE
PC13–0 ← addr1, SP ← SP – 6
CALL Note
!addr
3
3
(SP – 4)(SP – 1)(SP – 2) ← PC11-0
*6
(SP – 3) ← (MBE, RBE, PC13, 12)
PC13–0 ← addr, SP ← SP – 4
4
(SP – 5) ← 0, 0, PC13,12
(SP – 6)(SP – 3)(SP – 4) ← PC11-0
(SP – 2) ← ×, ×, MBE, RBE
PC13-0 ← addr, SP ← SP – 6
CALLF Note !faddr
2
2
(SP – 4)(SP – 1)(SP – 2) ← PC11-0
*9
(SP – 3) ← (MBE, RBE, PC13, 12)
PC13-0 ← 000 + faddr, SP ← SP – 4
3
(SP – 5) ← 0, 0, PC13,12
(SP – 6)(SP – 3)(SP – 4) ← PC11-0
(SP – 2) ← ×, ×, MBE, RBE
PC13-0 ← 000 + faddr,SP ← SP – 6
RET Note
1
3
(MBE, RBE, PC13, 12) ← (SP + 1)
PC11-0 → (SP)(SP + 3)(SP + 2)
SP ← SP + 4
×, ×, MBE, RBE ← (SP + 4)
0, 0, PC13-12 ← (SP + 1)
PC11-0 ← (SP)(SP + 3)(SP + 2)
SP ← SP + 6
RETS Note
1
3 + S (MBE, RBE, PC13, 12) ← (SP + 1)
Unconditional
PC11-0 ← (SP)(SP + 3)(SP + 2)
SP ← SP + 4
then skip unconditionally
×, ×, MBE, RBE ← (SP + 4)
0, 0, PC13-12 ← (SP + 1)
PC11-0 ← (SP)(SP + 3)(SP + 2)
SP ← SP + 6
then skip unconditionally
RETI Note
1
3
MBE, RBE, PC13, 12 ← (SP + 1)
PC11-0 ← (SP)(SP + 3)(SP + 2)
PSW ← (SP + 4)(SP + 5), SP ← SP + 6
0, 0, PC13, 12 ← (SP + 1)
PC11-0 ← (SP)(SP + 3)(SP + 2)
PSW ← (SP + 4)(SP + 5), SP ← SP + 6
Note Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.
26
µPD75P0116
Group
Subroutine
Mnemonic
PUSH
stack control
POP
Interrupt
Operand
1
(SP – 1)(SP – 2) ← rp, SP ← SP – 2
BS
2
2
(SP – 1) ← MBS, (SP – 2) ← RBS, SP ← SP – 2
rp
1
1
rp ← (SP + 1)(SP), SP ← SP + 2
BS
2
2
MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2
2
2
IME(IPS.3) ← 1
2
2
IE××× ← 1
2
2
IME(IPS.3) ← 0
IE×××
2
2
IE××× ← 0
A, PORTn
2
2
A ← PORTn
DI
I/O
2
2
XA ← PORTn+1, PORTn
(n = 4, 6)
2
PORTn ← A
(n = 2 - 8)
2
2
PORTn+1, PORTn ← XA
(n = 4, 6)
HALT
2
2
Set HALT Mode(PCC.2 ← 1)
STOP
2
2
Set STOP Mode(PCC.3 ← 1)
NOP
1
1
No Operation
RBn
2
2
RBS ← n
(n = 0 - 3)
MBn
2
2
MBS ← n
(n = 0, 1, 15)
taddr
1
3
• When using TBR instruction
PORTn, XA
Special
SEL
GETI Note 2, 3
PC
← (taddr)
Skip
condition
(n = 0 - 8)
2
XA, PORTn
OUT Note 1 PORTn, A
CPU control
Addressing
area
1
IE×××
IN Note 1
Operation
rp
EI
control
No. of Machine
bytes cycle
*10
+ (taddr + 1)
13-0
5-0
- - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -
• When using TCALL instruction
(SP – 4)(SP – 1)(SP – 2) ← PC11-0
(SP – 3) ← MBE, RBE, PC13, 12
PC13-0 ← (taddr)5-0 + (taddr + 1)
SP ← SP – 4
- - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -
• When using instruction other than
TBR or TCALL
Execute (taddr)(taddr + 1) instructions
1
3
• When using TBR instruction
PC
← (taddr)
Determined by
referenced
instruction
*10
+ (taddr + 1)
13-0
5-0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4
• When using TCALL instruction
(SP – 5) ← 0, 0, PC13, 12
(SP – 6)(SP – 3)(SP – 4) ← PC11-0
(SP – 2) ← ×, ×, MBE, RBE
PC13-0 ← (taddr)5-0 + (taddr + 1)
SP ← SP – 6
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3
• When using instruction other than
TBR or TCALL
Execute (taddr)(taddr + 1) instructions
Determined by
referenced
instruction
Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15.
2. TBR and TCALL are assembler directives for the GETI instruction’s table definitions.
3. Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.
27
µPD75P0116
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY
The program memory in the µPD75P0116 is a 16384 × 8-bit electronic write-enabled one-time PROM. The pins listed
in the table below are used for this PROM’s write/verify operations. Clock input from the CL1 pins is used instead of
address input as a method for updating addresses.
Pin name
Function
VPP
Pin (usually VDD) where programming voltage is applied during
program memory write/verify
CL1, CL2
Clock input to the CL1 pin for address updating during program
memory write/verify. Leave the CL2 pin open.
MD0/P30-MD3/P33
Operation mode selection pin for program memory write/verify
D0/P40-D3/P43 (lower 4) 8-bit data I/O pin for program memory write/verify
D4/P50-D7/P53 (higher 4)
VDD
Pin where power supply voltage is applied. Power voltage
range for normal operation is 1.8 to 5.5 V. Apply 6.0 V for
program memory write/verify.
Caution Pins not used for program memory write/verify should be processed as follows.
• All unused pins except XT2 ...... Connect to Vss via a pull-down resistor
• XT2 pin ........................................ Leave open
8.1 Operation Modes for Program Memory Write/Verify
When +6 V is applied to the µPD75P0116’s VDD pin and +12.5 V is applied to its VPP pin, program write/verify modes
are in effect. Furthermore, the following detailed operation modes can be specified by setting pins MD0 to MD3 as shown
below.
Operation mode specification
VPP
VDD
MD0
MD1
MD2
MD3
+12.5 V
+6 V
H
L
H
L
Zero-clear program memory address
L
H
H
H
Write mode
L
L
H
H
Verify mode
H
×
H
H
Program inhibit mode
Remark ×: L or H
28
Operation mode
µPD75P0116
8.2 Steps in Program Memory Write Operation
High-speed program memory write can be executed via the following steps.
(1) Pull down unused pins to VSS via resistors. Set the CL1 pin to low.
(2) Apply +5 V to the VDD and VPP pins.
(3) Wait 10 µs.
(4) Zero-clear mode for program memory addresses.
(5) Apply +6 V to VDD and +12.5 V power to VPP.
(6) Write data using 1-ms write mode.
(7) Verify mode. If write is verified, go to step (8) and if write is not verified, go back to steps (6) and (7).
(8) X [= number of write operations from steps (6) and (7)] × 1 ms additional write
(9) 4 pulse inputs to the CL1 pin updates (increments +1) the program memory address.
(10) Repeat steps (6) to (9) until the last address is completed.
(11) Zero-clear mode for program memory addresses.
(12) Apply +5 V to the VDD and VPP pins.
(13) Power supply OFF
The following diagram illustrates steps (2) to (9).
X repetitions
Write
Verify
Additional
write
Address increment
VPP
VPP
VDD
VDD + 1
VDD
VDD
CL1
D0/P40-D3/P43
D4/P50-D7/P53
Data input
Data output
Data input
MD0/P30
MD1/P31
MD2/P32
MD3/P33
29
µPD75P0116
8.3 Steps in Program Memory Read Operation
The µPD75P0116 can read out the program memory contents via the following steps.
(1) Pull down unused pins to VSS via resistors. Set the CL1 pin to low.
(2) Apply +5 V to the VDD and VPP pins.
(3) Wait 10 µs.
(4) Zero-clear mode for program memory addresses.
(5) Apply +6 V power to VDD and +12.5 V to VPP.
(6) Verify mode. When a clock pulse is input to the CL1 pin, data is output sequentially to one address at a time based
on a cycle of four pulse inputs.
(7) Zero-clear mode for program memory addresses.
(8) Apply +5 V power to the VDD and VPP pins.
(9) Power supply OFF
The following diagram illustrates steps (2) to (7).
VPP
VPP
VDD
VDD + 1
VDD
VDD
CL1
D0/P40-D3/P43
D4/P50-D7/P53
Data output
MD0/P30
MD1/P31
“L”
MD2/P32
MD3/P33
30
Data output
µPD75P0116
8.4 One-Time PROM Screening
Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends
the screening process, that is, after the required data is written to the PROM and the PROM is stored under the hightemperature conditions shown below, the PROM should be verified.
Storage temperature
Storage time
125 ˚C
24 hours
31
µPD75P0116
9. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 ˚C)
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
V DD
–0.3 to + 7.0
V
PROM supply voltage
V PP
–0.3 to + 13.5
V
–0.3 to V DD + 0.3
V
–0.3 to + 14
V
Input voltage
V I1
Other than ports 4, 5
V I2
Ports 4, 5 (N-ch open drain)
Output voltage
VO
High-level output current
IOH
–0.3 to VDD + 0.3
V
Per pin
–10
mA
Low-level output current
IOL
Total of all pins
–30
mA
Per pin
30
mA
Operating ambient
temperature
TA
220
mA
–40 to + 85
˚C
Storage temperature
Tstg
–65 to + 150
˚C
Total of all pins
Caution If the absolute maximum rating of even one of the parameters is exceeded even momentarily,
the quality of the product may be degraded. The absolute maximum ratings are therefore values
which, when exceeded, can cause the product to be damaged. Be sure that these values are
never exceeded when using the product.
Capacitance (TA = 25 ˚C, V DD = 0 V)
Parameter
Input capacitance
Symbol
Conditions
CIN
f = 1 MHz
Output capacitance
COUT
Pins other than tested pins: 0 V
I/O capacitance
CIO
32
MIN.
TYP.
MAX.
Unit
15
pF
15
pF
15
pF
µPD75P0116
Main System Clock Oscillation Circuit Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Resonator
Recommended
constants
RC oscillation
CL1
Note
CL2
Parameter
Oscillation frequency
(f CC) Note
Conditions
MIN.
TYP.
0.4
MAX.
Unit
2.0
MHz
The oscillation frequency shown above indicates characteristics of the oscillation circuit only. For the
instruction execution time and oscillation frequency characteristics, refer to AC Characteristics.
Caution When using the main system clock oscillation circuit, wire the portion enclosed in the dotted
line in the above figure as follows to prevent adverse influences due to wiring capacitance:
· Keep the wiring length as short as possible.
· Do not cross the wiring with other signal lines.
· Do not route the wiring in the vicinity of a line through which a high alternating current flows.
· Always keep the ground point of the capacitor of the oscillation circuit at the same potential
as V DD .
Do not ground to a power supply pattern through which a high current flows.
· Do not extract signals from the oscillation circuit.
33
µPD75P0116
Subsystem Clock Oscillation Circuit Characteristics (TA = –40 to +85 ˚C, V DD = 1.8 to 5.5 V)
Recommended
constants
Resonator
Crystal
resonator
XT1
R
External
clock
C4
XT1
XT2
Conditions
Oscillation frequency
(f XT) Note 1
XT2
C3
Parameter
Oscillation
stabilization time Note 2
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.0
2
s
10
s
VDD = 4.5 to 5.5 V
XT1 input frequency
(f XT) Note 1
32
100
kHz
XT1 input high-,
low-level widths
(t XTH, t XTL)
5
15
µs
Notes 1. The oscillation frequency shown above indicate characteristics of the oscillation circuit only. For the
instruction execution time, refer to AC Characteristics.
2. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been
applied.
Caution When using the subsystem clock oscillation circuit, wire the portion enclosed in the dotted line
in the above figure as follows to prevent adverse influences due to wiring capacitance:
· Keep the wiring length as short as possible.
· Do not cross the wiring with other signal lines.
· Do not route the wiring in the vicinity of a line through which a high alternating current flows.
· Always keep the ground point of the capacitor of the oscillation circuit at the same potential
as V DD .
Do not ground to a power supply pattern through which a high current flows.
· Do not extract signals from the oscillation circuit.
The subsystem clock oscillation circuit has a low amplification factor to reduce current
dissipation and is more susceptible to noise than the main system clock oscillation circuit.
Therefore, exercise utmost care in wiring the subsystem clock oscillation circuit.
34
µPD75P0116
DC Characteristics (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)
Parameter
Low-level
Symbol
IOL
output current
High-level input
VIH1
Conditions
MAX.
Unit
Per pin
15
mA
Total of all pins
150
mA
Ports 2, 3, 8
voltage
VIH2
VIH3
Ports 0, 1, 6, 7, RESET
Ports 4, 5 (N-ch open drain)
MIN.
2.7 ≤ VDD ≤ 5.5 V
0.7 VDD
VDD
V
1.8 ≤ VDD ≤ 2.7 V
0.9 VDD
VDD
V
2.7 ≤ VDD ≤ 5.5 V
0.8 VDD
VDD
V
1.8 ≤ VDD ≤ 2.7 V
0.9 VDD
VDD
V
2.7 ≤ VDD ≤ 5.5 V
0.7 VDD
13
V
1.8 ≤ VDD ≤ 2.7 V
0.9 VDD
13
V
VIH4
XT1
VIL1
Ports 2-5, 8
VIL2
Ports 0, 1, 6, 7, RESET
VIL3
XT1
High-level output
voltage
VOH
SCK, SO, ports 2, 3, 6-8
IOH = –1.0 mA
Low-level output
VOL1
SCK, SO,
IOL = 15 mA, VDD = 5.0 V ± 10 %
ports 2-8
IOL = 1.6 mA
Low-level input
voltage
VDD–0.1
VDD
V
2.7 ≤ VDD ≤ 5.5 V
0
0.3 VDD
V
1.8 ≤ VDD ≤ 2.7 V
0
0.1 VDD
V
2.7 ≤ VDD ≤ 5.5 V
0
0.2 VDD
V
0
0.1 VDD
V
0
0.1
V
1.8 ≤ VDD ≤ 2.7 V
voltage
VOL2
SB0, SB1
TYP.
VDD–0.5
V
0.2
2.0
V
0.4
V
0.2 VDD
V
Pins other than XT1
3
µA
XT1
20
µA
N-ch open drain
Pull-up resistor ≥ 1 kΩ
High-level input
ILIH1
leakage current
ILIH2
Low-level input
leakage current
VIN = V DD
ILIH3
VIN = 13 V
Ports 4, 5 (N-ch open drain)
20
µA
ILIL1
VIN = 0 V
Pins other than ports 4, 5, XT1
–3
µA
–20
µA
–3
µA
–30
µA
ILIL2
XT1
ILIL3
Ports 4, 5 (N-ch open drain) When
input instruction is not executed
Ports 4, 5 (N-ch
open drain)
When input
VDD = 5.0 V
–10
–27
µA
VDD = 3.0 V
–3
–8
µA
instruction is
executed
High-level output
ILOH1
VOUT = VDD
3
µA
leakage current
ILOH2
VOUT = 13 V Ports 4, 5 (N-ch open drain)
20
µA
Low-level output
ILOL
VOUT = 0 V
–3
µA
RL
VIN = 0 V
200
kΩ
SCK, SO/SB0, SB1, Ports 2, 3, 6-8
leakage current
Internal pull-up
Ports 0-3, 6-8 (except P00 pin)
50
100
resistor
35
µPD75P0116
DC Characteristics (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)
Parameter
Supply
current Note 1
Symbol
IDD1
IDD2
Conditions
MAX.
Unit
0.9
1.8
mA
500
µA
370
920
µA
VDD = 3.0 V ± 10 %
170
340
µA
55.0
200
µA
22.0
70.0
µA
55.0
90.0
µA
50.0
150
µA
50.0
85.0
µA
5.0
30.0
µA
32.768
kHz Note 5
crystal
oscillation
VDD = 3.0 V ± 10 %
Lowvoltage
VDD = 2.0 V ± 10 %
mode Note 6
VDD = 3.0 V, TA = 25 ˚C
Low
VDD = 3.0 V ± 10 %
current
dissipation
mode Note 7 VDD = 3.0 V, T A = 25 ˚C
HALT
mode
IDD4
IDD5
TYP.
250
% Note 3
mode
IDD3
MIN.
1.0
VDD = 5.0 V ± 10
RC oscillation
VDD = 3.0 V ± 10 % Note 4
R = 22 kΩ,
C = 22 pF
VDD = 5.0 V ± 10 %
HALT
MHz Note 2
LowVDD = 3.0 V ± 10 %
voltage
VDD = 2.0 V ± 10 %
mode Note 6
2.5
10.0
µA
VDD = 3.0 V, T A = 25 ˚C
5.0
10.0
µA
Low current VDD = 3.0 V ± 10 %
consumption
mode Note 7 VDD = 3.0 V, T A = 25 ˚C
4.0
15.0
µA
4.0
7.0
µA
XT1 = 0V Note 8
VDD = 5.0 V ± 10 %
0.05
5.0
µA
STOP
mode
VDD = 3.0 V ± 10 %
0.02
2.5
µA
0.02
0.2
µA
TA = 25 ˚C
Notes 1. The current flowing through the internal pull-up resistor is not included.
2. Including the case when the subsystem clock oscillates.
3. When the device operates in high-speed mode with the processor clock control register (PCC) set to
0011.
4. When the device operates in low-speed mode with PCC set to 0000.
5. When the device operates on the subsystem clock, with the system clock control register (SCC) set to
1001 and oscillation of the main system clock stopped.
6. When the suboscillation circuit control register (SOS) is set to 0000.
7. When SOS is set to 0010.
8. When SOS is set to 00×1, and the suboscillation circuit feedback resistor is not used (×: don’t care).
36
µPD75P0116
AC Characteristics (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
128
µs
125
µs
CPU clock cycle
t CY
timeNote 1
(minimum instruction
execution time = 1
machine cycle)
Operates with main system clock
2.0
Operates with subsystem clock
114
TI0 input frequency
f TI
VDD = 2.7 to 5.5 V
0
1.0
MHz
0
275
kHz
TI0 high-, low-level
t TIH, t TIL
VDD = 2.7 to 5.5 V
0.48
µs
1.8
µs
IM02 = 0
Note 2
µs
IM02 = 1
10
µs
10
µs
10
µs
10
µs
widths
Interrupt input high-, t INTH,
low-level widths
INT0
t INTL
INT1, 2, 4
KR0-KR7
RESET low-level width
tRSL
RC oscillation
f CC
frequency
122
R = 22 kΩ,
VDD = 2.7 to 5.5 V
0.9
1.0
1.3
MHz
C = 22 pF
VDD = 1.8 to 5.5 V
0.55
1.0
1.3
MHz
Notes 1. The cycle time of the CPU clock (φ) (minimum instruction execution time) when the device operates with
the main system clock is determined by the time constant of the connected resistor (R) and capacitor
(C), and the value of the processor clock control register (PCC). When the device operates with the
subsystem clock, the cycle time of the CPU clock (φ) is determined by the oscillation frequency of the
connected oscillator (and external clock), and the values of the system clock control register (SCC) and
processor clock control register (PCC).
The figure on the below shows the supply voltage VDD vs. cycle time tCY characteristics when the device
operates with the main system clock.
2. 2t CY or 128/fCC depending on the setting of the interrupt mode register (IM0).
tCY vs VDD
(with main system clock)
128
6
5
Operation guaranteed range
Cycle time tCY (µs)
4
3
2
1
0.5
0
1
1.8 2
3
4
5 5.5 6
Supply voltage VDD [V]
37
µPD75P0116
Serial Transfer Operation
2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high-, low-level widths
Symbol
tKCY1
tKL1,
Conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
tKH1
SI Note 1
setup time
tSIK1
VDD = 2.7 to 5.5 V
(vs. SCK ↑)
SI Note 1 hold time
tKSI1
VDD = 2.7 to 5.5 V
(vs. SCK ↑)
SCK ↓ → SONote 1 output
tKSO1
delay time
Notes 1.
RL = 1 kΩNote 2
VDD = 2.7 to 5.5 V
CL = 100 pF
MIN.
TYP.
MAX.
Unit
1300
ns
3800
ns
tKCY1/2–50
ns
tKCY1/2–150
ns
150
ns
500
ns
400
ns
600
ns
0
250
ns
0
1000
ns
Read as SB0 or SB1 when using the 2-wire serial I/O mode.
RL and CL respectively indicate the load resistance and load capacitance of the SO output line.
2.
2-wire and 3-wire serial I/O modes (SCK ··· external clock input): (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high-, low-level widths
Symbol
tKCY2
tKL2,
Conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
tKH2
SI Note 1 setup time
tSIK2
VDD = 2.7 to 5.5 V
(vs. SCK ↑)
SI Note 1 hold time
tKSI2
VDD = 2.7 to 5.5 V
(vs. SCK ↑)
SCK ↓ → SONote 1 output
delay time
Notes 1.
2.
38
tKSO2
RL = 1 kΩ Note 2
VDD = 2.7 to 5.5 V
CL = 100 pF
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
150
ns
400
ns
600
ns
0
300
ns
0
1000
ns
Read as SB0 or SB1 when using the 2-wire serial I/O mode.
RL and CL respectively indicate the load resistance and load capacitance of the SO output line.
µPD75P0116
SBI mode (SCK ··· internal clock output (master)): (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high-, low-level widths
Symbol
tKCY3
tKL3
Conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
tKH3
SB0, 1 setup time
tSIK3
VDD = 2.7 to 5.5 V
(vs. SCK ↑)
SB0, 1 hold time (vs. SCK ↑)
tKSI3
SCK ↓ → SB0, 1 output
tKSO3
delay time
MIN.
TYP.
MAX.
1300
ns
3800
ns
tKCY3/2–50
ns
tKCY3/2–150
ns
150
ns
500
ns
t KCY3/2
RL = 1 kΩ Note
VDD = 2.7 to 5.5 V
CL = 100 pF
Unit
ns
0
250
0
1000
ns
ns
SCK ↑ → SB0, 1 ↓
tKSB
tKCY3
ns
SB0, 1 ↓ → SCK ↓
tSBK
tKCY3
ns
SB0, 1 low-level width
tSBL
tKCY3
ns
SB0, 1 high-level width
tSBH
tKCY3
ns
Note R L and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines.
SBI mode (SCK ··· external clock input (slave)): (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high-, low-level widths
Symbol
tKCY4
tKL4
Conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
tKH4
SB0, 1 setup time
tSIK4
VDD = 2.7 to 5.5 V
(vs. SCK ↑)
SB0, 1 hold time (vs. SCK ↑)
tKSI4
SCK ↓ → SB0, 1 output
tKSO4
delay time
MIN.
TYP.
MAX.
800
ns
3200
ns
400
ns
1600
ns
100
ns
150
ns
t KCY4/2
RL = 1 kΩ Note
CL = 100 pF
VDD = 2.7 to 5.5 V
Unit
ns
0
300
0
1000
ns
ns
SCK ↑ → SB0, 1 ↓
tKSB
tKCY4
ns
SB0, 1 ↓ → SCK ↓
tSBK
tKCY4
ns
SB0, 1 low-level width
tSBL
tKCY4
ns
SB0, 1 high-level width
tSBH
tKCY4
ns
Note R L and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines.
39
µPD75P0116
AC Timing Test Points (except XT1 input)
VIH (MIN.)
VIH (MIN.)
VIL (MAX.)
VIL (MAX.)
VOH (MIN.)
VOH (MIN.)
VOL (MAX.)
VOL (MAX.)
Clock timing
1/fXT
tXTL
tXTH
VDD – 0.1 V
XT1 input
0.1 V
TI0 timing
1/fTI
tTIL
TI0
40
tTIH
µPD75P0116
Serial Transfer Timing
3-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
tKSI1, 2
Input data
SI
tKSO1, 2
Output data
SO
2-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
tKSI1, 2
SB0, 1
tKSO1, 2
41
µPD75P0116
Serial Transfer Timing
Bus release signal transfer
tKCY3, 4
tKL3, 4
tKH3, 4
SCK
tKSB
tSBL
tSBH
tSIK3, 4
tSBK
SB0, 1
tKSO3, 4
Command signal transfer
tKCY3, 4
tKL3, 4
tKH3, 4
SCK
tKSB
tSIK3, 4
tSBK
SB0, 1
tKSO3, 4
Interrupt input timing
tINTL
tINTH
INT0, 1, 2, 4
KR0-7
RESET input timing
tRSL
RESET
42
tKSI3, 4
tKSI3, 4
µPD75P0116
Data Retention Characteristics of Data Memory in STOP Mode and at Low Supply Voltage
(TA = –40 to +85 ˚C)
Parameter
Symbol
Release signal setup time
tSREL
Oscillation stabilization
wait time Note 1
tWAIT
Note
Conditions
MIN.
TYP.
MAX.
Unit
µs
0
Released by RESET
56/fCC
µs
Released by interrupt request
512/fCC
µs
The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable
operation when oscillation is started.
Data retention timing (when STOP mode released by RESET)
Internal reset operation
HALT mode
STOP mode
Operation mode
Data retention mode
VDD
tSREL
STOP instruction execution
RESET
tWAIT
Data retention timing (standby release signal: when STOP mode released by interrupt signal)
HALT mode
STOP mode
Operation mode
Data retention mode
tSREL
VDD
STOP instruction execution
Standby release signal
(interrupt request)
tWAIT
43
µPD75P0116
DC Programming Characteristics (TA = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, V PP = 12.5 ± 0.3 V, V SS = 0V)
Parameter
Symbol
Input voltage, high
Input voltage, low
Conditions
MIN.
MAX.
Unit
VDD
V
VDD – 0.5
VDD
V
0
0.3 VDD
V
0
0.4
V
10
µA
V IH1
Other than CL1 pin
0.7 VDD
V IH2
CL1
V IL1
Other than CL1 pin
V IL2
CL1
Input leakage current
I LI
VIN = VIL or V IH
Output voltage, high
V OH
I OH = – 1 mA
Output voltage, low
V OL
I OL = 1.6 mA
VDD supply current
I DD
VPP supply current
I PP
TYP.
VDD – 1.0
V
MD0 = V IL, MD1 = VIH
0.4
V
30
mA
30
mA
Cautions 1. Keep V PP to within +13.5 V, including overshoot.
2. Apply V DD before VPP and turn it off after V PP.
AC Programming Characteristics (TA = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, V PP = 12.5 ± 0.3 V, VSS = 0 V)
Parameter
Symbol
Note 1
t AS
t AS
2
µs
MD1 setup time (vs. MD0 ↓)
t M1S
t OES
2
µs
Data setup time (vs. MD0 ↓)
t DS
t DS
2
µs
t AH
t AH
2
µs
Data hold time (vs. MD0 ↑)
t DH
t DH
2
MD0 ↑ → data output float
delay time
t DF
t DF
0
VPP setup time (vs. MD3 ↑)
t VPS
t VPS
2
VDD setup time (vs. MD3 ↑)
t VDS
t VCS
2
Initial program pulse width
tPW
tPW
0.95
Additional program pulse width
t OPW
t OPW
0.95
MD0 setup time (vs. MD1 ↑)
t M0S
t CES
2
MD0 ↓ → data output delay time
t DV
t DV
MD0 = MD1 = VIL
MD1 hold time (vs. MD0 ↑)
t M1H
t OEH
t M1H + tM1R ≥ 50 µs
MD1 recovery time (vs. MD0 ↓)
t M1R
tOR
Program counter reset time
t PCR
Address setup time
(vs. MD0 ↓)
Address hold time
(vs. MD0 ↑)
Note 2
Note 2
Conditions
MIN.
TYP.
MAX.
Unit
µs
130
ns
µs
µs
1.0
1.05
ms
21.0
ms
µs
1
µs
2
µs
2
µs
—
10
µs
CL1 input high-, low-level width t XH, tXL
—
0.125
CL1 input frequency
f CC
—
Initial mode set time
tI
—
2
µs
MD3 setup time (vs. MD1 ↑)
t M3S
—
2
µs
MD3 hold time (vs. MD1 ↓)
t M3H
—
2
µs
MD3 setup time (vs. MD0 ↓)
t M3SR
—
2
µs
When program memory is read
→ data output
t DAD
t ACC
When program memory is read
Address Note 2 → data output
hold time
t HAD
tOH
When program memory is read
0
MD3 hold time (vs. MD0 ↑)
t M3HR
—
When program memory is read
2
MD3 ↓ → data output float
delay time
t DFR
—
When program memory is read
Note 2
Address
delay time
Notes 1.
2.
MHz
2
µs
130
ns
µs
2
µs
Symbol of corresponding µPD27C256A
The internal address signal is incremented by one at the rising edge of the fourth CL1 input and is not
connected to a pin.
44
µs
4.19
µPD75P0116
Program Memory Write Timing
tVPS
VPP
VPP
VDD
VDD
VDD+1
VDD
tVDS
tXH
CL1
tXL
D0/P40-D3/P43
D4/P50-D7/P53
Data input
Data output
Data input
tDS
tI
tDS
tDH
tDV
Data input
tDH
tDF
tAH
tAS
MD0/P30
tPW
tM1R
tM0S
tOPW
MD1/P31
tPCR
tM1S
tM1H
MD2/P32
tM3S
tM3H
MD3/P33
Program Memory Read Timing
tVPS
VPP
VPP
VDD
tVDS
VDD+1
VDD
tXH
VDD
CL1
tXL
tDAD
tHAD
D0/P40-D3/P43
D4/P50-D7/P53
Data output
Data output
tDV
tI
tDFR
tM3HR
MD0/P30
MD1/P31
tPCR
MD2/P32
tM3SR
MD3/P33
45
µPD75P0116
10. CHARACTERISTICS CURVES (REFERENCE VALUE)
IDD vs VDD (Main system clock : 1.0 MHz RC oscillation)
(TA = 25 °C)
10
5.0
1.0
PCC = 0011
PCC = 0010
PCC = 0001
PCC = 0000
Main system clock HALT mode
+32-kHz oscillation
Supply Current IDD (mA)
0.5
0.1
Subsystem clock operation mode
(Low voltage)
0.05
Subsystem clock HALT mode
(SOS.1 = 0) and main system
clock STOP mode +32-kHz
oscillation (SOS.1 = 0)
Subsystem clock HALT mode
(SOS.1 = 1) and main system
clock STOP mode +32-kHz
oscillation (SOS.1 = 1)
0.01
0.005
CL2 XT1
CL1
RC
oscillation
22 kΩ
22 pF
0.001
0
1
2
3
4
Supply Voltage VDD (V)
46
5
XT2
Crystal
resontor
32.768 kHz 220 kΩ
33 pF
6
7
33 pF
8
µPD75P0116
11. RC OSCILLATION FREQUENCY CHARACTERISTICS EXAMPLES (REFERENCE VALUE)
fCC vs VDD (RC oscillation, R = 22kΩ, C = 22 pF)
(TA = –40 °C)
Main system clock frequency fCC (MHz)
2.0
CL1
CL2
22 kΩ
22 pF
1.0
Sample A
Sample B
Sample C
0.5
1
0
2
3
5
4
Supply voltage VDD (V)
6
7
(TA = 25 °C)
Main system clock frequency fCC (MHz)
2.0
CL1
CL2
22 kΩ
22 pF
1.0
Sample A
Sample B
Sample C
0.5
0
1
2
3
4
5
Supply voltage VDD (V)
6
7
8
(TA = 85 °C)
2.0
Main system clock frequency fCC (MHz)
8
CL1
CL2
22 kΩ
22 pF
1.0
Sample A
Sample B
or Sample C
0.5
0
1
2
3
4
5
Supply voltage VDD (V)
6
7
8
47
µPD75P0116
fCC vs TA (RC oscillation, R = 22kΩ, C = 22 pF)
(Sample A)
Main system clock frequency fCC (MHz)
2.0
CL1
CL2
22 kΩ
22 pF
VDD = 5.0 V
VDD = 3.0 V
VDD = 2.2 V
VDD = 1.8 V
1.0
0.5
–60
–40
–20
0
+20
+40
Operating ambient temperature TA (°C)
+60
+80
(Sample B)
Main system clock frequency fCC (MHz)
2.0
CL1
CL2
22 kΩ
22 pF
VDD = 5.0 V
VDD = 3.0 V
1.0
VDD = 2.2 V
VDD = 1.8 V
0.5
–60
–40
–20
0
+20
+40
Operating ambient temperature TA (°C)
+60
+80
Main system clock frequency fCC (MHz)
+100
(Sample C)
2.0
CL1
CL2
22 kΩ
22 pF
VDD = 5.0 V
VDD = 3.0 V
1.0
VDD = 2.2 V
VDD = 1.8 V
0.5
–60
48
+100
–40
–20
0
+20
+40
Operating ambient temperature TA (°C)
+60
+80
+100
µPD75P0116
12. PACKAGE DRAWINGS
42PIN PLASTIC SHRINK DIP (600 mil)
42
22
1
21
A
K
H
G
J
I
L
F
B
D
N
R
M
C
M
NOTES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
2) Item "K" to center of leads when formed parallel.
ITEM
MILLIMETERS
INCHES
A
39.13 MAX.
1.541 MAX.
B
1.78 MAX.
0.070 MAX.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020 +0.004
–0.005
F
0.9 MIN.
0.035 MIN.
G
3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.08 MAX.
0.200 MAX.
K
L
15.24 (T.P.)
13.2
0.520
M
0.25 +0.10
–0.05
0.010 +0.004
–0.003
N
0.17
0.007
R
0~15°
0~15°
0.600 (T.P.)
P42C-70-600A-1
49
µPD75P0116
44 PIN PLASTIC QFP ( 10)
A
B
23
22
33
34
detail of lead end
C
D
S
R
Q
12
11
44
1
F
J
G
H
I
M
K
M
P
N
L
NOTE
Each lead centerline is located within 0.16 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
50
ITEM
MILLIMETERS
A
13.2±0.2
INCHES
0.520 +0.008
–0.009
B
10.0±0.2
0.394 +0.008
–0.009
C
10.0±0.2
0.394 +0.008
–0.009
D
13.2±0.2
0.520 +0.008
–0.009
F
1.0
0.039
G
1.0
0.039
H
0.37 +0.08
–0.07
0.015 +0.003
–0.004
I
0.16
0.007
J
0.8 (T.P.)
0.031 (T.P.)
K
1.6±0.2
0.063±0.008
L
0.8±0.2
0.031 +0.009
–0.008
M
0.17 +0.06
–0.05
0.007 +0.002
–0.003
N
0.10
0.004
P
2.7
0.106
Q
0.125±0.075
R
3° +7°
–3°
0.005±0.003
3° +7°
–3°
S
3.0 MAX.
0.119 MAX.
S44GB-80-3BS
µPD75P0116
13. RECOMMENDED SOLDERING CONDITIONS
Solder the µPD75P0116 under the following recommended conditions.
For the details on the recommended soldering conditions, refer to Information Document Semiconductor
Device Mounting Technology Manual (C10535E).
For the soldering methods and conditions other than those recommended, consult NEC.
Table 13-1. Soldering Conditions of Surface Mount Type
µPD75P0116GB-3BS-MTX: 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)
Soldering method
Soldering conditions
Symbol of
recommended
condition
Infrared reflow
Package peak temperature: 235 ˚C, Time: 30 seconds max. (210 ˚C min.),
Number of times: 3 max.
IR35-00-3
VPS
Package peak temperature: 215 ˚C, Time: 40 seconds max. (200 ˚C min.),
Number of times: 3 max.
VP15-00-3
Wave soldering
Soldering bath temperature: 260 ˚C max., Time: 10 seconds max.,
Number of times: 1
WS60-00-1
Preheating temperature: 120 ˚C max. (package surface temperature)
Partial heating
Pin temperature: 300 ˚C max., Time: 3 seconds max. (per side of device)
–
Caution Do not use two or more soldering methods in combination (except the partial heating method).
Table 13-2. Soldering Conditions of Insertion Type
µPD75P0116CU: 42-pin plastic Shrink DIP (600 mil, 1.778-mm pitch)
Soldering method
Soldering conditions
Wave soldering (pin only)
Soldering bath temperature: 260 ˚C max., Time: 10 seconds max.
Partial heating
Pin temperature: 300 ˚C max., Time: 3 seconds max. (per pin)
Caution Apply wave soldering to the pins only. Be careful not to allow solder jet to come into direct
contact with the body of the chip.
51
µPD75P0116
APPENDIX A. FUNCTION LIST OF µPD750008, 750108, AND 75P0116
(1/2)
µPD750008
Parameter
Program memory
µPD750108
µPD75P0116
Mask ROM
0000H-1FFFH
One-time PROM
0000H-3FFFH
(8192 × 8 bits)
(16384 × 8 bits)
Data memory
000H-1FFH
(512 × 4 bits)
CPU
75XL CPU
General register
(4 bits × 8 or 8 bits × 4) × 4 banks
Main system clock oscillation circuit
Crystal/ceramic oscillation
circuit
RC oscillation circuit (external resistor and capacitor)
Start-up time after reset
217/f X, 215/f X
(Selected by mask option)
56/f CC fixed
Wait time after releasing STOP
220/f X, 217/f X, 215/f X, 2 13/f X
(Selected by setting BTM)
29/f CC, no wait
(Selected by mask option)
mode due to interrupt occurrence
29/f CC fixed
Subsystem clock oscillation circuit
Crystal oscillation circuit
Instruction
execution
time
When main system
clock is selected
• 0.95, 1.91, 3.81, 15.3 µs
(at fX = 4.19-MHz operation)
• 0.67, 1.33, 2.67, 10.7 µs
(at fX = 6.0-MHz operation)
When subsystem
clock is selected
122 µs (at 32.768 kHz operation)
CMOS input
8 (on-chip pull-up resistors can be specified in software: 7)
I/O port
• 4, 8, 16, 64 µs (at f CC = 1.0 MHz operation)
• 2, 4, 8, 32 µs (at fCC = 2.0 MHz operation)
CMOS input/output
18 (on-chip pull-up resistors can be specified in software)
N-ch open drain
input/output
8 (on-chip pull-up resistors can be specified in
software), Withstand voltage is 13 V
Total
34
8 (no mask option)
Withstand voltage is 13 V.
Timer
4 channels
• 8-bit timer counter:
1 channel
• 8-bit timer/event counter:
1 channel
• Basic interval timer/
watchdog timer: 1 channel
• Watch timer: 1 channel
Serial interface
3 modes are available
• 3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit
• 2-wire serial I/O mode
• SBI mode
Clock output (PCL)
• Φ, 524, 262, 65.5 kHz
(Main system clock:
at 4.19-MHz operation)
• Φ, 750, 375, 93.8 kHz
(Main system clock:
at 6.0-MHz operation)
• Φ, 125, 62.5, 15.6 kHz
(main system clock: at 1.0-MHz operation)
• Φ, 250, 125, 31.3 kHz
(main system clock: at 2.0-MHz operation)
Buzzer output (BUZ)
• 2, 4, 32 kHz
(Main system clock:
at 4.19-MHz operation
or subsystem clock:
at 32.768-kHz operation)
• 2.93, 5.86, 46.9 kHz
(Main system clock:
at 6.0-MHz operation)
• 2, 4, 32 kHz
(Subsystem clock: at 32.768-kHz operation)
• 0.488, 0.977, 7.813 kHz
(Main system clock: at 1.0-MHz operation)
• 0.977, 1.953, 15.625 kHz
(Main system clock: at 2.0-MHz operation)
52
4 channels
• 8-bit timer counter (with watch timer output function):
1 channel
• 8-bit timer/event counter: 1 channel
• Basic interval timer/watchdog timer: 1 channel
• Watch timer: 1 channel
µPD75P0116
(2/2)
Parameter
µPD750008
µPD750108
Vectored interrupt
External: 3, internal: 4
Test input
External: 1, internal: 1
Operation supply voltage
VDD = 2.2 to 5.5 V
Operating ambient temperature
TA = –40 to +85 ˚C
Package
• 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
• 44-pin plastic shrink QFP (10 × 10 mm, 0.8-mm pitch)
µPD75P0116
VDD = 1.8 to 5.5 V
53
µPD75P0116
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are provided for system development using the µPD75P0116. The 75XL series uses
a common relocatable assembler, in combination with a device file matching each machine.
RA75X relocatable assembler
Host machine
Part number
OS
PC-9800 series
TM
MS-DOS
Ver.3.30 to
Ver.6.2 Note
Device file
Supply medium
(product name)
3.5" 2HD
µS5A13RA75X
5" 2HD
µS5A10RA75X
IBM PC/ATTM
Refer to OS for
3.5" 2HC
µS7B13RA75X
or compatible
IBM PCs
5" 2HC
µS7B10RA75X
Host machine
Part number
OS
PC-9800 series
MS-DOS
Ver.3.30 to
Ver.6.2 Note
Supply medium
(product name)
3.5" 2HD
µS5A13DF750008
5" 2HD
µS5A10DF750008
IBM PC/AT
Refer to OS for
3.5" 2HC
µS7B13DF750008
or compatible
IBM PCs
5" 2HC
µS7B10DF750008
Note Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swap function, but it does not work with this
software.
Remark
54
The operation of the assembler and device file is guaranteed only on the above host machines and OSs.
µPD75P0116
PROM Write Tools
Hardware
PG-1500
PA-75P008CU
A stand-alone system can be configured of a single-chip microcomputer with on-chip PROM
when connected to an auxiliary board (companion product) and a programmer adapter
(separately sold). Alternatively, a PROM programmer can be operated on a host machine for
programming.
In addition, typical PROMs in capacities ranging from 256 K to 4 M bits can be programmed.
This is a PROM programmer adapter for the µPD75P0116CU/GB. It can be used when
connected to a PG-1500.
Software
PG-1500 controller
Establishes serial and parallel connections between the PG-1500 and a host machine for hostmachine control of the PG-1500.
Host machine
Part number
OS
PC-9800 Series
MS-DOS
Ver.3.30 to
Supply medium
(product name)
3.5" 2HD
µS5A13PG1500
5" 2HD
µS5A10PG1500
Ver.6.2 Note
IBM PC/AT
Refer to OS for
3.5" 2HD
µS7B13PG1500
or compatible
IBM PCs
5" 2HC
µS7B10PG1500
Note Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swapping function, but it does not work with
this software.
Remark
Operation of the PG-1500 controller is guaranteed only on the above host machine and OSs.
55
µPD75P0116
Debugging Tools
In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the µPD75P0116.
Various system configurations using these in-circuit emulators are listed below.
Hardware
Software
IE-75000-RNote 1
The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during
development of application systems that use 75X or 75XL Series products. For development
of the µPD750108 subseries, the IE-75000-R is used with a separately sold emulation board IE75300-R-EM and emulation probe EP-75008CU-R or EP-75008GB-R.
These products can be applied for highly efficient debugging when connected to a host machine
and PROM programmer.
The IE-75000-R can include a connected emulation board (IE-75000-R-EM).
IE-75001-R
The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during
development of application systems that use 75X or 75XL Series products. The IE-75001-R is
used with a separately sold emulation board IE-75300-R-EM and emulation probe EP75008CU-R or EP-75008GB-R.
These products can be applied for highly efficient debugging when connected to a host machine
and PROM programmer.
IE-75300-R-EM
This is an emulation board for evaluating application systems that use the µPD750108
subseries. It is used in combination with the IE-75000-R or IE-75001-R in-circuit emulator.
EP-75008CU-R
This is an emulation probe for the µPD75P0116CU.
When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.
EP-75008GB-R
EV-9200G-44
This is an emulation probe for the µPD75P0116GB.
When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.
It includes a 44-pin conversion socket EV-9200G-44 to facilitate connections with various target
systems.
IE control program
This program can control the IE-75000-R or IE-75001-R on a host machine when connected to
the IE-75000-R or IE-75001-R via an RS-232-C or Centronics I/F.
Host machine
Part number
OS
PC-9800 series
MS-DOS
Ver.3.30 to
Supply medium
(product name)
3.5" 2HD
µS5A13IE75X
5" 2HD
µS5A10IE75X
Ver.6.2 Note 2
IBM PC/AT
Refer to OS for
3.5" 2HC
µS7B13IE75X
or compatible
IBM PCs
5" 2HC
µS7B10IE75X
Notes 1. This is a service part provided for maintenance purpose only.
2. Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swapping function, but it does not work
with this software.
Remarks 1. Operation of the IE control program is guaranteed only on the above host machine and OSs.
2. The µPD750108 subseries consists of the µPD750104, 750106, 750108 and 75P0116.
56
µPD75P0116
OS for IBM PCs
The following operating systems for the IBM PC are supported.
OS
TM
PC DOS
Version
Ver.3.1 to Ver.6.3
J6.1/VNote to J6.3/VNote
MS-DOS
Ver.5.0 to Ver.6.22
5.0/VNote to J6.2/VNote
IBM DOSTM
J5.02/VNote
Note Supports English version only.
Caution Ver 5.0 and above include a task swapping function, but this software is not able to use that function.
57
µPD75P0116
APPENDIX C. RELATED DOCUMENTS
Some of the following related documents are preliminary. This document, however, is not indicated as
preliminary.
Device Related Documents
Document No.
Document name
Japanese
English
µPD750104, 750106, 750108, 750104(A), 750106(A), 750108(A)
Data Sheet
U12301J
Planned
µPD75P0116 Data Sheet
U12603J
This document
µPD750108 User’s Manual
U11330J
U11330E
µPD750008, 750108 Instruction List
U11456J
–
75XL Series Selection Guide
U10453J
U10453E
Development Tool Related Documents
Document No.
Document name
IE-75000 R/IE-75001-R User’s Manual
Hardware
Software
Japanese
English
EEU-846
EEU-1416
IE-75300-R-EM User’s Manual
U11354J
U11354E
EP-750008CU-R User’s Manual
EEU-699
EEU-1317
EP-750008GB-R User’s Manual
EEU-698
EEU-1305
PG-1500 User’s Manual
U11940J
EEU-1335
RA75X Assembler Package
Operation
EEU-731
EEU-1346
User’s Manual
Language
EEU-730
EEU-1363
PG-1500 Controller User’s Manual
PC-9800 Series
(MS-DOS) Base
EEU-704
EEU-1291
IBM PC Series
(PC DOS) Base
EEU-5008
U10540E
Other Documents
Document name
IC Package Manual
Document No.
Japanese
English
C10943X
Semiconductor Device Mounting Technology Manual
C10535J
C10535E
Quality Grades on NEC Semiconductor Devices
C11531J
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983J
C10983E
Static Electricity Discharge (ESD) Test
MEM-539
–
Semiconductor Devices Quality Guarantee Guide
C11893J
MEI-1202
Guide for Products Related to Microcomputer : Other Companies
C11416J
–
Caution The above related documents are subject to change without notice. For design purpose, etc.,
be sure to use the latest documents.
58
µPD75P0116
[MEMO]
59
µPD75P0116
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred.
Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity.
Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded.
The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with
bare hands.
Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using a pull-up or pull-down circuitry.
Each unused pin should be connected to VDD or GND with a resistor, if it is
considered to have a possibility of being an output pin. All handling related
to the unused pins must be judged device by device and related specifications
governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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µPD75P0116
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics (France) S.A.
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
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µPD75P0116
[MEMO]
MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States
and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
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