DATA SHEET MOS INTEGRATED CIRCUIT µ PD8891 (5340 × 5340) PIXELS × 3 + 2670 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR DESCRIPTION The µ PD8891 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The µ PD8891 has 3 rows of (5340+5340) staggered pixels, and each row has a dual-sided readout type of charge transfer register, and has 3 rows of 2670 pixels, and each row has a single-sided readout type of charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 1200 dpi/A4 color image scanners, color facsimiles and so on. FEATURES • Valid photocell : (5340+5340) pixels × 3 + 2670 pixels × 3 • Photocell pitch : 5.25 µ m (1200 dpi), 10.5 µ m (300 dpi) • Photocell size : 5.25 × 5.25 µ m (1200 dpi), 10.5 × 8 µ m (300 dpi) • Line spacing : [1200 dpi sensor] 2 2 52.5 µ m (10 lines) Red line - Green line, Green line - Blue line 10.5 µm (2 lines) Odd line – Even line (for each color) [300 dpi sensor] 42 µ m (4 lines) Red line - Green line, Green line - Blue line 7 • Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour) • Resolution : 48 dot/mm A4 (210 × 297 mm) size (shorter side) 1200 dpi US letter (8.5” × 11”) size (shorter side) : • Drive clock level : CMOS output under 5 V operation • Data rate : 5 MHz Max. • Power supply : +12 V • On-chip circuits : Reset feed-through level clamp circuits :: Voltage amplifiers ORDERING INFORMATION Part Number Package µ PD8891CY CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) The information in this document is subject to change without notice. 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Document No. S16039EJ2V0DS00 (2nd edition) Date Published March 2003 NS CP (K) Printed in Japan 2002 µ PD8891 BLOCK DIAGRAM VOD GND GND 22 1 11 φ RB φ 2L φ 2-1200 φ 1-1200 4 3 7 8 φ TG1 (Blue) 10 φ TG2 (Green) 9 φ TG3 (Red) D161 ··· 12 D162 D156 S10680 Photocell (Blue) D155 S10679 S1 D153 ···· S2 VOUT1 20 (Blue) D154 D47 CCD analog shift register Transfer gate Transfer gate CCD analog shift register D161 ··· D162 D156 S10680 Photocell (Green) D155 S10679 S1 D153 ···· S2 VOUT2 21 (Green) D154 D47 CCD analog shift register Transfer gate Transfer gate CCD analog shift register CCD analog shift register D161 ··· D162 D156 S10680 Photocell (Red) D155 S10679 S1 D153 ···· 2 S2 VOUT3 (Red) D154 D47 Transfer gate D41 D40 Photocell (Blue) S2670 S2 S1 ···· D39 D13 Transfer gate CCD analog shift register Transfer gate D40 D41 D40 D41 Photocell (Green) S2670 S2 S1 ···· D39 D13 CCD analog shift register Transfer gate Photocell (Red) S2670 S2 S1 ···· D39 D13 CCD analog shift register Transfer gate CCD analog shift register 2 5 19 17 14 16 13 15 φ CLB φ SEL φ 1L φ 2-300 φ 2-300 φ 1-300 φ 1-300 Data Sheet S16039EJ2V0DS µ PD8891 PIN CONFIGURATION (Top View) CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) • µ PD8891CY 1 22 VOD Output drain voltage Output signal 3 (Red) VOUT3 2 21 VOUT2 Output signal 2 (Green) Last stage shift register clock 2 φ 2L 3 20 VOUT1 Output signal 1 (Blue) Reset gate clock φ RB 4 19 φ SEL 300/1200 dpi select input Reset feed-through level level clamp clock φ CLB 5 18 NC No connection No connection NC 6 17 φ 1L Last stage shift register clock 1 Shift register clock 2 (for 1200 dpi) φ 2-1200 7 16 φ 2-300 Shift register clock 2 (for 300 dpi) Shift register clock 1 (for 1200 dpi) φ 1-1200 8 15 φ 1-300 Shift register clock 1 (for 300 dpi) Transfer gate clock 3 (for Red) φ TG3 9 14 φ 2-300 Shift register clock 2 (for 300 dpi) Transfer gate clock 2 (for Green) φ TG2 10 13 φ 1-300 Shift register clock 1 (for 300 dpi) Ground GND 11 12 φ TG1 Transfer gate clock 1 (for Blue) Red Green Blue 2670 2670 2670 Red Green Blue 10680 10680 10680 1 1 1 GND 1 1 1 Ground Caution Connect the No connection pins (NC) to GND. Data Sheet S16039EJ2V0DS 3 µ PD8891 PHOTOCELL STRUCTURE DIAGRAM 1200 dpi sensor 8.0 µ m Channel stopper Aluminium shield 2.5 µ m 8.0 µ m 2.5 µ m 5.25 µ m 2.75 µ m 300 dpi sensor Channel stopper Aluminium shield PHOTOCELL ARRAY STRUCTURE DIAGRAM 1 (Line Spacing) 10.5 µ m Blue photocell array 4 lines (42 µ m) 300 dpi sensor 10.5 µ m Green photocell array 4 lines (42 µ m) 10.5 µ m Red photocell array 42 µ m 5.25 µ m 5.25 µ m 5.25 µ m Blue photocell array Blue photocell array 5.25 µ m 8 lines (42 µ m) 1200 dpi sensor 5.25 µ m 5.25 µ m 5.25 µ m Green photocell array Green photocell array 2 lines (10.5 µ m) 8 lines (42 µ m) 5.25 µ m 5.25 µ m 5.25 µ m 4 Red photocell array Red photocell array Data Sheet S16039EJ2V0DS 10 lines (52.5 µ m) 2 lines (10.5 µ m) 10 lines (52.5 µ m) µ PD8891 PHOTOCELL ARRAY STRUCTURE DIAGRAM 2 (The Relation of the Photocell Array) Dummy Optical black Invalid photocell Valid photocell 46 pixels 100 pixels 8 pixels 10680 pixels Invalid photocell 8 pixels 10831 10833 10835-10841 1-45 47-145 147 149 151 153 155 157 − 1200 dpi 2-46 48-146 − 148 150 152 154 156 158 10832 10834 10836-10842 300 dpi 12 pixels 25 pixels 2 pixels 1-12 13-37 38, 39 2670 pixels 40 Data Sheet S16039EJ2V0DS − 2 pixels 2709 2710, 2711 5 µ PD8891 ABSOLUTE MAXIMUM RATINGS (TA = +25°°C) Parameter Symbol Ratings Unit Output drain voltage VOD −0.3 to +15 V Shift register clock voltage Vφ 1-300, Vφ 1-1200, Vφ 1L, −0.3 to +8 V Vφ 2-300, Vφ 2-1200, Vφ 2L Reset gate clock voltage Vφ RB −0.3 to +8 V Reset feed-through level clamp clock voltage Vφ CLB −0.3 to +8 V 300/1200 dpi select signal voltage Vφ SEL −0.3 to +8 V Transfer gate clock voltage Vφ TG1 to Vφ TG3 Operating ambient temperature Note Storage temperature −0.3 to +8 V TA 0 to +60 °C Tstg −40 to +70 °C Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25°°C) Parameter Symbol Min. Typ. Max. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock high level Vφ 1-300H, Vφ 1-1200H, Vφ 1LH, 4.75 5.0 5.25 V Shift register clock low level Vφ 1-300L, Vφ 1-1200L, Vφ 1LL, −0.3 0 +0.25 V Reset gate clock high level Vφ RBH 4.5 5.0 5.5 V Reset gate clock low level Vφ RBL −0.3 0 +0.5 V Reset feed-through level clamp clock high level Vφ CLBH 4.5 5.0 5.5 V Reset feed-through level clamp clock low level Vφ CLBL −0.3 0 +0.5 V 300/1200 dpi select signal high level Vφ SELH 4.5 5.0 5.5 V 300/1200 dpi select signal low level Vφ SELL −0.3 0 +0.5 V Transfer gate clock high level Vφ TG1H to Vφ TG3H 4.75 Vφ 1-300H, Vφ 1-300H, V Vφ 2-300H, Vφ 2-1200H, Vφ 2LH Vφ 2-300L, Vφ 2-1200L, Vφ 2LL Vφ 1-1200H Transfer gate clock low level Vφ TG1L to Vφ TG3L Data rate fφ RB Note Vφ 1-1200H Note −0.3 0 +0.15 V − 2.0 5.0 MHz When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than shift register clock high level (Vφ 1-300H, Vφ 1-1200H), image lag can increase. 6 Note Data Sheet S16039EJ2V0DS µ PD8891 ELECTRICAL CHARACTERISTICS TA = +25°C, VOD = 12 V, data rate (fφ RB) = 2 MHz, storage time = 11.0 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm) Parameter Symbol Saturation voltage Test Conditions Min. Typ. Max. Unit 2.7 − V Vsat 300 dpi 2.5 1200 dpi 2.0 2.4 − V SER 300 dpi − 0.167 − lx•s 1200 dpi − 0.445 − lx•s 300 dpi − 0.176 − lx•s 1200 dpi − 0.470 − lx•s SEB 300 dpi − 0.274 − lx•s 1200 dpi − 0.732 − lx•s Photo response non-uniformity PRNU VOUT = 1.0 V − 6 20 % Average dark signal ADS Light shielding 300 dpi − 0.4 4.0 mV Light shielding 1200 dpi − 0.2 2.0 mV Dark signal non-uniformity DSNU Light shielding 300 dpi − 4.0 12.0 mV Light shielding 1200 dpi − 2.0 6.0 mV − 300 480 mW Saturation exposure Red Green Blue SEG Power consumption PW Output impedance ZO Response Red Green Blue Offset level Note 1 RR RG RB − 0.4 1.0 kΩ 300 dpi 11.32 16.17 21.02 V/lx•s 1200 dpi 3.77 5.39 7.01 V/lx•s 300 dpi 10.73 15.33 19.93 V/lx•s 1200 dpi 3.58 5.11 6.64 V/lx•s 300 dpi 6.89 9.84 12.79 V/lx•s 1200 dpi 2.30 3.28 4.26 V/lx•s 4.5 6.0 7.5 V − 3.0 7.0 % VOS Image lag IL Note 2 VOUT = 1.0 V td VOUT = 1.0 V − 25 − ns Total transfer efficiency TTE VOUT = 1.0 V, data rate = 5 MHz 92 98 − % Register imbalance RI VOUT = 1.0 V − 1.0 4.0 % Output fall delay time Response peak Red − 630 − nm Green − 540 − nm Blue − 460 − nm Dynamic range Reset feed-through noise Random noise (CDS) (1200 dpi) Note 1 DR1 Vsat/DSNU 300 dpi − 675 − times Vsat/DSNU 1200 dpi − 1200 − times DR2 Vsat/σ CDS 300 dpi − 2700 − times Vsat/σ CDS 1200 dpi − 2400 − times RFTN Light shielding −2000 −500 +1000 mV σ CDS Light shielding − 1.0 − mV Notes 1. Refer to TIMING CHART 2− −1 to 2− −8. −1 to 2− −8). 2. When the fall time of φ 1L or φ 2L (t1’, t2’) is the Typ. value (refer to TIMING CHART 2− Data Sheet S16039EJ2V0DS 7 µ PD8891 INPUT PIN CAPACITANCE (TA = +25°°C, VOD = 12 V) Parameter Symbol Pin name Cφ 1-300 φ 1-300 15 − 250 − pF Cφ 1-1200 φ 1-1200 8 − 850 − pF Cφ 2-300 φ 2-300 14 − 300 − pF 16 − 300 − pF Cφ 2-1200 φ 2-1200 7 − 850 − pF Last stage sift reset gate clock pin capacitance 1 Cφ 1L φ 1L 17 − 15 − pF Last stage sift reset gate clock pin capacitance 2 Cφ 2L φ 2L 3 − 15 − pF Reset gate clock pin capacitance Cφ RB φ RB 4 − 15 − pF Reset feed-through level clamp clock pin capacitance Cφ CLB φ CLB 5 − 15 − pF 300/1200 dpi select signal pin capacitance Cφ SEL φ SEL 19 − 15 − pF Transfer gate clock pin capacitance Cφ TG φ TG1 12 − 200 − pF φ TG2 10 − 200 − pF φ TG3 9 − 200 − pF Shift register clock pin capacitance 1 Shift register clock pin capacitance 2 Pin No. Min. Typ. Max. Unit 13 − 250 − pF 300/600/1200 MODE Mode Description 1 300 dpi only 2 600 dpi only 3 Note 1 1200 dpi only φ SEL 300 dpi data High Use Low Flush Low Flush Note 2 Note 2 φ 1-300, φ 2-300 1200 dpi data Note 2 φ 1-1200, φ 2-1200 Clocked Flush Clocked Clocked Use 1 line Clocked Clocked Use Clocked Notes 1. For 600 dpi mode, the reset pulse is extended to allow second line’s charge to dump immediately to DC level. 2. Flush means that data is continuously sunk via reset gate. 8 Data Sheet S16039EJ2V0DS TIMING CHART 1− −1 (1200 dpi, for each color) φ TG1 to φ TG3 φ 1-1200, φ 1L φ 2-1200, φ 2L φ RB Note Note 10842 10843 10834 10835 154 155 45 46 47 146 147 φ CLB (Line clamp mode) 1 2 3 4 5 6 Data Sheet S16039EJ2V0DS φ CLB (Bit clamp mode) VOUT1 to VOUT3 Valid photocell (10680 pixels) Optical black (100 pixels) Invalid photocell (8 pixels) And set the φ RB pulse to high level while the φ CLB pulse is low level at line clamp mode. Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB at line clamp mode. 9 µ PD8891 Note Set the φ RB pulse and φ CLB pulse (bit clamp mode) to high level during the φ TG1 to φ TG3 pulse. Invalid photocell (8 pixels) 10 TIMING CHART 1− −2 (600 dpi, even pixel, for each color) φ TG1 to φ TG3 φ 1-1200, φ 1L φ 2-1200, φ 2L φ RB Note Note 10842 10836 10834 10832 158 156 154 148 146 144 50 48 46 44 4 φ CLB (Line clamp mode) 2 Data Sheet S16039EJ2V0DS φ CLB (Bit clamp mode) VOUT1 to VOUT3 Valid photocell (5340 pixels) Optical black (50 pixels) Invalid photocell (4 pixels) And set the φ RB pulse to high level while the φ CLB pulse is low level at line clamp mode. Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB at line clamp mode. µ PD8891 Note Set the φ RB pulse and φ CLB pulse (bit clamp mode) to high level during the φ TG1 to φ TG3 pulse. Invalid photocell (4 pixels) TIMING CHART 1− −3 (600 dpi, odd pixel, for each color) φ TG1 to φ TG3 φ 1-1200, φ 1L φ 2-1200, φ 2L φ RB Note Note 10841 10835 10833 10831 157 155 153 147 145 143 49 47 45 43 3 φ CLB (Line clamp mode) 1 Data Sheet S16039EJ2V0DS φ CLB (Bit clamp mode) VOUT1 to VOUT3 Optical black (50 pixels) Valid photocell (5340 pixels) Invalid photocell (4 pixels) And set the φ RB pulse to high level while the φ CLB pulse is low level at line clamp mode. 11 Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB at line clamp mode. µ PD8891 Note Set the φ RB pulse and φ CLB pulse (bit clamp mode) to high level during the φ TG1 to φ TG3 pulse. Invalid photocell (4 pixels) 12 TIMING CHART 1− −4 (300 dpi, for each color) φ TG1 to φ TG3 φ 1-300, φ 1L φ 2-300, φ 2L φ RB Note Note 2708 2709 2710 2711 2712 36 37 38 39 40 41 φ CLB (Line clamp mode) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Data Sheet S16039EJ2V0DS φ CLB (Bit clamp mode) VOUT1 to VOUT3 Optical black (25 pixels) Valid photocell (2670 pixels) Invalid photocell (2 pixels) And set the φ RB pulse to high level while the φ CLB pulse is low level at line clamp mode. Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB at line clamp mode. µ PD8891 Note Set the φ RB pulse and φ CLB pulse (bit clamp mode) to high level during the φ TG1 to φ TG3 pulse. Invalid photocell (2 pixel) µ PD8891 −1 (1200 dpi, bit clamp mode, for each color) TIMING CHART 2− t1 t2 90% φ 1-1200 10% 90% φ 2-1200 10% t1’ 90% φ 1L 10% 90% φ 2L 10% t5 φ RB t6 t3 t5 t4 t3 t6 t4 90% 10% t7 t9 t8 t10 t7 t9 t11 t8 t10 t11 90% φ CLB 10% + td td RFTN VOUT t2’ – RFTN VOS 10% Symbol Min. Typ. Max. Unit t1, t2 0 25 − ns t1’, t2’ 0 5 − ns t3 20 50 − ns t4 50 150 − ns t5, t6 0 5 − ns −5 Note +25 − ns t8 20 50 − ns t9, t10 0 5 − ns t11 5 25 − ns t7 Note Min. of t7 shows that the φ RB and φ CLB overlap each other. 90% φ RB t7 φ CLB 90% Data Sheet S16039EJ2V0DS 13 µ PD8891 −2 (1200 dpi, line clamp mode, for each color) TIMING CHART 2− t1 t2 90% φ 1-1200 10% 90% φ 2-1200 10% t1’ 90% φ 1L 10% 90% φ 2L 10% t5 t3 t6 t5 t4 t6 “H” td td RFTN – RFTN VOS 10% Symbol 14 t4 10% + VOUT t3 90% φ RB φ CLB t2’ Min. Typ. Max. Unit t1, t2 0 25 − ns t1’, t2’ 0 5 − ns t3 20 50 − ns t4 50 150 − ns t5, t6 0 5 − ns Data Sheet S16039EJ2V0DS µ PD8891 −3 (600 dpi, even pixel, bit clamp mode, for each color) TIMING CHART 2− t1 t2 90% φ 1-1200 10% 90% φ 2-1200 10% t1’ t2’ 90% φ 1L 10% 90% φ 2L 10% t5 φ RB t3’ t6 t3’ t4 90% 10% t9 t7 t8 t10 t11 90% φ CLB 10% td + RFTN VOUT RFTN – VOS 10% Symbol Min. Typ. Max. Unit t1, t2 0 25 − ns t1’, t2’ 0 5 − ns t3’ 50 100 − ns t4 50 370 − ns t5, t6 0 5 − ns −5 Note +25 − ns 100 200 − ns t9, t10 0 5 − ns t11 5 100 − ns t7 t8 Note Min. of t7 shows that the φ RB and φ CLB overlap each other. 90% φ RB t7 φ CLB 90% Data Sheet S16039EJ2V0DS 15 µ PD8891 −4 (600 dpi, even pixel, line clamp mode, for each color) TIMING CHART 2− t1 t2 90% φ 1-1200 10% 90% φ 2-1200 10% t1’ t2’ 90% φ 1L 10% 90% φ 2L 10% t5 φ RB φ CLB t3’ t6 t3’ t4 90% 10% “H” td + RFTN VOUT RFTN – VOS 10% Symbol 16 Min. Typ. Max. Unit t1, t2 0 25 − ns t1’, t2’ 0 5 − ns t3’ 50 100 − ns t4 50 370 − ns t5, t6 0 5 − ns Data Sheet S16039EJ2V0DS µ PD8891 −5 (600 dpi, odd pixel, bit clamp mode, for each color) TIMING CHART 2− t2 t1 90% φ 1-1200 10% 90% φ 2-1200 10% t1’ t2’ 90% φ 1L 10% 90% φ 2L 10% t5 t3’ t6 t3’ t4 90% φ RB 10% t9 t8 t7 t10 t11 90% φ CLB 10% td + RFTN RFTN – VOUT VOS 10% Symbol Min. Typ. Max. Unit t1, t2 0 25 − ns t1’, t2’ 0 5 − ns t3’ 50 100 − ns t4 50 370 − ns t5, t6 0 5 − ns −5 Note +25 − ns 100 200 − ns t9, t10 0 5 − ns t11 5 100 − ns t7 t8 Note Min. of t7 shows that the φ RB and φ CLB overlap each other. 90% φ RB t7 φ CLB 90% Data Sheet S16039EJ2V0DS 17 µ PD8891 −6 (600 dpi, odd pixel, line clamp mode, for each color) TIMING CHART 2− t2 t1 90% φ 1-1200 10% 90% φ 2-1200 10% t1’ t2’ 90% φ 1L 10% 90% φ 2L 10% t5 t4 90% φ RB φ CLB t3’ t6 t3’ 10% “H” td + RFTN RFTN – VOUT VOS 10% Symbol 18 Min. Typ. Max. Unit t1, t2 0 25 − ns t1’, t2’ 0 5 − ns t3’ 50 100 − ns t4 50 370 − ns t5, t6 0 5 − ns Data Sheet S16039EJ2V0DS µ PD8891 −7 (300 dpi, bit clamp mode, for each color) TIMING CHART 2− t1 t2 90% φ 1-300 10% 90% φ 2-300 10% t1’ 90% φ 1L 10% 90% φ 2L 10% t5 φ RB t2’ t6 t3 t4 90% 10% t9 t7 t8 t10 t11 90% φ CLB 10% td + RFTN VOUT RFTN – VOS 10% Symbol Min. Typ. Max. Unit t1, t2 0 25 − ns t1’, t2’ 0 5 − ns t3 20 50 − ns t4 50 150 − ns t5, t6 0 5 − ns +25 − ns −5 t7 Note t8 20 50 − ns t9, t10 0 5 − ns t11 5 25 − ns Note Min. of t7 shows that the φ RB and φ CLB overlap each other. 90% φ RB t7 φ CLB 90% Data Sheet S16039EJ2V0DS 19 µ PD8891 −8 (300 dpi, line clamp mode, for each color) TIMING CHART 2− t1 t2 90% φ 1-300 10% 90% φ 2-300 10% t1’ 90% φ 1L 10% 90% φ 2L 10% t5 t6 t3 t4 90% φ RB φ CLB t2’ 10% “H” td + RFTN VOUT RFTN – VOS 10% Symbol t1, t2 20 Min. Typ. Max. Unit 0 25 − ns t1’, t2’ 0 5 − ns t3 20 50 − ns t4 50 150 − ns t5, t6 0 5 − ns Data Sheet S16039EJ2V0DS µ PD8891 φ TG1 to φ TG3, φ 1, φ 2 TIMING CHART t13 t14 t12 90% 10% t15 φ TG1 to φ TG3 t16 90% φ 1-300, φ 1-1200 90% φ 2-300, φ 2-1200 t17 Note 1 t18 90% φ RB t7 t11 90% φ CLB (Bit clamp mode) t20 t22 t21 Note 2 t23 90% 10% φ CLB (Line clamp mode) t9 Symbol Min. −5 t7 Note 3 t19 t10 Typ. Max. Unit +25 − ns t9, t10 0 5 − ns t11 5 25 − ns t12 5000 10000 50000 ns t13, t14 0 50 − ns t15, t16 900 1000 − ns t17, t18 200 400 − ns t19 t12 t12 50000 ns t20, t21 0 50 − ns t22, t23 0 350 − ns Notes 1. Set the φ RB pulse and φ CLB pulse (bit clamp mode) to high level during this period. 2. Set the φ RB pulse to high level during this period. 3. Min. of t7 shows that the φ RB and φ CLB overlap each other. 90% φ RB t7 φ CLB 90% Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB. Data Sheet S16039EJ2V0DS 21 µ PD8891 φ 1-300, φ 2-300 cross points φ 1-300 φ 2-300 1.0 V to 4.0 V 1.0 V to 4.0 V 1.0 V to 4.0 V 1.0 V to 4.0 V φ 1-1200, φ 2-1200 cross points φ 1-1200 φ 2-1200 φ 1-300, φ 1-1200, φ 2L cross points φ 1-300, φ 1-1200 2.0 V or more 0.5 V or more 2.0 V or more 0.5 V or more φ 2L φ 2-300, φ 1-1200, φ 1L cross points φ 2-300, φ 2-1200 φ 1L Remark Adjust cross points (φ 1-300, φ 2-300), (φ 1-1200, φ 2-1200), (φ 1-300, φ 1-1200, φ 2L) and (φ 2-300, φ 11200, φ 1L) with input resistance of each pin. 22 Data Sheet S16039EJ2V0DS µ PD8891 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = ∆x × 100 x ∆ x : maximum of xj − x Valid pixels Σx x= j j=1 Valid pixels xj : Output voltage of valid pixel number j VOUT Register Dark DC level x ∆x 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. Valid pixels Σd j ADS (mV) = j=1 Valid pixels dj : Dark signal of valid pixel number j Data Sheet S16039EJ2V0DS 23 µ PD8891 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj − ADS j = 1 to valid pixels dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. φ TG Light ON OFF VOUT V1 VOUT IL (%) = 24 V1 × 100 VOUT Data Sheet S16039EJ2V0DS µ PD8891 9. Register Imbalance : RI (1200 dpi) The rate of the difference between the averages of the output voltage of Odd and Even bits, against the average output voltage of all the valid pixels. n 2 2 n ∑ (V2j –1 – V2j) j=1 RI (%) = × 100 n 1 n ∑ Vj j=1 n : Number of valid pixels Vj : Output voltage of each pixel 10. Random noise (CDS) : σ CDS Random noise σ CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). σ CDS is calculated by the following procedure. 1. One valid photocell in one reading is fixed as measurement point. 2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get “VDi”. 3. The output level is measured during the Video Output time averaged over 100 ns to get “VOi”. 4. The correlated double sampling output is defined by VCDSi = VDi – VOi 5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. Calculate the standard deviation σ CDS using the following formula equation. 100 σ CDS (mV) = Σ (VCDS – V) 2 i i=1 100 , V= 1 100 Σ VCDS i 100 i = 1 Video output Reset feed-through Data Sheet S16039EJ2V0DS 25 µ PD8891 STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25°C) 8 2 1 Relative Output Voltage Relative Output Voltage 4 2 1 0.5 0.2 0.25 0.1 0 10 20 30 40 0.1 50 Operating Ambient Temperature TA (°C) 1 5 10 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter ) (TA = +25°C) 100 R G B Response Ratio (%) 80 60 40 G 20 B 0 400 500 600 Wavelength (nm) 26 Data Sheet S16039EJ2V0DS 700 800 µ PD8891 APPLICATION CIRCUIT EXAMPLE +5 V +12 V + + µ PD8891 10 µ F/16 V 0.1 µ F 1 2 B3 φ 2L φ RB φ CLB φ 2-1200 φ 1-1200 3 47 Ω 47 Ω 150 Ω 4 5 6 0.1 µ F GND VOD VOUT3 VOUT2 φ 2L VOUT1 φ RB φ SEL φ CLB NC φ 1L NC 22 +5 V 21 B2 20 B1 19 18 150 Ω 150 Ω 7 φ 2-1200 φ 1-300 16 4.7 Ω 4.7 Ω 8 φ 1-1200 φ 2-300 15 4.7 Ω 10 Ω 9 φ TG3 φ 1-300 14 4.7 Ω 10 Ω 10 φ 2-300 13 4.7 Ω 12 10 Ω 11 φ TG1 GND + 0.1 µ F 10 µ F/16 V φ SEL 17 4.7 Ω φ TG2 47 µ F/25 V φ 1L φ 1-300 φ 2-300 φ TG Caution Connect the No connection pins (NC) to GND. Remarks 1. The inverters shown in the above application circuit example are the 74HC04 (data rate < 2 MHz) or the 74AC04 (2 ≤ data rate < 5 MHz). 2. B1 to B3 in the application circuit example are shown in the figure blow. B1 to B3 EQUIVALENT CIRCUIT +12 V + 100 Ω CCD VOUT 100 Ω 47 µ F/25 V 2SC945 2 kΩ Data Sheet S16039EJ2V0DS 27 µ PD8891 PACKAGE DRAWING µ PD8891CY CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400) ) (Unit : mm) 44.0±0.3 1st valid pixel 0.5±0.3 1 9.25±0.3 22 12 1 11 2.0 37.5 1.02±0.15 0.46±0.1 4.39±0.4 2.54±0.25 (5.42) (1.72) 2 2.62±0.2 3 10.16±0.2 0.25±0.05 10.16 +0.7 −0.2 4.21±0.5 Name Dimensions Refractive index Plastic cap 42.9×8.35×0.7 1.5 1 1st valid pixel The center of the pin1 2 The surface of the CCD chip The top of the cap 3 The bottom of the package The surface of the CCD chip 22C-1CCD-PKG11-1 28 Data Sheet S16039EJ2V0DS µ PD8891 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device µ PD8891CY : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400)) Process Partial heating method Cautions 1. Conditions Pin temperature : 300°C or below, Heat time : 3 seconds or less (per pin) During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap soiling and heat resistance. So the method cannot be guaranteed. Data Sheet S16039EJ2V0DS 29 µ PD8891 NOTES ON HANDLING THE PACKAGES 1 DUST AND DIRT PROTECTING The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents. CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents Symbol Ethyl Alcohol Methyl Alcohol Isopropyl Alcohol EtOH MeOH IPA N-methyl Pyrrolidone NMP 2 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating 3 OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E) 4 ELECTROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. 2. 3. 4. Ground the tools such as soldering iron, radio cutting pliers of or pincer. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. Either handle bare handed or use non-chargeable gloves, clothes or material. Ionized air is recommended for discharge when handling CCD image sensor. 5. For the shipment of mounted substrates, use box treated for prevention of static charges. 6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 MΩ. 30 Data Sheet S16039EJ2V0DS µ PD8891 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S16039EJ2V0DS 31 µ PD8891 • The information in this document is current as of March, 2003. The information is subject to change without notice. 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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1