DATA SHEET MOS INTEGRATED CIRCUIT µPD3799 5300 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR The µPD3799 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The µPD3799 has 3 rows of 5300 pixels, and each row has a single-sided readout type of charge transfer register. And it has reset feed-through level clamp circuits, clamp pulse generation circuit and voltage amplifiers. Therefore, it is suitable for 600 dpi/A4 color image scanners, color facsimiles and so on. FEATURES • Valid photocell : 5300 pixels × 3 • Photocell's pitch : 7 µm • Line spacing : 28 µm (4 lines) Red line-Green line, Green line-Blue line • Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour) • Resolution : 24 dot/mm A4 (210 × 297 mm) size (shorter side) 600 dpi US letter (8.5” × 11”) size (shorter side) • Drive clock level : CMOS output under 5 V operation • Data rate : 4 MHz MAX. • Power supply : +12 V • On-chip circuits : Reset feed-through level clamp circuits Clamp pulse generation circuit Voltage amplifiers ORDERING INFORMATION Part Number µPD3799CY Package CCD linear image sensor 32-pin plastic DIP (400 mil) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14083EJ1V0DS00 (1st edition) Date published April 1999 N CP(K) Printed in Japan © 1999 µPD3799 BLOCK DIAGRAM 24 ······ Photocell (Blue) D67 25 D66 11 D65 2 S5300 30 S5299 φ1 S2 φ2 S1 GND D64 GND D14 VOD Transfer gate VOUT1 31 (Blue) 22 φ TG2 (Green) 10 φ TG3 (Red) D67 D66 D65 S5300 Photocell (Green) S5299 S2 S1 D64 D14 ······ Transfer gate D67 D66 D65 S5300 Photocell (Red) S5299 S2 S1 ······ D64 D14 CCD analog shift register Transfer gate CCD analog shift register 1 Clamp pulse generator 2 φTG1 (Blue) CCD analog shift register VOUT2 (Green) 32 VOUT3 (Red) 23 3 8 9 φ RB φ2 φ1 DATA SHEET S14083EJ1V0DS00 µPD3799 PIN CONFIGURATION (Top View) CCD linear image sensor 32-pin plastic DIP (400 mil) • µPD3799CY 32 VOUT2 Output signal 2 (Green) Ground GND 2 31 VOUT1 Output signal 1 (Blue) Reset gate clock φ RB 3 30 VOD Output drain voltage No connection NC 4 29 NC No connection No connection NC 5 28 NC No connection Internal connection IC 6 27 IC Internal connection Internal connection IC 7 26 IC Internal connection Shift register clock 2 φ2 8 25 φ2 Shift register clock 2 Shift register clock 1 φ1 9 24 φ1 Shift register clock 1 Transfer gate clock 3 (for Red) φTG3 10 23 φ TG1 Transfer gate clock 1 (for Blue) Ground GND 11 22 φ TG2 Transfer gate clock 2 (for Green) Internal connection IC 12 21 IC Internal connection Internal connection IC 13 20 IC Internal connection No connection NC 14 19 NC No connection No connection NC 15 18 NC No connection No connection NC 16 17 NC No connection Blue 5300 Green 5300 Red 5300 1 1 1 VOUT3 1 Output signal 3 (Red) Caution Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected. DATA SHEET S14083EJ1V0DS00 3 µPD3799 PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing) 7 µm 7 µm 4 µm 3 µm 4 lines (28 µm) 7 µm Green photocell array Channel stopper 4 lines (28 µm) 7 µm Aluminum shield 4 Blue photocell array DATA SHEET S14083EJ1V0DS00 Red photocell array µPD3799 ABSOLUTE MAXIMUM RATINGS (TA = +25 °C) Parameter Symbol Ratings Unit Output drain voltage VOD –0.3 to +15 V Shift register clock voltage V φ1 , V φ2 –0.3 to +8 V Reset gate clock voltage VφRB –0.3 to +8 V Transfer gate clock voltage VφTG1 to VφTG3 –0.3 to +8 V Operating ambient temperature TA –25 to +60 °C Storage temperature Tstg –40 to +70 °C Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. RECOMMENDED OPERATING CONDITIONS (TA = +25 °C) Parameter Symbol MIN. TYP. MAX. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock high level Vφ1H, Vφ2H 4.5 5.0 5.5 V Shift register clock low level Vφ1L, Vφ2L –0.3 0 +0.5 V Reset gate clock high level VφRBH 4.5 5.0 5.5 V Reset gate clock low level VφRBL –0.3 0 +0.5 V Transfer gate clock high level VφTG1H to VφTG3H 4.5 Vφ1HNote Vφ1HNote V Transfer gate clock low level VφTG1L to VφTG3L –0.3 0 +0.5 V Data rate fφRB – 1.0 4.0 MHz Note When Transfer gate clock high level (VφTG1H to VφTG3H) is higher than Shift register clock high level (Vφ1H), Image lag can increase. DATA SHEET S14083EJ1V0DS00 5 µPD3799 ELECTRICAL CHARACTERISTICS TA = +25 °C, VOD = 12 V, data rate (fφRB) = 1 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm) + HA-50 (heat absorbing filter, t = 3 mm) Parameter Symbol Saturation voltage Test Conditions Vsat Saturation exposure Unit 2.0 2.5 – V 0.223 lx•s Green SEG 0.245 lx•s Blue SEB 0.409 lx•s VOUT = 1.0 V Average dark signal ADS Dark signal non-uniformity DSNU Power consumption Output impedance 6 20 % Light shielding 0.2 2.0 mV Light shielding 1.5 3.0 mV PW 360 540 mW ZO 0.5 1 kΩ Red RR 7.8 11.2 14.6 V/lx•s Green RG 7.1 10.2 13.3 V/lx•s Blue RB 4.2 6.1 8.0 V/lx•s 1.5 7.0 % 5.5 7.0 V Image lag IL Note1 Output fall delay time MAX. SER PRNU Offset level TYP. Red Photo response non-uniformity Response MIN. VOUT = 1.0 V VOS Note2 4.0 50 ns 98 % Red 630 nm Green 540 nm Blue 460 nm Total transfer efficiency td VOUT = 1.0 V TTE VOUT = 1.0 V, 92 data rate = 4 MHz Response peak Dynamic range Reset feed-through noise Random noise Note1 DR1 Vsat /DSNU 1666 times DR2 Vsat /σ 2500 times RFTN Light shielding –1000 –300 +500 mV σ Light shielding – 1.0 – mV Notes 1. Refer to TIMING CHART 2. 2. When the fall time of φ1 (t1) is the TYP. value (refer to TIMING CHART 2). 6 DATA SHEET S14083EJ1V0DS00 µPD3799 INPUT PIN CAPACITANCE (TA = +25 °C, VOD = 12 V) Parameter Shift register clock pin capacitance 1 Shift register clock pin capacitance 2 Symbol C φ1 C φ2 Pin name Pin No. φ1 φ2 MIN. TYP. MAX. Unit 9 400 pF 24 400 pF 8 400 pF 25 400 pF Reset gate clock pin capacitance CφRB φRB 3 15 pF Transfer gate clock pin capacitance CφTG φTG1 23 100 pF φTG2 22 100 pF φTG3 10 100 pF Remark Pins 9 and 24 (φ1), 8 and 25 (φ2) are each connected inside of the device. DATA SHEET S14083EJ1V0DS00 7 8 TIMING CHART 1 (for each color) φ TG1 to φ TG3 φ1 φ2 61 62 63 64 65 66 DATA SHEET S14083EJ1V0DS00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note 5363 5364 5365 5366 5367 5368 5369 φ RB Note VOUT1 to VOUT3 Optical black (49 pixels) Valid photocell (5300 pixels) Invalid photocell (2 pixels) Invalid photocell (3 pixels) Note Input the φ RB pulse continuously during this period, too. µPD3799 TIMING CHART 2 (for each color) t1 90 % φ1 10 % 90 % φ2 10 % t5 DATA SHEET S14083EJ1V0DS00 φ RB t2 t3 t6 t4 90 % 10 % + td RFTN VOUT _ RFTN VOS 10 % µPD3799 9 µPD3799 φTG1 to φTG3, φ1, φ2 TIMING CHART t7 t8 t9 90 % φ TG1 to φ TG3 10 % t11 t10 90 % φ1 φ2 Symbol MIN. TYP. MAX. Unit t1, t2 0 25 – ns t3 20 50 – ns t4 110 250 – ns t5, t6 0 25 – ns t7, t8 0 50 – ns t9 3000 10000 – ns t10, t11 900 1000 – ns φ1, φ2 cross points φ2 2.0 V or more 0.5 V or more φ1 Remark Adjust cross points of φ1 and φ2 with input resistance of each pin. 10 DATA SHEET S14083EJ1V0DS00 µPD3799 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = ∆x × 100 x ∆x : maximum of xj − x 5300 Σx x= j j=1 5300 xj : Output voltage of valid pixel number j VOUT Register Dark DC level 4. x ∆x Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 5300 Σd j ADS (mV) = j=1 5300 dj : Dark signal of valid pixel number j 5. Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj − ADS j = 1 to 5300 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU DATA SHEET S14083EJ1V0DS00 11 µPD3799 6. Output impedance: ZO Impedance of the output pins viewed from outside. 7. Response: R Output voltage divided by exposure (Ix•s). Note that the response varies with a light source (spectral characteristic). 8. Image Lag: IL The rate between the last output voltage and the next one after read out the data of a line. φTG Light ON OFF VOUT V1 VOUT V1 IL (%) = 9. VOUT ×100 Random noise: σ Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). 100 σ (mV) = Σi=1 (V – V) i 2 100 , V= 1 100 ΣV i 100 i=1 Vi: A valid pixel output signal among all of the valid pixels for each color VOUT V1 line 1 V2 line 2 … … V100 line 100 This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling). 12 DATA SHEET S14083EJ1V0DS00 µPD3799 STANDARD CHARACTERISTIC CURVES (Nominal) DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25 °C) 2 1 Relative Output Voltage 2 1 0.5 0.2 0.25 0.1 0 10 20 30 40 0.1 50 Operating Ambient Temperature TA(°C) 1 5 10 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25 °C) 100 R B G 80 Response Ratio (%) Relative Output Voltage 4 60 40 G 20 B 0 400 500 600 700 800 Wavelength (nm) DATA SHEET S14083EJ1V0DS00 13 µPD3799 APPLICATION CIRCUIT EXAMPLE +12 V +5 V 10 Ω + + µ PD3799 10 µ F/16 V 0.1 µ F B3 1 2 φ RB 47 Ω 3 0.1 µ F 47 µ F/25 V VOUT3 VOUT2 GND VOUT1 φ RB VOD NC NC NC NC 4 5 6 7 4.7 Ω 8 4.7 Ω 9 4.7 Ω 10 φ2 11 12 13 14 15 16 32 31 B2 B1 30 29 +5 V 28 + 27 IC IC IC IC φ2 φ2 φ1 φ1 φ TG3 φ TG1 GND φ TG2 0.1 µ F 10 µ F/16 V 26 25 4.7 Ω 24 4.7 Ω 23 4.7 Ω 22 4.7 Ω φ TG 21 IC IC IC IC NC NC NC NC NC NC 20 19 18 17 Caution Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected. Remark The inverters shown in the above application circuit example are the 74HC04. 14 DATA SHEET S14083EJ1V0DS00 φ1 µPD3799 B1 to B3 EQUIVALENT CIRCUIT 12 V + 100 Ω CCD VOUT 47 µF/25 V 100 Ω 2SC945 2 kΩ DATA SHEET S14083EJ1V0DS00 15 µPD3799 PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (400 mil) OUTLINE DRAWINGS (Unit : mm) 1st valid pixel 12.6±0.5 9.25±0.3 1 9.05±0.3 4.0±0.3 4.1±0.5 54.8±0.5 55.2±0.5 10.16 (1.80) 2.58±0.3 (5.42) 2.54 1.02±0.15 2 3 0.25±0.05 0~1 0° 4.21±0.5 0.46±0.06 4.55±0.5 38.1 Name Dimensions Refractive index Plastic cap 52.2×6.4×0.7 4 1.5 1 The 1st valid pixel The center of the pin1 2 The surface of the chip 3 The bottom of the package The top of the cap The surface of the chip 4 Thickness of plastic cap over CCD chip 32C-1CCD-PKG1-1 16 DATA SHEET S14083EJ1V0DS00 µPD3799 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "Semiconductor Device Mounting Technology Manual"(C10535E). Type of Through-hole Device µPD3799CY : CCD linear image sensor 32-pin plastic DIP (400 mil) Process Partial heating method Conditions Pin temperature: 300 °C or below, Heat time: 3 seconds or less (per pin) Caution During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. DATA SHEET S14083EJ1V0DS00 17 µPD3799 NOTES ON CLEANING THE PLASTIC CAP 1 CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. 2 RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents 18 Symbol Ethyl Alcohol EtOH Methyl Alcohol MeOH Isopropyl Alcohol IPA N-methyl Pyrrolidone NMP DATA SHEET S14083EJ1V0DS00 µPD3799 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. DATA SHEET S14083EJ1V0DS00 19 µPD3799 [MEMO] • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98.8