DATA SHEET MOS INTEGRATED CIRCUIT µPD3794 2700 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR The µPD3794 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The µPD3794 has 3 rows of 2700 pixels, and each row has a single-sided readout type of charge transfer register. And it has reset feed-through level clamp circuits, a clamp pulse generation circuit, an RGB selector and voltage amplifiers. Therefore, it is suitable for 300 dpi/A4 color image scanners, color facsimiles and so on. FEATURES • Valid photocell : 2700 pixels × 3 • Photocell's pitch : 8 µm • Line spacing : 32 µm (4 lines) Green line-Blue line, Blue line-Red line • Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour) • Resolution : 12 dot/mm A4 (210 × 297 mm) size (shorter side) 300 dpi US letter (8.5” × 11”) size (shorter side) • Drive clock level : CMOS output under 5 V operation • Data rate : 4 MHz MAX. • Power supply : +12 V • On-chip circuits : Reset feed-through level clamp circuits Clamp pulse generation circuit RGB selector Voltage amplifiers ORDERING INFORMATION Part Number Package µPD3794CY CCD linear image sensor 22-pin plastic DIP (400 mil) The information in this document is subject to change without notice. Document No.S13125EJ1V0DS00(1st edition) Date published December 1997 N CP(K) Printed in Japan © 1997 µPD3794 BLOCK DIAGRAM ······ Photocell (Green) D67 14 D66 φ1 15 D65 GND 11 S2700 GND 2 S2699 GND 19 S2 VOD S1 20 D15 22 D64 SEL1 SEL2 Transfer gate 13 φ TG1 (Green) 12 φ TG2 (Blue) 10 φ TG3 (Red) D67 D66 D65 S2700 Photocell (Blue) S2699 S2 S1 ······ D64 D15 CCD analog shift register Transfer gate 1 D67 D66 D65 S2700 Photocell (Red) S2699 S2 S1 ······ D64 CCD analog shift register D15 VOUT Transfer gate CCD analog shift register Clamp pulse generator 2 3 9 φ RB φ2 µPD3794 PIN CONFIGURATION (Top View) CCD linear image sensor 22-pin plastic DIP (400 mil) 22 SEL1 RGB select input 1 Ground GND 2 21 NC No connection Reset gate clock φ RB 3 20 SEL2 RGB select input2 No connection NC 4 19 VOD Output drain voltage No connection NC 5 18 NC No connection No connection NC 6 17 NC No connection No connection NC 7 16 NC No connection No connection NC 8 15 GND Ground Shift register clock 2 φ2 9 14 φ1 Shift register clock 1 Transfer gate clock 3 (for Red) φTG3 10 13 φ TG1 Transfer gate clock 1 (for Green) Ground GND 11 12 φ TG2 Transfer gate clock 2 (for Blue) 8 µm Green PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing) 8 µm 5 µm 2700 Blue 2700 Red 2700 PHOTOCELL STRUCTURE DIAGRAM 1 1 1 VOUT 1 Output signal Green photocell array 3 µm 4 lines (32 µm) 8 µm Blue photocell array Channel stopper 4 lines (32 µm) 8 µm Red photocell array Aluminum shield 3 µPD3794 ABSOLUTE MAXIMUM RATINGS (TA = +25 °C) Parameter Symbol Ratings Unit Output drain voltage VOD –0.3 to +15 V Shift register clock voltage Vφ1, Vφ2 –0.3 to +8 V Reset gate clock voltage VφRB –0.3 to +8 V Transfer gate clock voltage VφTG1 to VφTG3 –0.3 to +8 V RGB select input voltage VSEL1,VSEL2 –0.3 to +8 V Operating ambient temperature TA –25 to +60 °C Storage temperature Tstg –40 to +70 °C Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. RECOMMENDED OPERATING CONDITIONS (TA = +25 °C) Parameter MIN. TYP. MAX. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock high level Vφ1H, Vφ2H 4.5 5.0 5.5 V Shift register clock low level Vφ1L, Vφ2L –0.3 0 +0.5 V Reset gate clock high level VφRBH 4.5 5.0 5.5 V Reset gate clock low level VφRBL –0.3 0 +0.5 V Transfer gate clock high level VφTG1H to VφTG3H 4.5 Vφ1HNote Vφ1HNote V Transfer gate clock low level VφTG1L to VφTG3L –0.3 0 +0.5 V RGB select input high level VSEL1H, VSEL2H 4.5 5.0 5.5 V RGB select input low level VSEL1L, VSEL2L –0.3 0 +0.5 V Data rate fφRB – 1.0 4.0 MHz Note When Transfer gate clock high level (VφTG1H to VφTG3H) is higher than Shift register clock high level (Vφ1H), Image lag can increase. 4 Symbol µPD3794 ELECTRICAL CHARACTERISTICS TA = +25 °C, VOD = 12 V, data rate (fφ RB) = 1 MHz, storage time = 10 ms, light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 Vp-p Parameter Symbol Saturation voltage Saturation exposure Test Conditions Vsat TYP. MAX. Unit 2.0 3.0 V Red SER 0.205 lx•s Green SEG 0.225 lx•s Blue SEB 0.375 lx•s Photo response non-uniformity PRNU VOUT = 1.0 V Average dark signal ADS Dark signal non-uniformity DSNU Power consumption Output impedance Response MIN. 6 20 % Light shielding 0.5 5.0 mV Light shielding 4.0 10.0 mV PW 300 600 mW ZO 0.5 1 kΩ Red RR 10.3 14.6 18.9 V/lx•s Green RG 9.4 13.3 17.2 V/lx•s Blue RB 5.6 8.0 10.4 V/lx•s 5.0 10.0 % 6.0 7.5 V Image lag IL VOUT = 1.0 V Offset level Note1 VOS Output fall delay time Note2 td VOUT = 1.0 V Total transfer efficiency TTE VOUT = 1.0 V, 4.5 70 ns 98 % Red 630 nm Green 540 nm Blue 460 nm 92 data rate = 4 MHz Response peak Dynamic range DR1 Vsat /DSNU 750 times DR2 Vsat /σ 3000 times Reset feed-through noise Note1 RFTN Light shielding –1000 –300 +500 mV Random noise σ Light shielding – 1.0 – mV Notes 1. Refer to TIMING CHART 2. 2. When the fall time of φ1 (t1) is the TYP. value (refer to TIMING CHART 2). 5 µPD3794 INPUT PIN CAPACITANCE (TA = +25 °C, VOD = 12 V) Parameter Symbol Pin No. MIN. TYP. MAX. Unit Shift register clock pin capacitance 1 C φ1 φ1 14 300 pF Shift register clock pin capacitance 2 C φ2 φ2 9 300 pF Reset gate clock pin capacitance CφRB φRB 3 20 pF Transfer gate clock pin capacitance CφTG φTG1 13 50 pF φTG2 12 50 pF φTG3 10 50 pF SEL1 22 50 pF SEL2 20 50 pF RGB select input pin capacitance CSEL RGB SELECT FUNCTION RGB select input Output color SEL1 6 Pin name SEL2 High level High level Blue High level Low level Green Low level High level Red Low level Low level Prohibited TIMING CHART 1-1 SEL1 SEL2 φ TG1 to φ TG3 a b φ1 φ2 61 62 63 64 65 66 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note 2763 2764 2765 2766 2767 2768 2769 φ RB Note VOUT (Blue) Optical black (48 pixels) Valid photocell (2700 pixels) Invalid photocell (2 pixels) 7 µPD3794 Note Input the φ RB pluse continuously during this period, too. Invalid photocell (3 pixels) 8 TIMING CHART 1-2 SEL1 SEL2 φ TG1 to φ TG3 b c φ1 φ2 61 62 63 64 65 66 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note 2763 2764 2765 2766 2767 2768 2769 φ RB Note VOUT (Green) Optical black (48 pixels) Valid photocell (2700 pixels) Invalid photocell (2 pixels) Invalid photocell (3 pixels) Note Input the φ RB pluse continuously during this period, too. µPD3794 TIMING CHART 1-3 SEL1 SEL2 φ TG1 to φ TG3 c a φ1 φ2 61 62 63 64 65 66 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note 2763 2764 2765 2766 2767 2768 2769 φ RB Note VOUT (Red) Optical black (48 pixels) Valid photocell (2700 pixels) Invalid photocell (2 pixels) 9 µPD3794 Note Input the φ RB pluse continuously during this period, too. Invalid photocell (3 pixels) µPD3794 TIMING CHART 2 (for each color) t1 φ1 90 % 10 % φ2 90 % 10 % t5 φ RB t3 t6 t2 t4 90 % 10 % + td RFTN VOUT _ 10 % φTG1 to φTG3, φ1, φ2 TIMING CHART t8 t9 t7 90 % φ TG1 to φ TG3 10 % t11 t10 90 % φ1 φ2 Symbol MIN. TYP. t1, t2 0 25 ns t3 30 50 ns t4 150 250 ns 0 25 ns 3000 10000 ns 0 50 ns 900 1000 ns t5, t6 t7 t8, t9 t10, t11 MAX. Unit φ1, φ2 cross points φ1 2 V or more 2 V or more φ2 10 Remark Adjust cross points of φ1 and φ2 with input resistance of each pin. RFTN VOS µPD3794 APPLICATION TIMING EXAMPLE (for reference) The µPD3794 can be operated under the following timing to switch Red, Green, and Blue outputs and get each color data in a 1-pixel period. However the offset level of each color is not the same. Therefore, offset level compensation is required to each color by using each color’s data at dark or the optical black pixels. The following timing and parameters are for reference only. SEL1 SEL2 tR tG tB φ1 φ2 φ RB at dark VOUT with light Red Green Symbol MIN. TYP. tR , t G, t B 300 – Blue MAX. Unit ns 11 µPD3794 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = ∆x × 100 x ∆x : maximum of xj − x 2700 Σx j x= j=1 2700 xj : Output voltage of valid pixel number j VOUT Register Dark DC level 4. x ∆x Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 2700 Σd ADS (mV) = j j=1 2700 dj : Dark signal of valid pixel number j 5. Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj − ADS j = 1 to 2700 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 12 µPD3794 6. Output impedance: ZO Impedance of the output pins viewed from outside. 7. Response: R Output voltage divided by exposure (Ix•s). Note that the response varies with a light source (spectral characteristic). 8. Image Lag: IL The rate between the last output voltage and the next one after read out the data of a line. φTG Light ON OFF VOUT V1 VOUT V1 IL (%) = 9. VOUT ×100 Random noise: σ Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). 100 σ (mV) = Σi=1 (V – V) i 2 100 , V= 1 100 ΣV i 100 i=1 Vi: A valid pixel output signal among all of the valid pixels for each color VOUT V1 line 1 V2 line 2 … … V100 line 100 This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling). 13 µPD3794 STANDARD CHARACTERISTIC CURVES DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25 °C) 2 Relative Output Voltage Relative Output Voltage 4 2 1 0.5 1 0.2 0.25 0.1 0 10 20 30 40 0.1 50 Operating Ambient Temperature TA(°C) 1 5 10 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter) (TA = +25 °C) 100 R B G Response Ratio (%) 80 60 40 G 20 B 0 400 500 600 Wavelength (nm) 14 700 800 µPD3794 APPLICATION CIRCUIT EXAMPLE +5 V +12 V 10 Ω + + µ PD3794 10 µ F/16 V 0.1 µ F B 1 2 47 Ω φ RB 3 VOUT SEL1 GND NC φ RB SEL2 4 NC VOD NC NC NC NC NC NC NC GND 22 7 8 4.7 Ω 9 10 Ω 10 φ2 11 Remark SEL1 20 47 Ω SEL2 19 +5 V 18 17 φ2 φ TG1 GND φ TG2 + 16 0.1 µ F 10 µ F/16 V 15 φ1 φ TG3 0.1 µ F 47 µ F/25 V 21 5 6 47 Ω 14 4.7 Ω 13 10 Ω 12 10 Ω φ1 φ TG Inverters: 74HC04 B EQUIVALENT CIRCUIT 12 V + 100 Ω CCD VOUT 47 µF/25 V 100 Ω 2SC945 2 kΩ 15 µPD3794 PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 22PIN PLASTIC DIP (400 mil) (Unit : mm) 1st valid pixel 9.25±0.3 3 2.0 3.95±0.3 37.5 44.0±0.3 10.16 (1.99) 2.35±0.2 1 (5.42) 2.54 1.02±0.15 0~10° 4.21±0.5 0.46±0.1 0.05 0.25± 4.39±0.4 25.4 Name Plastic cap Dimensions 42.9 x 8.35 x 0.7 1 The bottom of the package Refractive index 2 1.5 The surface of the chip 2 The thickness of the cap over the chip 3 The 1st valid pixel The center of the pin 1. 22C-1CCD-PKG10-1 16 µPD3794 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "Semiconductor Device Mounting Technology Manual"(C10535E). Type of Through-hole Device µPD3794CY: CCD linear image sensor 22-pin plastic DIP (400 mil) Process Partial heating method Caution Conditions Pin temperature: 260 °C or below, Heat Time: 10 seconds or less (per pin) During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. 17 µPD3794 NOTES ON CLEANING THE PLASTIC CAP 1 CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. 2 RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents 18 Symbol Ethyl Alcohol EtOH Methyl Alcohol MeOH Isopropyl Alcohol IPA N-methyl Pyrrolidone NMP µPD3794 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 19 µPD3794 [MEMO] The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5