DATA SHEET MOS INTEGRATED CIRCUIT µPD3720A 2700 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR The µPD3720A is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The µPD3720A has 3 rows of 2700 pixels and 3 pairs of 2 rows of 1350-bit charge transferred registers, reset feedthrough level clamp circuits, clamp pulse generation circuit and voltage amplifiers. It is suitable for color image scanners, color facsimiles and so on. FEATURES • Valid photocell : 2700 pixels × 3 • Photocell's pitch : 10.5 µm • Line spacing : 42 µm (4 lines) Red line-Green line, Green line-Blue line • Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour) • Resolution : 12 dot/mm A4 (210 × 297 mm) size (shorter side) 300 dpi US letter (8.5” × 11”) size (shorter side) • Drive clock level : CMOS output under 5 V operation • Data rate : 3 MHz MAX. • Power supply : +12 V • On-chip circuits : Reset feed-through level clamp circuits Clamp pulse generation circuit Voltage amplifiers • Pin assign : Compatible with the µPD3720 ORDERING INFORMATION Part Number Package µPD3720ACY CCD linear image sensor 22-pin plastic DIP (400 mil) The information in this document is subject to change without notice. Document No. S12035EJ1V0DS00(1st edition) Date published November 1996 N Printed in Japan © 1996 µPD3720A COMPARISON CHART µPD3720A Item PIN CONFIGURATION Pin 11 ELECTRICAL CHARACTERISTICS Output fall delay time TYP. (ns) TIMING CHART Output signal waveform µPD3720 Analog ground Digital ground 70 80 Spike noise reduced – BLOCK DIAGRAM VOD AGND AGND φ 2L φ1 19 2 11 17 14 CCD analog shift register 13 φ TG1 D67 D66 D65 S2700 Photocell S2699 S2 ........ S1 21 D64 VOUT1 (B) D14 Transfer gate Transfer gate CCD analog shift register CCD analog shift register 12 φ TG2 D67 D66 D65 S2700 Photocell S2699 S2 ........ S1 22 D64 VOUT2 (G) D14 Transfer gate Transfer gate CCD analog shift register Clamp pulse generator CCD analog shift register φ TG3 D67 D66 D65 S2700 Photocell 10 S2699 S2 ........ S1 1 D64 VOUT3 (R) D14 Transfer gate Transfer gate CCD analog shift register 2 3 4 9 φ RB φ 1L φ2 µPD3720A PIN CONFIGURATION (Top View) CCD linear image sensor 22-pin plastic DIP(400 mil) 22 VOUT2 Output signal 2 (GREEN) Analog ground AGND 2 21 VOUT1 Output signal 1 (BLUE) Reset gate clock φ RB 3 20 NC No connection Last stage shift register clock 1 φ 1L 4 19 VOD Output drain voltage No connection NC 5 18 NC No connection No connection NC 6 17 φ 2L Last stage shift register clock 2 No connection NC 7 16 NC No connection No connection NC 8 15 NC No connection Shift register clock 2 φ2 9 14 φ1 Shift register clock 1 Transfer gate clock 3 φ TG3 10 13 φ TG1 Transfer gate clock 1 Analog ground AGND 11 12 φ TG2 Transfer gate clock 2 2700 B G 2700 R 2700 1 1 1 VOUT3 1 Output signal 3 (RED) PHOTOCELL STRUCTURE DIAGRAM 10.5 µ m 7.5 µ m 3 µm Channel stopper Aluminum shield 3 µPD3720A ABSOLUTE MAXIMUM RATINGS (TA = +25 °C) Parameter Symbol Ratings Unit Output drain voltage VOD –0.3 to +15 V Shift register clock voltage Vφ1, Vφ2, Vφ1L, Vφ2L –0.3 to +15 V Reset gate clock voltage VφRB –0.3 to +15 V Transfer gate clock voltage VφTG1 – VφTG3 –0.3 to +15 V Operating ambient temperature TA –25 to +60 °C Storage temperature Tstg –40 to +70 °C Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. RECOMMENDED OPERATING CONDITIONS (TA = +25 °C) Parameter 4 Symbol MIN. TYP. MAX. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock signal high level Vφ1H, Vφ2H, Vφ1LH, Vφ2LH 4.5 5.0 5.5 V Shift register clock signal low level Vφ1L, Vφ2L, Vφ1LL, Vφ2LL –0.3 0 +0.5 V Reset gate clock high level VφRBH 4.5 5.0 5.5 V Reset gate clock low level VφRBL –0.3 0 +0.5 V Transfer gate clock high level VφTG1H – VφTG3H 4.5 5.0 5.5 V Transfer gate clock low level VφTG1L – VφTG3L –0.3 0 +0.5 V Data rate fφRB – 1 3 MHz µPD3720A ELECTRICAL CHARACTERISTICS TA = +25 °C, VOD = 12 V, fφRB = 1 MHz, data rate = 1 MHz, storage time = 5 ms, light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 Vp-p Parameter Symbol Saturation voltage Saturation exposure Test Conditions Vsat MAX. Unit 2.0 3.0 – V SER 0.15 lx•s Green SEG 0.16 lx•s Blue SEB 0.27 lx•s PRNU VOUT = 1 V Average dark signal ADS Dark signal non-uniformity DSNU Power consumption Output impedance 6 20 % Light shielding 0.5 2.5 mV Light shielding 1.5 8.0 mV PW 400 600 mW ZO 0.5 1 kΩ Red RR 14.14 20.20 26.26 V/lx•s Green RG 12.95 18.50 24.05 V/lx•s Blue RB 7.77 11.10 14.43 V/lx•s 2 10 % 4.5 6.6 V Image lag IL Offset level Note1 VOS Output fall delay time Note2 td VOUT = 1 V Total transfer efficiency TTE VOUT = 1 V, data rate = 3 MHz Register imbalance RI VOUT = 1 V Response peak TYP. Red Photo response non-uniformity Response MIN. VOUT = 1 V 3 70 ns 92 98 % 0 1.0 4.0 % Red 630 nm Green 540 nm Blue 460 nm Dynamic range DR1 Vsat /DSNU 2000 times DR2 Vsat /σ 3000 times Reset feed-through noise Note1 RFTN Light shielding –1000 –300 +300 mV Random noise σ Light shielding – 1.0 – mV Notes 1. Refer to TIMING CHART2. 2. When each fall delay time of φ1L and φ2L (t2´, t1´) is the TYP. value (refer to TIMING CHART 2). 5 µPD3720A INPUT PIN CAPACITANCE Parameter Transfer gate clock pin capacitance 6 Symbol CφTG Pin name Pin No. MIN. TYP. MAX. Unit φTG1 13 200 pF φTG2 12 200 pF φTG3 10 200 pF Reset gate clock pin capacitance CφRB φRB 3 50 pF Last stage shift register clock pin capacitance C φL φ1L 4 30 pF φ2L 17 30 pF Shift register clock pin capacitance 1 C φ1 φ1 14 700 pF Shift register clock pin capacitance 2 C φ2 φ2 9 700 pF µPD3720A TIMING CHART 1 (for each color) 8 7 6 5 4 3 2 φ1 1 φ TG1 to φ TG3 φ2 φ 1L φ 2L 2769 2768 2767 2766 2765 2764 2763 66 65 64 63 62 61 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 φ RB VOUT1 to VOUT3 Valid photocell (2700 pixels) Optical black (49 pixels) Invalid photocell (2 pixels) Invalid photocell (3 pixels) TIMING CHART 2 (for each color) t1 t2 90 % φ1 10 % 90 % φ2 10 % 90 % 10 % φ 1L t2' 90 % φ 2L t5 φ RB t1' t3 t6 10 % t4 td 90 % 10 % + RFTN RFTN 90 % VOUT − 10 % VOS 7 µPD3720A φTG1 to φTG3, φ1, φ2 TIMING CHART t7 t8 t10 90 % φ TG 10 % t11 t9 90 % φ1 φ2 Symbol MIN. TYP. MAX. Unit t1, t2 0 50 – ns t1´, t2´ 0 5 – ns t4 130 300 – ns t3 20 150 – ns t5, t6 0 50 – ns t7, t8 0 50 – ns t9, t11 900 1000 – ns t10 3000 10000 – ns φ 1, φ 2 cross points φ 1L, φ 2 cross points φ1 φ2 2 V or more φ2 2 V or more 2 V or more φ 1L φ 1, φ 2L cross points φ1 2 V or more φ 2L Remark 8 0.5 V or more Adjust cross points (φ1, φ2), (φ1L, φ2) and (φ1, φ2L) with input resistance of each pin. 0.5 V or more µPD3720A DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time(s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. ∆x × 100 x PRNU (%) = ∆x : maximum of xj − x 2700 Σx j x= j=1 2700 xj : Output voltage of valid pixel number j VOUT x Register Dark DC level 4. ∆x Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 2700 Σd ADS (mV) = j j=1 2700 dj : Dark signal of valid pixel number j 9 µPD3720A 5. Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV): maximum of | dj – ADS | j = 1 to 2700 dj: Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance: ZO Impedance of the output pins viewed from outside. 7. Response: R Output voltage divided by exposure (Ix•s). Note that the response varies with a light source (spectral characteristic). 8. Image Lag: IL The rate between the last output voltage and the next one after read out the data of a line. φTG ON Light OFF VOUT V1 VOUT V1 IL (%) = 10 VOUT ×100 µPD3720A 9. Register Imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. n 2 Σ (V 2 n – V2j) 2j – 1 j=1 RI (%) = 1 n × 100 n ΣV j j=1 n : Number of valid pixels Vj : Output voltage of each pixel 10. Random noise: σ Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). 100 σ= Σ (V – V) i i=1 2 , V= 100 1 100 ΣV i 100 i=1 Vi : A valid pixel output signal among all of the valid pixels for each color VOUT V1 line 1 V2 line 2 … … V100 line 100 This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling). 11 µPD3720A STANDARD CHARACTERISTIC CURVES (TA = +25 °C) DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC 2 Relative Output Voltage Relative Output Voltage 4 2 1 0.5 0.2 0.25 0.1 0 1 10 20 30 40 0.1 50 1 5 Operating Ambient Temperature TA(°C) 10 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter) 100 B R Response Ratio (%) 80 G 60 40 G 20 B 0 400 500 600 Wavelength (nm) 12 700 800 µPD3720A APPLICATION CIRCUIT EXAMPLE 10 Ω +12 V + B3 1 2 φ RB 47 Ω 47 Ω AGND VOUT1 φ RB NC 4 φ 1L VOD NC NC NC φ 2L 6 7 8 9 10 Ω VOUT2 3 5 φ2 VOUT3 10 11 22 0.1 µ F 47 µ F/25 V B2 21 B1 20 19 18 47 Ω 17 NC NC 16 NC NC φ2 φ1 14 φ TG3 φ TG1 13 AGND φ TG2 12 15 φ1 10 Ω φ TG 10 Ω B1 to B3 EQUIVALENT CIRCUIT 12 V + 100 Ω CCD VOUT 100 Ω 47 µ F/25 V 2SC945 2 kΩ Remark Inverters : µ PD74HC04 13 µPD3720A PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 22PIN PLASTIC DIP (400 mil) (Unit : mm) 1bit 9.25±0.3 2.0 0.5±0.3 37.5 44.0±0.3 10.16 (1.79) 2.55±0.2 1 1.02±0.15 (5.42) 2.54 4.21±0.5 0.46±0.1 0 ∼ 10° 0.05 0.25± 4.39±0.4 25.4 Name Plastic cap Dimensions 42.9 × 8.35 × 0.7 1 The bottom of the package Refractive index 2 1.5 The surface of the chip 2 The thickness of the cap over the chip 22C-1CCD-PKG6 14 µPD3720A RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "Semiconductor Device Mounting Technology Manual"(C10535E). Type of Through-hole Device µPD3720ACY: CCD linear image sensor 22-pin plastic DIP (400 mil) Process Conditions Wave soldering (only to leads) Solder temperature: 260 ˚C or below, Flow time: 10 seconds or less. Partial heating method Pin temperature: 260 ˚C or below, Heat time: 10 seconds or less (per each lead). Caution For through-hole device, the wave soldering process must be applied only to leads, and make sure that the package body dose not get jet soldered. During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. 15 µPD3720A NOTES ON CLEANING THE PLASTIC CAP 1 CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. 2 RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents 16 Symbol Ethyl Alcohol EtOH Methyl Alcohol MeOH Isopropyl Alcohol IPA N-methyl Pyrrolidone NMP µPD3720A [MEMO] 17 µPD3720A [MEMO] 18 µPD3720A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 19 µPD3720A [MEMO] The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5