SM5842AP/APT NIPPON PRECISION CIRCUITS INC. High-Class Audio Multi-function Digital Filter OVERVIEW The SM5842AP/APT is a multi-function digital filter IC, fabricated using NPC’s Molybdenum-gate CMOS process, for digital audio reproduction equipment. It features 8-times oversampling (interpolation), independent left and right-channel digital deemphasis, and soft muting functions. It accepts 16, 18, 20 or 24-bit input data, and outputs data in 18, 20, 22 or 24-bit format. It operates using either a 384fs or 256fs system clock at sampling frequencies up to 48 kHz + 10% (384fs SM5842AP, 384/256fs SM5842APT). ■ ■ ■ ■ ■ Filter Configuration ■ FEATURES Functions ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Linear phase 3-stage FIR interpolation filter • 169-tap 1st stage (fs to 2fs) • 29-tap 2nd stage (2fs to 4fs) • 17-tap 3rd stage (4fs to 8fs) Deemphasis filter - IIR filter configuration for accurate gain and phase characteristics 26 × 24-bit parallel multiplier/32-bit accumulator for high precision Overflow limiter built-in APPLICATIONS ■ ■ ■ CD players DAT players PCM systems PINOUT DI / INF2N 1 28 LRCI DG BCKI BCKO CKSLN WCKO INF1N IW1N / DIL DOL SM5842AP/APT ■ ■ L/R 2-channel processing 8-times oversampling (interpolation) • ≤ ±0.00002 dB passband ripple • ≥ 117 dB stopband attenuation Digital deemphasis • 32/44.1/48 kHz sampling frequency (fs) • 2-channel independent ON/OFF control Soft muting • 2-channel independent ON/OFF control Input data format • 2s complement, MSB first - LR alternating, 16/18/20/24-bit serial, trailing data - LR alternating, 24-bit serial, leading data - LR simultaneous, 24-bit serial, leading data Output data format • 2s complement, MSB first, LR simultaneous • 18/20/22/24-bit serial • BCKO burst (NPC format) Dither round-up processing • ON (dither rounding)/OFF (normal rounding) control 25-bit internal data length Jitter-free function for correct operation in the presence of jitter between the system clock and LRCI clock • ON (jitter-free mode)/OFF (sync mode) control 256fs/384fs system clock selectable • 384fs - 21.2 MHz maximum frequency (at maximum fs = 55.2 kHz) • 256fs - 13 MHz maximum frequency (at maximum fs = 50.7 kHz, SM5842AP) - 14.2 MHz maximum frequency (at maximum fs = 55.2 kHz, SM5842APT) Crystal oscillator circuit built-in TTL-compatible input/outputs 5.0 ± 0.25 V supply Molybdenum-gate CMOS process 28-pin plastic DIP XTI XTO VSS CKO IW2N / DIR DOR VDD DITHN MUTEL MUTER OW1N FSEL2 OW2N FSEL1 SYNCN DEMPL RSTN 14 15 DEMPR NIPPON PRECISION CIRCUITS—1 SM5842AP/APT PACKAGE DIMENSIONS Unit: mm 2.54 0.45 0.1 4.5 0.3 3.2 0.2 7.7 0.5 3.8 0.1 + 0.3 1.5 −0.05 + 0.25− 0.10 0.05 37.3 0.3 15.2 13.8 0.2 0° to 15° 28-pin plastic DIP BLOCK DIAGRAM CKSLN LRCI XTI XTO DI / INF2N BCKI System Clock IW1N / DIL IW2N / DIR Input Data Interface INF1N Filter and Attenuation Arithmetic block DITHN CKO RSTN SYNCN Timing Controller DEMPL DEMPR FSEL1 Deemphasis Control OW1N Output Data Interface FSEL2 OW2N MUTEL Mute Control MUTER VSS VDD BCKO WCKO DOL DOR DG NIPPON PRECISION CIRCUITS—2 SM5842AP/APT PIN DESCRIPTION Number Name I/O1 1 DI/INF2N Ip Data input when INF1N is LOW, and input format select pin 2 when INF1N is HIGH. 2 BCKI Ip Input bit clock 3 CKSLN Ip Oscillator and system clock select input. 384fs when HIGH, and 256fs when LOW. Description Input format select pin 1. INF1N and INF2N select the pin functions below. Pin function selection INF1N 4 INF1N Ip DI/INF2N Input format LOW LOW LOW HIGH HIGH LOW LR alternating, leading data HIGH HIGH LR simultaneous, leading data DI/INF2N IW1N/DIL IW2N/DIR DI IW1N IW2N INF2N DIL DIR LR alternating, trailing data Input bit length select pin 1 when INF1N is LOW, and left-channel data input when INF1N is HIGH. IW1N and IW2N select the input data length. INF1N 5 IW1N/DIL Ip IW2N/DIL IW1N/DIR Input bit length LOW LOW 24 bits LOW HIGH 20 bits HIGH LOW 18 bits HIGH HIGH 16 bits × × 24 bits LOW HIGH 6 XTI I Oscillator input connection 7 XTO O Oscillator output connection 8 VSS – Ground 9 CKO O Oscillator output clock. Same frequency as XTI. 10 IW2N/DIR Ip Input bit length select pin 2 when INF2N is LOW, and right-channel data input when INF2N is HIGH. IW1N and IW2N select the input data length as shown in the table for pin 5. Output length select bits. 11 12 OW1N OW2N Ip Ip OW2N OW1N Output bit length LOW LOW 24 bits LOW HIGH 22 bits HIGH LOW 20 bits HIGH HIGH 18 bits 13 SYNCN Ip Sync mode select pin. Normal sync mode when LOW, and jitter-free mode when HIGH. 14 RSTN Ip System reset. Reset operation when LOW, and normal operation when HIGH. 15 DEMPR Ip Right-channel deemphasis control signal. OFF when LOW, and ON when HIGH. 16 DEMPR Ip Left-channel deemphasis control signal. OFF when LOW, and ON when HIGH. Deemphasis filter select inputs 17 18 FSEL1 FSEL2 Ip Ip FSEL1 FSEL2 Sampling frequency (fs) LOW LOW 44.1 kHz LOW HIGH 48 kHz HIGH LOW Invalid setting HIGH HIGH 32 kHz NIPPON PRECISION CIRCUITS—3 SM5842AP/APT Number Name I/O1 19 MUTER Ip Right-channel mute signal. Muting when HIGH, and normal output when LOW. 20 MUTEL Ip Left-channel mute signal. Muting when HIGH, and normal output when LOW. 21 DITHN Ip Dither processing control. ON when LOW, and OFF when HIGH. 22 VDD – 5 V supply 23 DOR O Right-channel data output 24 DOL O Left-channel data output 25 WCKO O Output word clock 26 BCKO O Output bit clock 27 DG O Deglitched output 28 LRCI Ip Input data sample rate (fs) clock Description 1. I = input, Ip = Input with pull-up resistor, O = output NIPPON PRECISION CIRCUITS—4 SM5842AP/APT SPECIFICATIONS Absolute Maximum Ratings VSS = 0 V Parameter Symbol Rating Unit Supply voltage range VDD −0.3 to 7.0 V Input voltage range VIN −0.3 to VDD + 0.3 V Storage temperature range Tstg −40 to 125 °C Power dissipation PD 550 mW Soldering temperature Tsld 255 °C Soldering time tsld 10 s Condition Rating Unit 4.75 to 5.25 V Recommended Operating Conditions VSS = 0 V Parameter Symbol Supply voltage range VDD Operating temperature range Topr SM5842AP −20 to 80 SM5842APT −20 to 70 °C DC Electrical Characteristics VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter Symbol Condition VDD = 5.0 V1 Unit min typ max – 60 80 mA Current consumption IDD XTI HIGH-level input voltage VIH1 0.7VDD – – V XTI LOW-level input voltage VIL1 – – 0.3VDD V HIGH-level input voltage2 VIH2 2.4 – – V LOW-level input voltage2 VIL2 – – 0.5 V HIGH-level output voltage3 VOH1 IOH = −0.4 mA 2.5 – – V LOW-level output voltage3 VOL1 IOL = 1.6 mA – – 0.4 V XTO HIGH-level output voltage VOH2 IOH = −1.0 mA VDD − 0.5 – – V XTO LOW-level output voltage VOL2 IOL = 1.0 mA – – 0.4 V XTI HIGH-level input current ILH VIN = VDD – 10 20 µA XTI LOW-level input current ILL1 VIN = 0 V – 10 20 µA LOW-level input current2 ILL2 VIN = 0 V – 10 20 µA Input leakage current2 IIH VIN = VDD – – 1.0 µA 1. fSYS = 256fs = 14.2 MHz (CKSLN = LOW), no output load 2. Pins DI/INF2N, BCKI, CKSLN, INF1N, IW1N/DIL, IW2N/DIR, OW1N, OW2N, SYNCN, RSTN, DEMPR, DEMPL, FSEL1, FSEL2, MUTER, MUTEL, DITHN, LRCI 3. Pins CKO, DOL, DOR, BCKO, WCKO, DG NIPPON PRECISION CIRCUITS—5 SM5842AP/APT AC Electrical Characteristics Input Clock (XTI: SM5842AP) Crystal oscillator fs = 384fs (CKSLN = HIGH): VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter Symbol Oscillator frequency Unit fOSC min typ max 2.0 – 21.2 MHz fs = 256fs (CKSLN = LOW): VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter Symbol Oscillator frequency Unit fOSC min typ max 1.0 – 13.0 MHz External clock input fs = 384fs (CKSLN = HIGH): VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter Symbol Unit min typ max Clock HIGH-level pulsewidth tCWH 20 – 250 ns Clock LOW-level pulsewidth tCWL 20 – 250 ns tXI 47 – 500 ns Clock pulse cycle time fs = 256fs (CKSLN = LOW): VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter Symbol Unit min typ max Clock HIGH-level pulsewidth tCWH 35 – 500 ns Clock LOW-level pulsewidth tCWL 35 – 500 ns tXI 76 – 1000 ns Clock pulse cycle time VIH1 XTI 0.5VDD tCWH tCWL VIL1 tXI NIPPON PRECISION CIRCUITS—6 SM5842AP/APT Input Clock (XTI: SM5842APT) Crystal oscillator fs = 384fs (CKSLN = HIGH): VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 70 °C Rating Parameter Symbol Oscillator frequency Unit fOSC min typ max 2.0 – 21.2 MHz fs = 256fs (CKSLN = LOW): VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 70 °C Rating Parameter Symbol Oscillator frequency Unit fOSC min typ max 1.0 – 14.2 MHz External clock input fs = 384fs (CKSLN = HIGH): VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 70 °C Rating Parameter Symbol Unit min typ max Clock HIGH-level pulsewidth tCWH 20 – 250 ns Clock LOW-level pulsewidth tCWL 20 – 250 ns tXI 47 – 500 ns Clock pulse cycle time fs = 256fs (CKSLN = LOW): VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 70 °C Rating Parameter Symbol Unit min typ max Clock HIGH-level pulsewidth tCWH 30 – 500 ns Clock LOW-level pulsewidth tCWL 30 – 500 ns tXI 70 – 1000 ns Clock pulse cycle time VIH1 XTI 0.5VDD tCWH tCWL VIL1 tXI NIPPON PRECISION CIRCUITS—7 SM5842AP/APT Serial input timing (BCKI, DI, DIL, DIR, LRCI) SM5842AP: VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 80 °C SM5842APT: VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 70 °C Rating Parameter Symbol Unit min typ max BCKI HIGH-level pulsewidth tBCWH 50 – – ns BCKI LOW-level pulsewidth tBCWL 50 – – ns BCKI pulse cycle tBCY 100 – – ns DIN setup time tDS 50 – – ns DIN hold time tDH 50 – – ns Last BCKI rising edge to LRCI edge tBL 50 – – ns LRCI edge to first BCKI rising edge tLB 50 – – ns tBCY tBCWH tBCWL 1.5V BCKI tDS tDH DI DIL DIR 1.5V tLB tBL 1.5V LRCI Reset timing (RSTN) SM5842AP: VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 80 °C SM5842APT: VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 70 °C Rating Parameter RST LOW-level reset pulsewidth Symbol tRST Condition Unit min typ max At power-ON 1 – – µs At all other times 50 – – ns NIPPON PRECISION CIRCUITS—8 SM5842AP/APT Output timing SM5842AP: VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 80 °C, CL = 15 pF SM5842APT: VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 70 °C, CL = 15 pF Rating Parameter Symbol Condition Unit min typ max XTI to XTO delay tXTO XTI fall to XTO rise 3 – 15 ns XTI to CKO delay tCKO XTI fall to CKO fall 10 – 35 ns tsbH XTI fall to BCKO rise 20 – 65 tsbL XTI fall to BCKO fall 20 – 65 tsbH XTI fall to BCKO rise 20 – 65 tsbL XTI fall to BCKO fall 20 – 65 tbdH BCKO fall to output rise −5 – 10 tbdL BCKO fall to output fall −5 – 10 tcdH CKO fall to output rise 12 – 45 tcdL CKO fall to output fall 12 – 45 txdH XTO rise to output rise 15 – 50 txdL XTO rise to output fall 15 – 50 XTI to BCKO delay (CKSLN = HIGH) XTI to BCKO delay (CKSLN = LOW) BCKO to DOL, DOR, WCKO delay CKO to DOL, DOR, WCKO, DG delay XTO to DOL, DOR, WCKO, DG delay ns ns ns ns ns Tsys Tsys XTI (CKSLN = H) VDD / 2 Tsys XTI (CKSLN = L) VDD / 2 CXO (CKSLN = H) 1.5V tCKO CKO (CKSLN = L) 1.5V tsbH tsbL BCKO 1.5V tcdL tbdL 1.5V DOL DOR DG WCKO tcdH tbdH 1.5V NIPPON PRECISION CIRCUITS—9 SM5842AP/APT Filter Characteristics 8-times interpolation filter Parameter Rating Passband 0 to 0.4535fs Stopband 0.5465fs to 7.4535fs ≤ ±0.00002 dB Passband ripple ≥ 117 dB Stopband attenuation Group delay Fixed 8fs filter response with deemphasis OFF Attenuation(dB) 0 20 40 60 80 100 120 140 0.0 1.0 2.0 4.0 3.0 5.0 6.0 7.0 8.0 Frequency (×fs) 8fs filter passband response with deemphasis OFF Attenuation (dB) −0.00008 −0.00004 0.00000 0.00004 0.00008 0.000 0.125 0.250 0.375 0.500 Frequency (×fs) 8fs filter transition response with deemphasis OFF 0 Attenuation (dB) 20 40 60 80 100 120 140 0.440 0.465 0.490 0.515 0.540 0.565 0.590 0.615 0.640 Frequency (×Fs) NIPPON PRECISION CIRCUITS—10 SM5842AP/APT Deemphasis filter Sampling frequency (fs) Parameter Passband bandwidth (kHz) 32 kHz 44.1 kHz 48 kHz 0 to 14.5 0 to 20.0 0 to 21.7 ≤ ±0.001 dB Attenuation Deviation from ideal characteristic Phase, θ 0 to 1.5° Passband response with deemphasis ON (logarithmic frequency axis) 0 32kHz Phase 2 -20 44.1kHz 48kHz 4 -40 6 -60 8 Phase (degrees) Attenuation (dB) 0 32kHz 44.1kHz 48kHz 10 10 20 50 100 200 500 1k 2k 5k 10k 20k [Hz] Frequency (Hz) NIPPON PRECISION CIRCUITS—11 SM5842AP/APT FUNCTIONAL DESCRIPTION The basic arithmetic block is shown in figure 1, and the function of each block is described in the following sections. Input fs 2-times interpolator 1st FIR, 169-tap 2fs 2-times interpolator 2nd FIR, 29-tap 4fs Deemphasis IIR filter Deemphasis OFF Deemphasis ON 4fs Soft mute 4fs 2-times interpolator 3rd FIR, 17-tap 8fs Output Figure 1. Arithmetic block diagram 8-times Oversampling (Interpolation) The interpolation arithmetic block is comprised of 3 cascaded, 2-times FIR interpolation filters, as shown in figure 1. The input signal is sampled at rate fs, and then 8times oversampling data is output. Sampling noise in the 0.5465fs to 7.4535fs stopband is removed by the interpolation filter. Digital Deemphasis DEMPL/DEMPR is HIGH, DEMPL/DEMPR is LOW. and OFF when Table 1. Sampling frequency select FSEL1 FSEL2 Sampling frequency (fs) LOW LOW 44.1 kHz LOW HIGH 48 kHz HIGH LOW Invalid setting HIGH HIGH 32 kHz The digital deemphasis filter has the same construction as analog filters. It is implemented as an IIR filter to faithfully reproduce the gain and phase characteristics of standard analog deemphasis filters. The three sets of filter coefficients for the three fs = 32.0/44.1/48.0 kHz sampling frequencies are selected by FSEL1 and FSEL2 when the sampling frequency is specified, as shown in table 1. Independent deemphasis for the left and right channel is controlled independently by DEMPL and DEMPR, respectively. Digital deemphasis is ON when NIPPON PRECISION CIRCUITS—12 SM5842AP/APT Soft Muting Muting of the left and right channel is controlled independently by MUTEL and MUTER, respectively. Muting is ON when MUTEL/MUTER is HIGH, muting is OFF when MUTEL/MUTER is LOW. When MUTEL/MUTER goes HIGH, the attenuation changes smoothly from 0 to −∞ dB in 512/fs, or approximately 11.6 ms when fs = 44.1 kHz. When MUTEL/MUTER goes LOW, muting is released and the attenuation changes smoothly from −∞ to 0 dB, again taking approximately 11.6 ms. When RSTN goes LOW, the DOL and DOR outputs go LOW, immediately muting the output signal. Muting is released and timing is synchronized when RSTN goes HIGH. System Clock (XTI, XTO, CKO, CKSLN) Two system clock frequencies, 384fs and 256fs, can be used. An external clock source can be input on XTI, or a crystal oscillator can be constructed by connecting a crystal between XTI and XTO. The system clock is also buffered and then output on CKO. The system clock frequency selection and the internal clock frequency are shown in table 2. Table 2. System clock frequency select CKSLN Parameter HIGH LOW XTI input clock frequency (fXI = 1/tXI) 384fs 256fs CKO clock frequency 384fs 256fs Internal clock frequency (tSYS) 2 × tXI tXI To timing controller CKSLN XTI 1/2 Internal system clock (192fs or 256fs) XTO CKO Figure 2. Clock generator circuit NIPPON PRECISION CIRCUITS—13 SM5842AP/APT Audio Data Input (INF1N, INF2N, IW1N, IW2N, DI, DIL, DIR, BCKI, LRCI) The input data format and several input pin functions are selected by the state of INF1N and INF2N as shown in table 3. Table 3. Pin function select Pin function selection INF1N DI/INF2N Input format LOW LOW LOW HIGH HIGH LOW LR alternating, leading data HIGH HIGH LR simultaneous2, leading data DI/INF2N IW1N/DIL IW2N/DIR DI IW1N IW2N INF2N DIL DIR LR alternating1, trailing data 1. Alternating left-channel and right-channel data input on a single input DI. 2. Simultaneous left-channel and right-channel data input on two inputs, DIL and DIR, respectively. The input data word length is selected by the state of IW1N and IW2N when INF1N is LOW. 24-bit is selected when INF1N is HIGH. Table 4. Input word length INF1N IW2N/DIL IW1N/DIR Input word length LOW LOW 24 bits LOW HIGH 22 bits HIGH LOW 18 bits HIGH HIGH 16 bits × × 24 bits LOW HIGH resynchronized and all functions continue to operate normally. Sync mode (SYNCN = LOW) When SYNCN is LOW, the timing error value is ±1 × (system clock period), which is a much smaller timing error tolerance than in jitter-free mode. In this mode, the internal timing is guaranteed to follow the LRCI clock timing within this tolerance, making this mode useful for systems constructed from a multiple number of SM5842AP/APT devices. Note that resynchronization affects the internal operation and can generate a momentary click noise output. Jitter-free Function (SYNCN) The arithmetic circuit and output control timing is derived from the system clock, and is therefore independent of the input LRCI and BCKI clocks. Accordingly, any jitter in the data input clock (LRCI and BCKI) does not cause jitter in the output. Generally, the internal timing is synchronized to the LRCI input timing after a system reset release, when RSTN goes from LOW to HIGH, on the first LRCI clock start edge. If the input timing and LRCI start edge timing subsequently drift, the input timing is automatically resynchronized when the timing error exceeds a certain value. There are 2 timing error values at which resynchronization occurs, selected by the state of SYNCN. Jitter-free mode (SYNCN = HIGH) When SYNCN is HIGH, the timing error value is ±3/8 × (LRCI clock period). When the difference between the input timing and LRCI start edge position do not exceed this value, internal timing is not NIPPON PRECISION CIRCUITS—14 SM5842AP/APT Audio Data Output (DOL, DOR, BCKO, WCKO, OW20N) The output data is in serial, simultaneous left and right-channel, 2s complement, MSB first, BCKO burst (NPC format) format. The output data word length is selected by the state of OW1N and OW2N as shown in table 5. Table 5. Output word length select OW1N OW2N Output word length LOW LOW 24 bits LOW HIGH 22 bits HIGH LOW 20 bits HIGH HIGH 18 bits 8fs serial data is output in sync with the falling edge of the internal system clock and BCKO clock. The output timing is determined by CKSLN and the output word length. When CKSLN is LOW, the output timing is the same for different output word lengths. Only the number of BCKO bit clock pulses word changes depending on the output word length selected. When CKSLN is HIGH, however, the output timing for 24-bit output mode starts 1 bit earlier than for 18/20/22-bit output mode. Table 6. Output timing Parameter Bit clock rate Data word length Symbol CKSLN = HIGH CKSLN = LOW tB 1/192fs 1/256fs tDW 24tSYS 32tSYS NIPPON PRECISION CIRCUITS—15 SM5842AP/APT System Reset (RSTN) Under normal operating conditions, the SM5842AP/APT does not need to be reset. However, it can be reset when you want to synchronize the LRCI clock and internal operation timing in jitterfree mode. The system is reset by applying a LOW-level pulse on RSTN. The arithmetic and output timing counters are reset on the first LRCI start edge after reset is released, as long as the XTI clock has already stabilized. The LRCI start edge is determined by the state of INF1N and INF2N. When INF1N is LOW or when both INF1N and INF2N are HIGH, the start edge is the rising edge. When INF1N is HIGH and INF2N is LOW, the start edge is the falling edge. When RSTN is LOW, the DOL and DOR outputs are LOW, muting the output signal to an attenuation level of −∞. The power-ON reset pulse can be applied by a microcontroller or, for systems where XTI and LRCI are stable at power-ON, by connecting a capacitor of about 300 pF between RSTN and VSS. For systems that do not use a microcontroller, the capacitor must be chosen such that the XTI and LRCI clocks fully stabilize before RSTN goes from LOW to HIGH. RSTN 1 2 LRCI Internal reset WCKO DOL DOR Figure 3. System reset timing and output muting NIPPON PRECISION CIRCUITS—16 SM5842AP/APT TIMING DIAGRAMS Input Timing Examples (DIN, BCKI, LRCI) 1 / fs Lch DATA DI 1 Rch DATA (LSB) (MSB) 2 (MSB) 14 15 16 1 (LSB) 2 14 15 16 BCKI LRCI INF1N = LOW, IW1N = IW2N = HIGH Figure 4. LR alternating, trailing data, 16-bit input 1 / fs Lch DATA (MSB) DIL 1 2 (LSB) 23 24 3 1 Rch DATA (MSB) 1 DIR 2 (LSB) 23 24 3 BCKI LRCI INF1N HIGH, INF2N = LOW. Data following LSB is ignored. Requires minimum 24 BCKI clock pulses. Figure 5. LR alternating, leading data, 24-bit input 1 / fs (MSB) DIL 1 2 Lch DATA 3 (MSB) DIR 1 2 3 4 6 23 24 Rch DATA (LSB) 4 5 (LSB) 5 6 23 24 1 1 BCKI LRCI INF1N = INF2N = HIGH. Data following LSB is ignored. Requires minimum 24 BCKI clock pulses. Figure 6. LR simultaneous, leading data, 20-bit input NIPPON PRECISION CIRCUITS—17 SM5842AP/APT Output Timing Examples (DOL, DOR, BCKO, WCKO, DG) 24TB(TDW) System Clock DOL or DOR 1 2 3 4 16 17 18 19 20 21 22 (*) 1 2 BCKO TB TB WCKO 12TB 12TB DG 12TB 10TB 2TB The number of output bits is determined by the output bit length selected. Figure 7. 18/20/22-bit output (CKSLN = HIGH) 24TB(TDW) System Clock DOL or DOR 24 1 2 3 ............................. 4 21 22 23 24 1 2 3 ........................ BCKO TB WCKO 12TB 12TB DG 2TB 12TB 10TB The number of output bits is determined by the output bit length selected. Figure 8. 24-bit output (CKSLN = HIGH) 32TB(TDW) System Clock DOL or DOR 1 2 3 17 18 19 ...... 24 (*) 1 2 BCKO TB TB WCKO 16TB 16TB DG 14TB 16TB 2TB The number of output bits is determined by the output bit length selected. Figure 9. 24-bit output (CKSLN = LOW) NIPPON PRECISION CIRCUITS—18 SM5842AP/APT Data Input to Output Delay Timing This is the digital filter arithmetic computation time from the completion of data input at rate fs (tINPUT) on the rising edge of LRCI to the start of data output at rate 8fs (tOUTPUT) on the falling edge of WCKO. Table 7. Output delay CKSLN SYNCN Mode tOUTPUT − tINPUT LOW After reset + sync mode 48.625/fs HIGH Jitter-free mode 48.25/fs − 49.0/fs LOW After reset + sync mode 48.75/fs HIGH Jitter-free mode 48.375/fs − 49.125/fs LOW (256fs) HIGH (384fs) 1/fs LRCI Serial data Input tINPUT 48/fs WCKO (256fs) tOUTPUT WCKO (384fs) Serial data output tOUTPUT Serial data output Figure 10. Delay timing 1 tINPUT tOUTPUT − tINPUT tOUTPUT Figure 11. Delay timing 2 NIPPON PRECISION CIRCUITS—19 SM5842AP/APT APPLICATION CIRCUITS Input Interface Circuits CD decoder (CXD2500Q) connection (SONY) C16M LRCK DA16 CD DECODER CXD2500Q DA15 EMPH 16.9344MHz 44.1kHz 2.1168MHz PSSL CKSLN XTI LRCI DI SM5842 BCKI DEMPL MUTEL DEMPR MUTE MUTER FSEL1 FSEL2 IW1N IW2N INF1N X'tal(16.9344MHz) (SONY) XTAI LRCK DA16 CD DECODER CXD2500Q PSSL XTSL DA15 EMPH 16.9344MHz 44.1kHz 2.1168MHz CKSLN CKI LRCI DI BCKI XTO XTI SM5842 DEMPL DEMPR IW1N IW2N INF1N MUTE MUTEL MUTER FSEL1 FSEL2 Digital audio interface receiver (YM3623B) connection (YAMAHA) DIR YM3623B S1 S2 A L/R DO BCO DEF 384fs (16.9344MHz) fs (44.1kHz) XTI LRCI DI BCKI DEMPL DEMPR IW1N IW2N INF1N CKSLN SM5842 MUTEL MUTE MUTER FSEL1 FSEL2 NIPPON PRECISION CIRCUITS—20 SM5842AP/APT Output Interface Circuits 20-bit input Σ∆ DAC (SM5864AP) connection 1 384fs X'tal 384fs to SIGNAL PROCESSOR (CD DECODER) 384fs CKSLN CKO SM5842 (20bit OUT) XDIVN XTI BCKO WCKO DOL DOR 74HCU04 XTI 384fs CKO NPC LOA BCKI Σ∆DAC 8fs LOBN WCKI SM5864 DINL (ΣDECO) ROA DINR ROBN OW2N OW1N Analog LPF Lch OUT Analog LPF Rch OUT COMPN X3SL 512fs X'tal 512fs to SIGNAL PROCESSOR (CD DECODER) 256fs CKSLN CKO SM5842 (20bit OUT) 256fs XTI 1/2 BCKO 8fs WCKO DOL DOR XDIVN CKO NPC BCKI 74HCU04 XTI LOA Σ∆DAC LOBN WCKI SM5864 DINL (ΣDECO) ROA DINR ROBN OW2N OW1N Analog LPF Lch OUT Analog LPF Rch OUT COMPN X3SL NIPPON PRECISION CIRCUITS—21 SM5842AP/APT 20-bit input Σ∆ DAC (SM5864AP) connection 2 L/R-channel independent complementary PWM output to SIGNAL PROCESSOR (CD DECODER) 384fs CKSLN CKO SM5842 XDIVN XTI BCKO WCKO (20bit OUT) 384fs 8fs DOL DOR CKO BCKI DINR OW2N OW1N Σ∆DAC LOA LOBN WCKI SM5864 ROA DINL (ΣDECO) Analog LPF Lch OUT Analog LPF Rch OUT ROBN X3SL COMPN 74HCU04 XDIVN X'tal 384fs XTI BCKI LOA WCKI Σ∆DAC LOBN DINL SM5864 (ΣDECO) ROA DINR ROBN X3SL COMPN 20-bit input R − 2R DAC (PCM63P) connection L/R-channel independent (BURR − BROWN) PCM63P BCKO WCKO SM5842 DOL (20bit OUT) DOR 8fs CLOCK LE DATA BPO Iout Analog LPF Lch OUT Analog LPF Rch OUT OW2N OW1N (BURR − BROWN) PCM63P CLOCK L. E DATA BPO Iout NIPPON PRECISION CIRCUITS—22 SM5842AP/APT NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9714AE 1998.2 NIPPON PRECISION CIRCUITS—23