NPC SM5843A

SM5843A×1
Audio Multi-function Digital Filter
NIPPON PRECISION CIRCUITS INC.
OVERVIEW
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The SM5843A×1 is a multi-function digital filter IC,
fabricated using NPC’s Molybdenum-gate CMOS
process, for digital audio reproduction equipment. It
features 8-times oversampling (interpolation), digital
deemphasis and soft muting functions. It accepts 16,
18, or 20-bit input data, and outputs data in 18 or 20bit format. It operates using either a 384fs or 256fs
system clock.
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5 V supply
Crystal oscillator circuit built-in
TTL-compatible input/outputs
28-pin plastic DIP and SOP
Molybdenum-gate CMOS
APPLICATIONS
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CD players
DAT players
PCM systems
FEATURES
■
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Filter configuration (2-channel processing)
• 8-times oversampling (interpolation)
- 3-stage FIR configuration
• Deemphasis filter
- IIR filter configuration for correct gain and
phase characteristics
- 2-channel independent ON/OFF control
- 32/44.1/48 kHz sampling frequency (fs)
• 21 × 22-bit parallel multiplier/25-bit
accumulator for high precision
• Overflow limiter
2 oversampling filter characteristics
• Sharp roll-off characteristic (response 1)
- ≤ ±0.00005 dB passband ripple (0 to
0.4535fs)
- ≥ 110 dB stopband attenuation (0.5465fs to
7.4535fs)
• Slow roll-off characteristic (response 2)
- ≤ ±0.00003 dB passband ripple (0 to 0.235fs)
- ≥ 77 dB stopband attenuation (0.745fs to
7.255fs)
Soft muting
Digital attenuator
Input data format
• 2s complement, MSB first
- LR alternating, 16/18/20-bit serial, trailing
data
- LR alternating, 20-bit serial, leading data
- LR simultaneous, 20-bit serial, leading data
Output data format
• 2s complement, MSB first, LR simultaneous
• 18/20-bit serial
• BCKO burst (NPC format)
Dither processing ON/OFF control
Jitter-free/Sync mode selectable
256fs/384fs system clock selectable
• 21.2/14.2MHz
maximum
frequency
(384fs/256fs)
ORDERING INFOMATION
Device
Package
SM5843AP1
28pin DIP
SM5843AS1
28pin SOP
NIPPON PRECISION CIRCUITS—1
SM5843A×1
PACKAGE DIMENSIONS(Unit: mm)
28-pin DIP
28-pin DIP
BCKO
INF1N
4
25
WCKO
IW1N / DIL
5
24
DOL
XTI
6
23
DOR
XTO
7
22
VDD
VSS
8
21
TMOD1
CKO
9
20
SYNCN
IW2N / DIR
10
19
OW20N
MDT
11
18
FSEL2
MDK
12
17
FSEL1
MLEN
13
16
DEMP
RSTN
14
15
MUTE
+ 0.30
1.5 −0.05
2.54
0.45 0.1
TMOD2
CKSLN
3
26
BCKO
4
25
WCKO
5
24
DOL
XTI
6
23
DOR
XTO
7
22
VDD
VSS
8
21
TMOD1
CKO
9
20
SYNCN
IW2N / DIR
10
19
OW20N
MDT
11
18
FSEL2
MDK
12
17
FSEL1
MLEN
13
16
DEMP
RSTN
14
15
MUTE
SM5843AS1
INF1N
IW1N / DIL
18.3 TYP
3.0MAX
1.27 ± 0.15
0° to 10°
+ 0.10
0.15 − 0.05
+ 0.10
0.4 − 0.05
0.45TYP.
1.0 0.2
LRCI
27
11.8 0.3
28
2
0.10MIN.
1
BCKI
8.4TYP
DI / INF2N
0.6MAX.
28-pin SOP
3.0MAX.
28-pin SOP
37.3 0.3
+ 0.10
0.25 −0.05
26
15.2
3
13.8 0.2
TMOD2
CKSLN
4.5 0.3
LRCI
27
3.2 0.2
7.7 0.5
28
2
3.8 0.1
1
BCKI
SM5843AP1
DI / INF2N
0° to 15°
PINOUT(TOP VIEW)
0° to 10°
NIPPON PRECISION CIRCUITS—2
SM5843A×1
BLOCK DIAGRAM
CKSLN LRCI
BCKI
DI / INF2N
IW1N / DIL
IW2N / DIR
XTI
XTO
System
Clock
INF1N
Input data Interface
CKO
TOMD2
RSTN
Timing
Controller
Filter and Attenuation
Arithmetic block
SYNCN
TMOD1
DEMP
FSEL1
BCKO
Deemphasis
Controller
Output date
Interface
FSEL2
WCKO
DOL
MUTE
DOR
Mute/ Attenuation
Controller
OW20N
MDT MCK MLEN
VSS VDD
NIPPON PRECISION CIRCUITS—3
SM5843A×1
PIN DESCRIPTION
Number
Name
I/O1
1
DI/INF2N
Ip
Data input when INF1N is LOW, and input format select pin when INF1N is HIGH.
2
BCKI
Ip
Input bit clock
3
CKSLN
Ip
Oscillator and system clock select input. 384fs when HIGH, and 256fs when LOW.
Description
Input format select pin. INF1N and INF2N select the pin functions below.
Pin function selection
INF1N
4
INF1N
Ip
DI/INF2N
Input format
LOW
LOW
LOW
HIGH
HIGH
LOW
LR alternating, leading data
HIGH
HIGH
LR simultaneous, leading data
DI/INF2N
IW1N/DIL
IW2N/DIR
DI
IW1N
IW2N
INF2N
DIL
DIR
LR alternating, trailing data
Input bit length select pin when INF1N is LOW, and left-channel data input when INF1N is HIGH.
IW1N and IW2N select the input data length.
INF1N
5
IW1N/DIL
Ip
IW2N/DIL
IW1N/DIR
Input bit length
LOW
LOW
20 bits
LOW
HIGH
20 bits
HIGH
LOW
18 bits
HIGH
HIGH
16 bits
×
×
20 bits
LOW
HIGH
6
XTI
I
Oscillator input connection
7
XTO
O
Oscillator output connection
8
VSS
–
Ground
9
CKO
O
Oscillator output clock. Same frequency as XTI.
10
IW2N/DIR
Ip
Input bit length select pin when INF2N is LOW, and right-channel data input when INF2N is HIGH.
IW1N and IW2N select the input data length as shown in the table for pin 5.
11
MDT
Ip
Attenuator serial data input
12
MCK
Ip
Attenuator bit clock input
13
MLEN
Ip
Attenuator latch enable input
14
RSTN
Ip
System reset. Reset operation when LOW, and normal operation when HIGH.
15
MUTE
Ip
Mute control signal. Muting when HIGH, and normal operation when LOW.
16
DEMP
Ip
Deemphasis control signal. OFF when LOW, and ON when HIGH.
Deemphasis filter select inputs
17
18
FSEL1
FSEL2
Ip
Ip
FSEL1
FSEL2
Sampling frequency (fs)
LOW
LOW
44.1 kHz
LOW
HIGH
48 kHz
HIGH
LOW
Test mode
HIGH
HIGH
32 kHz
19
OW20N
Ip
Output bit length select pin. 20-bit output when LOW, and 18-bit output when HIGH.
20
SYNCN
Ip
Sync mode select pin. Normal sync mode when LOW, and jitter-free mode when HIGH.
21
TMOD1
Ip
Dither processing control. ON when LOW, and OFF when HIGH.
22
VDD
–
5 V supply
NIPPON PRECISION CIRCUITS—4
SM5843A×1
Number
Name
I/O1
23
DOR
O
Right-channel data output
24
DOL
O
Left-channel data output
25
WCKO
O
Output word clock
26
BCKO
O
Output bit clock
27
TMOD2
Ip
Filter characteristic select pin. Sharp roll-off (response 1) when HIGH, and slow roll-off (response 2)
when LOW.
28
LRCI
Ip
Input data sample rate (fs) clock
Description
1. I = input, Ip = Input with pull-up resistor, O = output
NIPPON PRECISION CIRCUITS—5
SM5843A×1
SPECIFICATIONS
Absolute Maximum Ratings
VSS = 0 V
Parameter
Symbol
Rating
Unit
Supply voltage range
VDD
−0.3 to 7.0
V
Input voltage range
VIN
−0.3 to VDD + 0.3
V
Storage temperature range
Tstg
−40 to 125
°C
Power dissipation
PD
550 (DIP)
mW
390 (SOP)
Soldering temperature
Tsld
255
°C
Soldering time
tsld
10
s
Symbol
Rating
Unit
Supply voltage range
VDD
4.5 to 5.5
V
Operating temperature range
Topr
−20 to 80
°C
Symbol
Rating
Unit
Supply voltage range
VDD
4.75 to 5.25
V
Operating temperature range
Topr
−20 to 70
°C
Recommended Operating Conditions
fs = 384fs (CKSLN = HIGH): VSS = 0 V
Parameter
fs = 256fs (CKSLN = LOW): VSS = 0 V
Parameter
DC Electrical Characteristics
VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C
Rating
Parameter
Symbol
Condition
VDD = 5.0 V1
Unit
min
typ
max
–
50
65
mA
Current consumption
IDD
XTI HIGH-level input voltage
VIH1
0.7VDD
–
–
V
XTI LOW-level input voltage
VIL1
–
–
0.3VDD
V
XTI AC-coupled input voltage
VINAC
0.3VDD
–
–
Vp-p
HIGH-level input voltage2
VIH2
2.4
–
–
V
LOW-level input voltage2
VIL2
–
–
0.5
V
HIGH-level output voltage3
VOH
IOH = −0.4 mA
2.5
–
–
V
LOW-level output voltage3
VOL
IOL = 1.6 mA
–
–
0.4
V
XTI HIGH-level input current
IIH
VIN = VDD
–
10
20
µA
XTI LOW-level input current
IIL1
VIN = 0 V
–
10
20
µA
LOW-level input current2
IIL2
VIN = 0 V
–
10
20
µA
Input leakage current2
ILH
VIN = VDD
–
–
1.0
µA
1. fSYS = 256fs = 14.2 MHz (CKSLN = LOW), no output load
2. Pins DI/INF2N, BCKI, CKSLN, INF1N, IW1N/DIL, IW2N/DIR, MDT, MCK, MLEN, RSTN, MUTE, DEMP, FSEL1, FSEL2, OW20N, SYNCN, LRCI,
TMOD1, TMOD2
3. Pins CKO, DOL, DOR, BCKO, WCKO
NIPPON PRECISION CIRCUITS—6
SM5843A×1
AC Electrical Characteristics
Input Clock (XTI)
Crystal oscillator
fs = 384fs (CKSLN = HIGH): VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C
Rating
Parameter
Symbol
Oscillator frequency
Unit
fOSC
min
typ
max
2.0
–
21.2
MHz
fs = 256fs (CKSLN = LOW): VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 70 °C
Rating
Parameter
Symbol
Oscillator frequency
Unit
fOSC
min
typ
max
1.0
–
14.2
MHz
External clock input
fs = 384fs (CKSLN = HIGH): VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C
Rating
Parameter
Symbol
Unit
min
typ
max
Clock HIGH-level pulsewidth
tCWH
20
–
250
ns
Clock LOW-level pulsewidth
tCWL
20
–
250
ns
tXI
47
–
500
ns
Clock pulse cycle time
fs = 256fs (CKSLN = LOW): VDD = 4.75 to 5.25 V, VSS = 0 V, Ta = −20 to 70 °C
Rating
Parameter
Symbol
Unit
min
typ
max
Clock HIGH-level pulsewidth
tCWH
30
–
500
ns
Clock LOW-level pulsewidth
tCWL
30
–
500
ns
tXI
70
–
1000
ns
Clock pulse cycle time
VlH1
0.5VDD
XTI
tCWL
tCWH
VlL1
tXI
NIPPON PRECISION CIRCUITS—7
SM5843A×1
Serial input timing (BCKI, DI, DIL, DIR, LRCI)
VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C
Rating
Parameter
Symbol
Unit
min
typ
max
BCKI HIGH-level pulsewidth
tBCWH
50
–
–
ns
BCKI LOW-level pulsewidth
tBCWL
50
–
–
ns
BCKI pulse cycle
tBCY
100
–
–
ns
DIN setup time
tDS
50
–
–
ns
DIN hold time
tDH
50
–
–
ns
Last BCKI rising edge to LRCI edge
tBL
50
–
–
ns
LRCI edge to first BCKI rising edge
tLB
50
–
–
ns
tBCY
tBCWH
tBCWL
1.5V
BCKI
tDS
tDH
DI
DIL
DIR
1.5V
tLB
tBL
1.5V
LRCI
Reset timing (RSTN)
VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C
Rating
Parameter
RST LOW-level reset pulsewidth
Symbol
tRST
Condition
Unit
min
typ
max
At power-ON
1
–
–
µs
At all other times
50
–
–
ns
NIPPON PRECISION CIRCUITS—8
SM5843A×1
Attenuator timing (MDT, MCK, MLEN)
VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C
Rating
Parameter
Symbol
Unit
min
typ
max
MDT setup time
tMDS
20
–
–
ns
MDT hold time
tMDH
20
–
–
ns
MLEN setup time
tMCS
40
–
–
ns
MLEN hold time
tMCH
20
–
–
ns
MLEN LOW-level pulsewidth
tMEWL
20
–
–
ns
MLEN HIGH-level pulsewidth
tMEWH
20
–
–
ns
MLEN pulse cycle time
tMLEY
6
–
–
tSYS1
1. tSYS = 1/384fs when CKSLN is HIGH, and 1/256fs when CKSLN is LOW.
MDT
1.5V
tMDS
tMDH
1.5V
MCK
tMCS
tMCH
MLEN
1.5V
tMEWL
tMEWH
tMLEY
NIPPON PRECISION CIRCUITS—9
SM5843A×1
Output timing
VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C, CL = 15 pF
Rating
Parameter
Symbol
Condition
Unit
min
typ
max
XTI to XTO delay
tXTO
XTI fall to XTO rise
3
–
15
ns
XTI to CKO delay
tCKO
XTI fall to CKO fall
10
–
35
ns
tsbH
XTI fall to BCKO rise
20
–
60
tsbL
XTI fall to BCKO fall
20
–
60
tsbH
XTI fall to BCKO rise
20
–
60
tsbL
XTI fall to BCKO fall
20
–
60
tbdH
BCKO fall to output rise
−5
–
10
tbdL
BCKO fall to output fall
−5
–
10
tcdH
CKO fall to output rise
5
–
25
tcdL
CKO fall to output fall
5
–
25
txdH
XTO rise to output rise
15
–
50
txdL
XTO rise to output fall
15
–
50
XTI to BCKO delay (CKSLN = HIGH)
XTI to BCKO delay (CKSLN = LOW)
BCKO to DOL, DOR, WCKO delay
CKO TODOL, DOR, WCKO delay
XTO TODOL, DOR, WCKO delay
ns
ns
ns
ns
Tsys
ns
Tsys
0.5VDD
XTI
(CKSLN = H)
tCKO
CKO
(CKSLN = H)
1.5V
Tsys
0.5VDD
XTI
(CKSLN = L)
tCKO
CKO
(CKSLN = L)
1.5V
tsbH
tsbL
BCKO
1.5V
tbdL
tcdL
XTO rising edge
DOL
DOR
WCKO
txdL
1.5V
tbdH
tcdH
1.5V
XTO rising edge
txdH
NIPPON PRECISION CIRCUITS—10
SM5843A×1
Filter Characteristics
8-times interpolation filter (sharp roll-off: response 1)
Parameter
Condition
Rating @ 256fs
Passband
0 to 0.4535fs
Stopband
0.5465fs to 7.4535fs
≤ ±0.00005 dB
Passband ripple
≥ 110 dB
Stopband attenuation
Group delay1
SYNCN = LOW
44.625/fs
SYNCN = HIGH
44.25/fs to 45.0/fs
1. The digital filter arithmetic computation time from when the completion of data input at rate fs to the start of data output at rate 8fs.
8fs filter response with deemphasis OFF
0
Attenuation (dB)
20
40
60
80
100
120
140
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Frequency (×fs)
8fs filter band transition response with deemphasis OFF
0
Attenuation (dB)
20
40
60
80
100
120
140
0.440
0.465
0.490
0.515
0.540
0.565
0.590
0.615
0.640
Frequency (×fs)
8fs filter passband response with deemphasis OFF
Attenuation (dB)
-0.0001
-0.00005
0.00000
0.00005
0.0001
0.000
0.125
0.250
0.375
0.500
Frequency (×fs)
NIPPON PRECISION CIRCUITS—11
SM5843A×1
8-times interpolation filter (slow roll-off: response 2)
Parameter
Condition
Rating @ 256fs
Passband
< 3 dB attenuation
0 to 0.455fs
Stopband
> 77 dB attenuation
0.745fs to 7.255fs
0 to 0.235fs
≤ ±0.00003 dB
Passband ripple
≥ 77 dB
Stopband attenuation
Group delay1
SYNCN = LOW
25.625/fs
SYNCN = HIGH
25.25/fs to 26.0/fs
1. The digital filter arithmetic computation time from when the completion of data input at rate fs to the start of data output at rate 8fs.
8fs filter response with deemphasis OFF
0
Attenuation (dB)
20
40
60
80
100
120
140
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Frequency (×fs)
8fs filter band transition response with deemphasis OFF
0
Attenuation (dB)
20
40
60
80
100
120
140
0.00
0.125
0.25
0.375
0.50
0.625
0.75
0.825
1.00
Frequency (×fs)
8fs filter passband response with deemphasis OFF
Attenuation (dB)
-2.0
0.0
2.0
4.0
6.0
0.000
0.125
0.250
0.375
0.500
Frequency (×fs)
NIPPON PRECISION CIRCUITS—12
SM5843A×1
8fs filter passband response [amplitude gain enlarged]
Attenuation (dB)
-0.0001
-0.00005
0.00000
0.00005
0.0001
0.000
0.125
0.250
0.375
0.500
Frequency (×fs)
Deemphasis filter
Sampling frequency (fs)
Parameter
Passband bandwidth (kHz)
32 kHz
44.1 kHz
48 kHz
0 to 14.5
0 to 20.0
0 to 21.7
≤ ±0.001 dB
Attenuation
Deviation from ideal characteristic
Phase, θ
0 to 1.5°
Passband response with deemphasis ON (logarithmic frequency axis)
32kHz
2
Attenuation (dB)
0
Phase
4
-20
-40
44.1kHz
48kHz
6
-60
Attenuation
32k A44.1k A48kHz
8
Phase θ ( ° )
0
10
10
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Passband response with deemphasis ON (linear frequency axis)
32kHz
2
Attenuation (dB)
0
Phase
-20
44.1kHz
48kHz
4
6
-40
-60
Attenuation
32k A44.1k A48kHz
8
Phase θ ( ° )
0
10
0
4k
8k
12k
16k
20k
22k
24k
Frequency (Hz)
NIPPON PRECISION CIRCUITS—13
SM5843A×1
FUNCTIONAL DESCRIPTION
The basic arithmetic block is shown in figure 1, and
the function of each block is described in the following sections.
Input
fs
2 - times oversampling
153 - tap (response 1 )or
25 - tap (response 2 )
FIR
2fs
2 - times oversampling
29 - tap FIR
4fs
Deemphasis IIR
filter
Deemphasis OFF
Deemphasis ON
4fs
Mute function
4fs
2 - times oversampling
17 - tap FIR
8fs
Output
Figure 1. Arithmetic block diagram
8-times Oversampling (Interpolation)
Digital Deemphasis
The interpolation arithmetic block is comprised of 3
cascaded, 2-times FIR interpolation filters, as shown
in figure 1.
The digital deemphasis filter has the same construction as analog filters. It is implemented as an IIR filter to faithfully reproduce the gain and phase
characteristics of standard analog deemphasis filters.
The three sets of filter coefficients for the three fs =
32.0/44.1/48.0 kHz sampling frequencies are
selected by FSEL1 and FSEL2 when the sampling
frequency is specified, as shown in the following
table. Deemphasis is ON when DEMP is HIGH, and
OFF when DEMP is LOW.
The input signal is sampled at rate fs, and then 8times oversampling data is output. Sampling noise in
the 0.5465fs to 7.4535fs stopband for the sharp rolloff (response 1) characteristic, 0.745fs to 7.255fs for
the slow roll-off (response 2) characteristic, is
removed by the interpolation filter.
FSEL1
FSEL2
Sampling frequency (fs)
LOW
LOW
44.1 kHz
LOW
HIGH
48 kHz
HIGH
LOW
Test mode
HIGH
HIGH
32 kHz
Note that test mode is not available for operation.
NIPPON PRECISION CIRCUITS—14
SM5843A×1
Soft Muting
The muting function controls the muting of both left
and right channels simultaneously. Muting is ON
when MUTE is HIGH, muting is OFF when MUTE
is LOW.
MUTE
L
When MUTE goes HIGH, the attenuation changes
smoothly from 0 to −∞ dB in 512/fs, or approximately 11.6 ms when fs = 44.1 kHz. When MUTE
goes LOW, muting is released and the attenuation
changes smoothly from −∞ to 0 dB, again taking
approximately 11.6 ms.
H
L
0dB
(Gain)
−∞
512 / fs
512 / fs
Figure 2. Mute timing
When RSTN goes LOW, the DOL and DOR outputs
go LOW, immediately muting the output signal.
Muting is released and timing is synchronized immediately after RSTN goes HIGH.
Digital Attenuator (MDT, MCK, MLEN)
The attenuation function is controlled by MDT,
MCK and MLEN. MDT data, in 11-bit serial MSB
first format, is shifted into an internal shift register
on the rising edge of the serial data clock MCK. The
MDT
contents of the shift register are transferred to the
internal processing circuits on the rising edge of the
MLEN gate pulse. The attenuation data format is
shown in figure 3.
B1
B2
B3
B4
B5
B6
B7
B8
B9 B10 B11
a0
a1
a2
a3
a4
a5
a6
a7
a8
a9
MSB
a10
LSB
MCK
MLEN
Figure 3. Attenuation data format
The attenuation register data DATT can take on any
value between 0 and 1024 (400H). The attenuation is
given by the following equation for both left and
right channels simultaneously.
Attenuation = 20 × log10(DATT/1024) [dB]
Thus, the attenuation level is −∞ when DATT is 0,
and attenuation is 0 dB when DATT is 1024. DATT
is set to 1024 (400H) after system reset initialization.
The attenuation data and attenuation level for sample
DATT values are shown in the following table.
Attenuation data DATT
Attenuation level (dB)
000H
−∞
001H
to
3FFH
−60.206
to
−0.0085
400H
0
NIPPON PRECISION CIRCUITS—15
SM5843A×1
Attenuation operation
When an attenuation value DATT is set, the attenuation changes smoothly from the current attenuation
level to the new level. The new attenuation data is
stored in the attenuation register while the current
attenuation data is stored in a temporary register. The
attenuation then changes smoothly by ramping
between the two register values, updating the temporary register with each step. If a new attenuation
Setting1
DATT1
−∞
When MUTE is HIGH, the attenuation level is −∞.
When MUTE goes LOW (muting OFF), the attenuation level returns to that of the original value of
DATT.
Setting4
DATT4
DATT2
DATT2
Setting2
(Gain)
value for DATT is set before the previous target
attenuation level is reached, the attenuation then
ramps toward the new attenuation level.
DATT3
Setting3
MUTE
L
H
L
Time
Figure 4. Attenuation and mute timing
System Clock (XTI, XTO, CKO, CKSLN)
Two system clock frequencies, 384fs and 256fs, can
be used. An external clock source can be input on
XTI, or a crystal oscillator can be constructed by
connecting a crystal between XTI and XTO. The
system clock is also buffered and then output on
CKO. The system clock frequency selection and the
internal clock frequency are shown in the following
table.
CKSL
Parameter
HIGH
LOW
XTI input clock frequency (fXI = 1/tXI)
384fs
256fs
CKO clock frequency
384fs
256fs
Internal clock frequency (tSYS)
2 × tXI
tXI
to timing controller
CKSLN
XTI
1/2
Internal system clock
(192fs or 256fs)
XTO
CKO
Figure 5. Clock generator circuit
NIPPON PRECISION CIRCUITS—16
SM5843A×1
Audio Data Input (INF1N, INF2N, IW1N,
IW2N, DI, DIL, DIR, BCKI, LRCI)
The input data format and several input pin functions
are selected by the state of INF1N and INF2N.
Pin function selection
INF1N
DI/INF2N
Input format
LOW
LOW
LOW
HIGH
HIGH
LOW
LR alternating, leading data
HIGH
HIGH
LR simultaneous2, leading data
DI/INF2N
IW1N/DIL
IW2N/DIR
DI
IW1N
IW2N
INF2N
DIL
DIR
LR alternating1, trailing data
1. Alternating left-channel and right-channel data input on a single input DI.
2. Simultaneous left-channel and right-channel data input on two inputs, DIL and DIR, respectively.
The input data word length is selected by the state of
IW1N and IW2N when INF1N is LOW. 20-bit is
selected when INF1N is HIGH.
INF1N
IW2N/DIL
IW1N/DIR
Input bit length
LOW
LOW
20 bits
LOW
HIGH
20 bits
HIGH
LOW
18 bits
HIGH
HIGH
16 bits
×
×
20 bits
LOW
HIGH
Jitter-free Function (SYNCN)
The arithmetic circuit and output control timing is
derived from the system clock, and is therefore independent of the input LRCI and BCKI clocks.
Accordingly, any jitter in the data input clock (LRCI
and BCKI) does not cause jitter in the output.
Generally, the internal timing is synchronized to the
LRCI input timing after a system reset release, when
RSTN goes from LOW to HIGH, on the first LRCI
clock start edge. If the input timing and LRCI start
edge timing subsequently drift, the input timing is
automatically resynchronized when the timing error
exceeds a certain value. There are 2 timing error values at which resynchronization occurs, selected by
the state of SYNCN.
Jitter-free mode (SYNCN = HIGH)
When SYNCN is HIGH, the timing error value is
±3/8 × (LRCI clock period). When the difference
between the input timing and LRCI start edge position do not exceed this value, internal timing is not
resynchronized and all functions continue to operate
normally.
Sync mode (SYNCN = LOW)
When SYNCN is LOW, the timing error value is ±1
× (system clock period), which is a much smaller
timing error tolerance than in jitter-free mode. In this
mode, the internal timing is guaranteed to follow the
LRCI clock timing within this tolerance, making this
mode useful for systems constructed from a multiple
number of SM5843A×1 devices.
Note that resynchronization affects the internal operation and can generate a momentary click noise output.
Audio Data Output (DOL, DOR, BCKO, WCKO, OW20N)
The output data is in serial, simultaneous left and
right-channel, 2s complement, MSB first, BCKO
burst (NPC format) format. The output data word
length is selected by the state of OW20N. 18-bit output is selected when OW20N is HIGH, and 20-bit
output when OW20N is LOW.
independent of the number of output bits as specified
in the following table.
Parameter
Bit clock rate
Data word length
8fs serial data is output in sync with the falling edge
of the internal system clock and BCKO clock. The
number of BCKO bit clock pulses per word changes
depending on the output bit length selected (18/20
bits). Consequently, output data is latched into the
internal output register on the falling of the edge of
an output word clock WCKO, which has timing
Symbol
CKSLN = HIGH
CKSLN = LOW
TB
1/192fs
1/256fs
TDW
24tSYS
32tSYS
NIPPON PRECISION CIRCUITS—17
SM5843A×1
System Reset (RSTN)
The SM5843A×1 must be reset under the following
conditions.
■
■
■
■
■
and INF2N. When INF1N is LOW or when both
INF1N and INF2N are HIGH, the start edge is the
rising edge. When INF1N is HIGH and INF2N is
LOW, the start edge is the falling edge.
At power-ON.
When the LRCI clock and internal operation timing need to be resynchronized.
When switching the CKSLN clock select input.
When switching between filter characteristics
using TMOD2.
When either or both of the LRCI and XTI clocks
stop or are interrupted.
When RSTN is LOW, the DOL and DOR outputs are
LOW, muting the output signal to an attenuation
level of −∞.
The power-ON reset pulse can be applied by a
microcontroller or, for systems where XTI and LRCI
are stable at power-ON, by connecting a capacitor of
several hundred pF between RSTN and VSS. For
systems that do not use a microcontroller, the capacitor must be chosen such that the XTI and LRCI
clocks fully stabilize before RSTN goes from LOW
to HIGH.
The system is reset by applying a LOW-level pulse
on RSTN.
The arithmetic and output timing counters are reset
on the first LRCI start edge after reset is released, as
long as the XTI clock has already stabilized. The
LRCI start edge is determined by the state of INF1N
RSTN
1
2
LRCI
Internal reset
WCKO
DOL
DOR
Figure 6. System reset timing and output muting
Filter Characteristic Selection (TMOD2)
There are 2 digital filter frequency response characteristics incorporated into the SM5843A×1, selected
by the state of TMOD2. A sharp roll-off characteristic (response 1) is selected when TMOD2 is HIGH,
and a slow roll-off characteristic (response 2) when
TMOD2 is LOW. The response is modified by
changing the number of taps in the 1st FIR filter
stage, as shown in figure 1.
■
■
Dither Rounding-off Processing
(TMOD1)
Dither rounding-off processing of output data is ON
when TMOD1 is LOW. Dither is OFF and normal
processing mode is selected when TMOD1 is HIGH.
Filter response 1
• 153-tap 1st FIR
• 29-tap 2nd FIR
• 17-tap 3rd FIR
Filter response 2
• 25-tap 1st FIR
• 29-tap 2nd FIR
• 17-tap 3rd FIR
Note that the device should be reset when changing
TMOD2 during normal operation.
NIPPON PRECISION CIRCUITS—18
SM5843A×1
TIMING DIAGRAMS
Input Timing Examples (DIN, BCKI, LRCI)
1 / fs
Lch DATA
DI
1
Rch DATA
(LSB)
(MSB)
2
(MSB)
14 15 16
1
(LSB)
2
14 15 16
BCKI
LRCI
Figure 7. LR alternating, trailing data, 16-bit input
1 / fs
Lch DATA
(MSB)
1
DIL
2
(LSB)
19 20
3
1
Rch DATA
(MSB)
1
DIR
2
(LSB)
19 20
3
BCKI
LRCI
Data after lsb (bit 20) is ignored. After bit 20, BCKI clock input is not needed.
Figure 8. LR alternating, leading data, 20-bit input
1 / fs
(MSB)
DIL
1
2
Lch DATA
3
4
3
4
(MSB)
DIR
1
2
5
6
(LSB)
18
19 20
Rch DATA
5
6
1
(LSB)
18 19 20
1
BCKI
LRCI
Data after lsb (bit20) is ignored. After bit 20, BCKI clock input is not needed.
Figure 9. LR simultaneous, leading data, 20-bit input
NIPPON PRECISION CIRCUITS—19
SM5843A×1
Output Timing Examples (DOL, DOR, BCKO, WCKO)
24TB(TDW)
System
Clock
DOL
1
2
3
4
17
18 19 20 (*)
1
2
3
4
DOR
1
2
3
4
17
18 19 20 (*)
1
2
3
4
BCKO
TB TB
WCKO
12TB
12TB
The number of output bits is determined by the output bit length selected.
Figure 10. 18/20-bit output (CKSL = HIGH)
32TB(TDW)
System
Clock
DOL
1
2
3
15
16 17
18 19 20 (*)
1
2
DOR
1
2
3
15
16 17
18 19 20 (*)
1
2
BCKO
WCKO
TB TB
16TB
16TB
The number of output bits is determined by the output bit length selected.
Figure 11. 18/20-bit output (CKSL = LOW)
NIPPON PRECISION CIRCUITS—20
SM5843A×1
Data Input to Output Delay Timing
This is the digital filter arithmetic computation time
from the completion of data input at rate fs (tINPUT)
Filter response
CKSLN
on the rising edge of LRCI to the start of data output
at rate 8fs (tOUTPUT) on the falling edge of WCKO.
SYNCN
Mode
tOUTPUT − tINPUT
LOW
After reset + sync mode
44.625/fs
HIGH
Jitter-free mode
44.25/fs − 45.0/fs
LOW
After reset + sync mode
44.75/fs
HIGH
Jitter-free mode
44.375/fs − 45.125/fs
LOW
After reset + sync mode
25.625/fs
HIGH
Jitter-free mode
25.25/fs − 26.0/fs
LOW
After reset + sync mode
25.75/fs
HIGH
Jitter-free mode
25.375/fs − 26.125/fs
LOW (256fs)
Filter response 1
HIGH (384fs)
LOW (256fs)
Filter response 2
HIGH (384fs)
1/fs
LRCI
Serial data Input
tINPUT
44/fs(Filter Response 1)
25/fs(Filter Response 2)
WCKO
(256fs)
tOUTPUT
WCKO
(384fs)
Serial data output
tOUTPUT
Serial data output
Figure 12. Delay timing (SYNCN = LOW)
44.625/fs (Filter Response 1)
tINPUT
25.625/fs (Filter Response 2)
tINPUT
tOUTPUT
tOUTPUT
Figure 13. Delay timing (SYNCN = CKSLN = LOW)
NIPPON PRECISION CIRCUITS—21
SM5843A×1
APPLICATION CIRCUITS
Input Interface Circuits
CD decoder (CXD2500Q) connection
C16M
LRCK
SONY
DA16
CD DECODER
DA15
CXD2500Q
16.9344MHz
44.1kHz
EMPH
PSSL
LRCI
DI
2.1168MHz
CKSLN
XTI
SM5843
BCKI
DEMP
MUTE
IW1N
IW2N
FSEL1
FSEL2
MUTE
INF1N
Digital audio interface receiver (YM3623B) connection
384fs
øA
L/R
YAMAHA
DO
DIR
YM3623B
S1
S2
(16.9344MHz)
fs(44.1kHz)
CKSLN
XTI
LRCI
DI
SM5843
BCO
BCKI
DEF
DEMP
MUTE
IW1N
IW2N
FSEL1
FSEL2
MUTE
INF1N
NIPPON PRECISION CIRCUITS—22
SM5843A×1
Output Interface Circuits
20-bit input Σ∆ DAC (SM5864AP) connection 1
74HCU04
X'tal
384fs
to SIGNAL
PROCESSOR
CKSLN
(CD DECODER)
384fs
CKO
XTI
XDIVN
XTI
BCKO
WCKO
DOL
SM5843 DOR
(20bitOUT)
384fs CKO
BCKI
8fs
WCKI
LOA
NPC LOBN
Σ∆DAC
DINL
SM5864 ROA
DINR
(ΣDECO)
ROBN
Analog
LPF
LchOUT
Analog
LPF
RchOUT
COMPN
X3SL
OW20N
20-bit input Σ∆ DAC (SM5864AP) connection 2
L/R-channel independent complementary PWM output
to SIGNAL
PROCESSOR
(CD DECODER)
384fs
CKSLN
CKO
XDIVN
XTI
BCKO
WCKO
SM5843 DOL
(20bitOUT)
DOR
384fs CKO
BCKI
8fs
WCKI
DINL
LOA
NPC LOBN
Σ∆DAC
SM5864 ROA
DINR
(ΣDECO)
Analog
LPF
LchOUT
Analog
LPF
RchOUT
ROBN
OW20N
74HCU04
X'tal
384fs
X3SL
COMPN
XDIVN
BCKI
WCKI
DINL
XTI
XTI
LOA
NPC LOBN
DINR Σ∆DAC
SM5864 ROA
(ΣDECO)
ROBN
X3SL
COMPN
NIPPON PRECISION CIRCUITS—23
SM5843A1
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome
Koto-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NC9626AE
1997.03
NIPPON PRECISION CIRCUITS—24