NTE2057 Integrated Circuit Dual 16–Bit Digital–to–Analog Converter for CD and DAT Players Description: The NTE2057 is a monolithic integrated dual 16–bit digital –to–analog converter (DAC) in a 28–Lead DIP type package designed for use in Hi–Fi digital audio equipment such as compact disc players, digital tape, or cassette recorders. Features: D Selectable Input Format: Offset Binary or Two’s Complement D Internal Timing and Control Circuit D TTL–Compatible Digital Inputs D High Maximum Input Bit Rate and Fast Settling Time D 6Mbits/s Data Rate D Low Linearity Error (1/2 LSB typ) D Fast Settling (1µs typ) Applications: D Compact Disc Players D Digital Audio Tape, and Cassette Recorders and Players D Waveform Generation Absolute Maximum Ratings: Supply Voltage Range, VDD Pin28 (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V Pin26 (VDD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7V Pin15 (VDD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –17V Junction Temperature Range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +150°C Operating Ambient Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20° to +70°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C Electrostatic Handling (Note 1), VES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1000 to +1000V Note 1. Discharging a 250pF capacitor through a 1kΩ series resistor. DC and AC Electrical Characteristics: (VDD = +5V, VDD1 = –5V, VDD2 = –15V, TA = +25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit VDD 4.0 5.0 6.0 V Pin26 –VDD1 4.5 5.0 6.0 V Pin15 –VDD2 14.0 15.0 16.0 V IDD – 45 60 mA Pin26 –IDD1 – 45 75 mA Pin15 –IDD2 – 25 60 mA – 16 – bits Supply Supply Voltage Range Pin28 Supply Currents Pin28 Resolution Inputs Input Current (Pin3, Pin4) Digital Inputs Low IIL < 0.8V – – TBD mA Digital Inputs High IIH > 2.0V – – TBD µA Input Frequency At Clock Input (Pin4) fSCK – – 6 MHz At Clock Input (Pin2) fBCK – – – MHz At Data Inputs (Pin3, Pin4) fDAT – – – MHz At Word Select Input (Pin1) fWS – – – kHz Input Capacitance of Digital Inputs CI – 12 – pF fOSC 150 200 250 kHz Output Voltage Compliance VCC TBD – TBD mV Full–Scale Current IFS 3.4 4.0 4.6 mA Oscillator Oscillator Frequency w/Internal Capacitor Analog Outputs (AOL, AOR) Zero–Scale Current ±IZS Full–Scale Temperature Coefficient TCFS Linearity Error Integral Linearity Error Differential E1 ED1 – TBD – nA TA = –20° to +70°C – ±200 – ppm/°C TA = +25°C – 0.5 – LSB TA = –20° to +70°C – TBD – LSB TA = +25°C – 0.5 1.0 LSB TA = –20° to +70°C – TBD – LSB Note 2 90 95 – dB Signal–to–Noise Ratio + THD S/N Setting Time to ±1 LSB tCS – 1 – µs Channel Separation T 80 TBD – dB Unbalance Between Outputs ∆IFS – 0.1 0.2 dB Time Delay Between Outputs tD – – 1 µs Power Supply Ripple Rejection (Note 3) RR VDD = +5V – TBD – dB VDD1 = –5V – TBD – dB VDD2 = –15V – TBD – dB Note 2. Signal–to–noise ratio + THD with 1kHz full–scale sine wave generated at a sampling rate of 176.4kHz. Note 3. VRIPPLE = 1% of supply voltage and fRIPPLE = 100Hz. DC and AC Electrical Characteristics (Cont’d): (VDD = +5V, VDD1 = –5V, VDD2 = –15V, TA = +25°Cunless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit S/N – –100 – dB Rise Time tR – – 35 ns Fall Time tF – – 35 ns Bit Clock Cycle Time tCY 160 – – ns Bit Clock High Time tHB 48 – – ns Bit Clock Low Time tLB 48 – – ns Bit Clock Fall Time to Latch Rise Time tFBRL 0 – – ns Bit Clock Rise Time to Latch Fall Time tRBFL 0 – – ns Data Setup Time to Bit Clock tSDB 32 – – ns Data Hold Time to Bit Clock tHDB 0 – – ns Data Setup Time to System Clock tSDS 32 – – ns Word Select Hold Time to System Clock tHWS 0 – – ns Word Select Setup Time to System Clock tSWS 32 – – ns Bit Clock Fall Time to System Clock Rise Time tFBRS 32 – – ns System Clock Rise Time to Bit Clock Fall Time tRSFB 32 – – ns System Clock Fall Time to Bit Clock Rise Time tFSRB 50 – – ns Bit Clock Rise Time to System Clock Fall Time tRBFS 0 – – ns Latch Enable Low Time tLLE 20 – – ns Latch Enable High Time tHLE 32 – – ns Analog Outputs (AOL, AOR) (Cont’d) Signal–to–Noise Ratio at Bipolar Zero Timing Pin Connection Diagram LE/WS 1 BCK 2 28 VDD 27 OB/TWC Data l/Data Data R/SCK 3 4 26 VDD 1 25 AOL AGND 5 24 Decoupling AOR 6 23 Decoupling Decoupling 7 22 Decoupling Decoupling 8 21 Decoupling Decoupling 9 20 Decoupling Decoupling 10 Decoupling 11 19 Decoupling Decoupling 12 17 CCLK Decoupling 13 16 CCLK DGND 14 18 Decoupling 15 VDD 2 14 1 15 28 1.469 (37.32) Max .540 (13.7) .250 (6.35) .100 (2.54) 1.300 (33.02) .122 (3.1) Min .600 (15.24)