NTE21256 262,144–Bit Dynamic Random Access Memory (DRAM) Description: The NTE21256 is a 262,144 word by 1–bit dynamic Random Access Memory. This 5V–only component is fabricated with N–channel silicon gate technology. Nine multiplexed address inputs permit the NTE21256 to be packaged in an industry standard 16–Lead DIP package. Features of this device include single power supply with ±10% tolerance, on– chip address, date registers which eliminate the need for interface registers, and fully TTL compatible inputs and outputs, including clocks. In addition to the usual read, write, and read–modify–write cycles, the NTE21256 is capable of early and late write cycles, RAS–only refresh, and hidden refresh. Common I/O capability is given by using early write operation. The NTE21256 also features page mode which allows high–speed random access of bits in the same row. Features: D 262,144 x 1–Bit Organization D Single +5V Supply, ±10% Tolerance D Low Power Dissipation: –385mW active (Max) –28mW standby (Max) D Access Time: 150ns D Cycle Time: 260ns D All Inputs and Outputs TTL Compatible D On–Chip Substrate Bias Generator D Three–State Data Output D Read, Write, Read–Modify–Write, RAS–Only–Refresh, Hidden Refresh D Common I/O Capability using “Early Write” Operation D Page Mode Read and Write, Read–Write D 256 Refresh Cycles with 4ms Refresh Period Absolute Maximum Ratings: (Note 1) Operating Temperature Range, Topr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to +70°C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C Voltage on any pin relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 to +7V Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W Data Out Current (Short Circuit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Note 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional Description: Device Initialization Since the NTE21256 is a dynamic RAM with a single +5V supply, no power sequencing is required. For power–up, an initial pause of 200µs is necessary for the internal bias generator to establish the proper substrate bias voltage. To initialize the nodes of the dynamic circuitry, a minimum of 8 active cycles of the Row Address Strobe (RAS) has to be performed. This is also necessary after an extended inactive state of greater than 4ms. Addressing (A0–A8) For selecting one of the 262,144 memory cells, a total of 18 address bits are required. First 8 Row Address bits are set up on pins A0 through A8 and latched into the row address latches by the Row Address Strobe (RAS). Then the 9 column address bits are set up on pins A0 through A8 and latched into the column address latches by the Column Address Strobe (CAS). All input addresses must be stable on the falling edges of RAS and CAS. It should be noted that RAS is similar to a Chip Enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select activating the column decoder and the input and output buffers. Write Enable (WE) The read or write mode is selected with the WE input. A logic high (VIH) on WE dictates read mode; logic low (VIL) dictates write mode. The data input is disabled when read mode is selected. When WE goes low prior to CAS, data output (DO) will remain in the high–impedance state for the entire cycle permitting common I/O operation. Data Input (DI) Data is written during a write or read–modify–write cycle. The falling edge of CAS or WE strobes data into the on–chip data latch. In an early write cycle, WE is brought low prior to CAS and the data is strobed in by CAS with setup and hold times referenced to this signal. Data Output (DO) The output is three–state TTL compatible with a fan–out of two standard TTL loads. Data Out has the same polarity as Data In. The output is in a high impedance state until CAS is brought low. In a read cycle or read–write cycle, the output is valid after tRAC from transition of RAS when tRCD (Min) is satisfied, or after tCAC from transition of CAS when the transition occurs after tRCD (Max). In an early write cycle, the output is always in the high impedance state. In a delayed write or read–modify–write cycle, the output will follow the sequence for the read cycle. With CAS going high the output returns to the high impedance state within tOFF. Hidden Refresh RAS–only refresh cycle may take place while maintaining valid output data. This feature is referred to as Hidden Refresh. Hidden Refresh is performed by holding CAS at VIL of a previous memory read cycle. Refresh Cycle A refresh operation must be performed at least every 4ms to retain data. Since the output buffer is in the high impedance state unless CAS is applied, the RAS–only refresh sequence avoids any signal during refresh. Strobing each of the 256 row addresses (A0 through A7) with RAS, causes all bits in each row to be refreshed. CAS can remain high (inactive) for this refresh sequence to conserve power. Page Mode Page–mode operation allows effectively faster memory access by maintaining the row address and strobing random column addresses onto the chip. Thus, the time necessary to setup and strobe sequential row addresses for the same page is no longer required. The maximum number of columns that can be addressed in sequence is determined by tRAS, the maximum RAS low pulse width. DC Characteristics: (TA = 0° to +70°C, VSS = 0V, VCC = +5V ±10% unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Input High Voltage (All Inputs) VIH Notes 2, Note3 2.4 – VCC +1 V Input Low Voltage (All Inputs) VIL Notes 2, Note3 –1.0 – 0.8 V Output High Voltage VOH Note 4 2.4 – – V Output Low Voltage VOL Note 5 – – 0.4 V Average VCC Supply Current ICC1 tRC = 260ns, Note 6 – – 70 mA Standby VCC Supply Current ICC2 Note 7 – – 5 mA Average VCC Supply Current during RAS–only refresh cycles ICC3 Note 6 – – 65 mA Average VCC supply Current during Page Mode ICC4 Note 6 – – 55 mA Input Leakage Current (Any Input) II (L) – – 10 µA Output Leakage Current IO (L) CAS at Logic 1, 0 ≤ V out ≤ 5.5 – – 10 µA Supply Voltage VCC Note 2 4.5 – 5.5 V 0 – 0 V VSS Note 2. All voltages referenced to VSS. Note 3. Overshooting and undershooting on input levels of +6.5V or –2V for a period 0f 30ns Max. will influence function and reliability of the device. Note 4. IOH = 4mA and 100pf load. Note 5. IOL = 4mA and 100pf load. Note 6. ICC depends on frequency of operation. Maximum current is measured at the fastest cycle rate. Note 7. RAS and CAS are both at VIH. Capacitance: (Note 6) Parameter Symbol Test Conditions Min Typ Max Unit Input Capacitance (A0–A8, DI) CI1 – – 6 pF Input Capacitance (RAS, CAS, WE) CI2 – – 7 pF Output Capacitance (DO, CAS = VIH to disable output) CO – – 7 pF Note 6. Effective capacitance calculated from the equation: C= I • ∆t with ∆V = 3V or measured with Boonton meter. ∆V AC Test Conditions: Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns between 0.8 and 2.4V Input Timing Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 to 2.4V Output Timing Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 to 2.4V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . equivelent to 2 standard TTL loads and 100pf AC Characteristics: (TA = 0° to +70°C, VCC = 5V ±10%, Note 9, Note 10, Note 11 unless otherwise specified) Parameter Random Read or Write Cycle Time Symbol Test Conditions Min Typ Max Unit tRC Note 12 260 – – ns Read–Modify–Write Cycle Time tRWC Note 12 310 – – ns Access Time from RAS tRAC Notes 13, Note 14 – – 150 ns Access Time from CAS tCAC Notes 13, Note 15 – – 75 ns RAS Pulse Width tRAS 150 – 104 ns CAS Pulse Width tCAS 75 – – ns Refresh Period tREF – – 4 ms RAS Precharge Time tRP 100 – – ns CAS to RAS Precharge Time tCRP 0 – – ns RAS to CAS Delay Time tRCD 30 – 75 ns RAS Hold Time tRSH 75 – – ns CAS Hold Time tCSH 150 – – ns Row Address Setup Time tASR 0 – – ns Row Address Hold Time tRAH 20 – – ns Column Address Setup Time tASC 0 – – ns Column Address Hold Time tCAH 30 – – ns Column Address Hold Time referenced to RAS tAR Note 17 105 – – ns tT Note 9 3 – 50 ns 0 – – ns Transition Time (Rise and Fall) Note 16 Read Command Setup Time tRCS Read Command Hold Time referenced to CAS tRCH Note 18 0 – – ns Read Command Hold Time referenced to RAS tRRH Note 18 10 – – ns Output Buffer Turn–Off Delay tOFF Note 19 0 – 40 ns Note 9. VIH and VIL are reference levels to measure timing of input signals. Also, transition times are measured between VIH and VIL. Note10. An initial pause of 200µs is required after power–up followed by a minimum of eight initialization cycles prior to normal operation. Note 11. The time parameters specified here are valid for a transition time of tT = 5ns for the input signals Note12. The specification for tRC (Min), tRWC (Min), and page–mode cycle time (tPC) are only used to indicate cycle time at which proper operation over full temperature range (0°C ≤ TA ≤ +70°C) is assured. Note13. Measured with a load equivalent to two TTL loads and 100pf. Note14. Assumes that tRCD ≤ tRCD (Max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. Note15. Assumes that tRCD ≤ tRCD (Max). Note16. Operation within the tRCD (Max) limit ensures that tRAC (Max) can be met. tRCD (Max) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max) limit, then access time is controlled exclusively by tCAC. Note17. tRCD + tCAH ≥ tAR Min, tRCD + tDH ≥ tDHR Min, tRCD + tWCH ≥ tWCR Min. Note18. Either tRRH or tRCH must be satisfied for a read cycle. Note19. tOFF (Max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. AC Characteristics (Cont’d): (TA = 0° to +70°C, VCC = 5V ±10%, Note 9, Note 10, Note 11 unless otherwise specified) Parameter Symbol Write Command Setup Time tWCS Write Command Hold Time tWCH Write Command Hold Time referenced to RAS tWCR Test Conditions Note 20 Note 17 Min Typ Max Unit 0 – – ns 45 – – ns 120 – – ns Write Command Pulse Width tWP 45 – – ns Write Command to RAS Lead Time tRWL 45 – – ns Write Command to CAS Lead Time tCWL 45 – – ns Data in Setup Time tDS Note 21 0 – – ns Data in Hold Time tDH Note 21 45 – – ns Data in Hold Time referenced to RAS tDHR Note 17 120 – – ns CAS to WE Delay tCWD Note 20 75 – – ns RAS to WE Delay tRWD Note 20 150 – – ns RMW Cycle RAS Pulse Width tRRW 200 – – ns RMW Cycle CAS Pulse Width tCRW 125 – – ns 145 – – ns tPRWC 190 – – ns tCP 60 – – ns Page Mode Cycle Time Page Mode Read–Write Cycle Time Page Mode CAS Precharge Time tPC Note 12 Note 9. VIH and VIL are reference levels to measure timing of input signals. Also, transition times are measured between VIH and VIL. Note10. An initial pause of 200µs is required after power–up followed by a minimum of eight initialization cycles prior to normal operation. Note 11. The time parameters specified here are valid for a transition time of tT = 5ns for the input signals Note12. The specification for tRC (Min), tRWC (Min), and page–mode cycle time (tPC) are only used to indicate cycle time at which proper operation over full temperature range (0°C ≤ TA ≤ +70°C) is assured. Note17. tRCD + tCAH ≥ tAR Min, tRCD + tDH ≥ tDHR Min, tRCD + tWCH ≥ tWCR Min. Note20. tWCS, tCWD, and tRWC are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: If tWCS ≥ tWCS (Min), the cycle is an early write cycle and the Data Out will remain open circuit (high impedance) throughout the entire cycle; if tCWD ≥ tCWD (Min) and tRWD ≥ tRWD (Min) the cycle is a read–write cycle and the Data Out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the Data Out (at access time) is indeterminate. Note21. tDS and tDH are referenced to the leading edge of CAS in early write cycles, and to the leading edge of WE in delayed write of read–modify–write cycles. Pin Connection Diagram A8 1 16 VSS DI 2 15 CAS WE 3 14 DO RAS 4 13 A6 A0 5 12 A3 A2 6 11 A4 A1 7 10 A5 VCC 8 9 A7 16 9 .260 (6.6) Max 1 8 .785 (19.9) Max .300 (7.62) .200 (5.08) Max .245 (6.22) Min .100 (2.54) .700 (17.7)