FEDL7020-02 1Semiconductor ML7020 This version: Nov. 2000 Previous version: Feb. 2000 1200 bps MODEM for Remote Control Systems GENERAL DESCRIPTION The ML7020 is a 1200 bps modem LSI developed for remote control systems. The functions incorporated are those of a 1200 bps FSK modem conforming to ITU-T Recommendations V.23, DTMF signal generation and detection, call progress tone (CPT) generation and detection. Each functional block can be controlled via a 4-bit processor interface. FEATURES • Single 5 V power supply operation (VDD: 4.5 to 5.5 V) • Low power consumption: During operation: 5 mA typ. During the power down mode: 7 µA typ. • Built-in 1200 bps modem conforming to ITU-T V.23 recommendations • Built-in DTMF signal generator with a switchable 6-dB attenuator • Built-in DTMF detector (the input can be selected from either the line or the terminal) • Built-in call progress tone generator. The output frequency can be selected from 400 Hz and 800 Hz. • Built-in call progress tone detector • Three analog input systems (switchable) • Analog output for the line is of the differential type and can drive a 600 Ω line transformer. • Analog output for the terminal is of the single-ended type and can drive a 1.2 kΩ load. • Built-in switch for selecting the 600 Ω termination • 4-Bit processor interface • Built-in oscillator circuit for a 3.579545 MHz crystal • Package: 32-Pin plastic SSOP (SSOP32-P-430-1.00-K) (Product name: ML7020MB) 1/19 FEDL7020-02 1Semiconductor ML7020 BLOCK DIAGRAM Input Amplifier 1 SW1 TI– DTMF Reception TI+ TIO SP Input Amplifier 2 CPT Detection LI1– LI1+ LI1O DETB SW2 Input Amplifier 3 LI2– Modem Reception RD LI2O Output Amplifier 1 SW4 CPT Transmission TO 1.2 kΩ Output Amplifier 2 LO– LO+ Modem Transmission –1 1.2 kΩ PostLPF +1 SW5 XD DTMF Transmission ATT Output Amplifier 3 SWI SW3 SGO SGC SG X1 Oscillator Circuit X2 CLKO D3 to D0 A1, A0 WRB RDB CSB VDD GND MCU I/F * CPT: Call progress tone * The state shown of each switch is that when the register is set to “0”. 2/19 FEDL7020-02 1Semiconductor ML7020 PIN CONFIGURATION (TOP VIEW) 32-Pin plastic SSOP VDD 1 32 SP TIO 2 31 DETB TI– 3 30 RD TI+ 4 29 XD LI1O 5 28 X1 LI1– 6 27 X2 LI1+ 7 26 CLKO SWI 8 25 D3 SGO 9 24 D2 LI2O 10 23 D1 LI2– 11 22 D0 TO 12 21 A1 LO+ 13 20 A0 LO– 14 19 WRB SGC 15 18 RDB GND 16 17 CSB 3/19 FEDL7020-02 1Semiconductor ML7020 PIN DESCRIPTIONS Pin No. Symbol I/O Description 1 VDD Power supply pin. 2 TIO O The output pin of the input amplifier 1. See Figure 1. For the sake of noise reduction, connect a capacitor between this pin and TI– (3) so as to attenuate high frequency components above 10 kHz. 3 TI– I The inverting input pin for the input amplifier 1. When the input amplifier 1 is not used, connect pin TIO (2) to pin TI– (3), and connect pin TI+ (4) to pin SGO. 4 TI+ I The non-inverting input pin for the input amplifier 1. Connect a +5 V power supply to this pin. 5 LI1O O The output pin for the input amplifier 2. See Figure 1. For the sake of noise reduction, connect a capacitor between this pin and LI1– (6) so as to attenuate high frequency components above 10 kHz. 6 LI1– I The inverting input pin for the input amplifier 2. When the input amplifier 2 is not used, connect pin LI1O (5) and LI1– (6), and connect pin LI+ (7) to pin SGO. 7 LI1+ I The non-inverting input pin for the input amplifier 2. 8 SWI I The input pin for SW3. to be made ON. 9 SGO O The signal ground output pin for external circuits. output from this pin. 10 LI2O O The output pin for the input amplifier 3. See Figure 1. For the sake of noise reduction, connect a capacitor between this pin and LI2– (10) so as to attenuate high frequency components above 10 kHz. 11 LI2– I 12 TO O 13 LO+ O The non-inverting output pin for the output amplifier 2. See Figure 2 for details of connecting a peripheral circuit. 14 LO– O The inverting output pin of the output amplifier 2. connecting a peripheral circuit. See Figure 2 for details of SGC O The signal ground output pin for internal circuits. output from this pin. A voltage of about VDD/2 is 15 This pin is connected internally to SGO (9) when SW3 is A voltage of about VDD/2 is The inverting input pin for the input amplifier 3. When the input amplifier 3 is not used, connect pin LI2O (10) and LI2– (11). The output pin of the output amplifier 1. Can drive a load of 1.2 kΩ or more. Connect a 1 µF capacitor between SGC (15) and GND (16). 16 GND The ground pin for the LSI. Connect a 0 V input to this pin. The chip select pin for the processor interface. 17 CSB I 18 RDB I 19 WRB I 20 A0 I Reading and writing are possible when this input is “0”. disabled when this input is “1”. Reading and writing are The read control pin for the processor interface. Data can be read from the LSI when this pin is “0”. The write control pin for the processor interface. Data is written into this LSI at the rising edge of the WR signal. The address input pin A0 for the processor interface. 4/19 FEDL7020-02 1Semiconductor Pin No. Symbol ML7020 I/O I Description 21 A1 22 D0 IO The data input/output pin D0 for the processor interface. The address input pin A1 for the processor interface. 23 D1 IO The data input/output pin D1 for the processor interface. 24 D2 IO The data input/output pin D2 for the processor interface. 25 D3 IO The data input/output pin D3 for the processor interface. 26 CLKOUT O The 3.579545 MHz oscillator circuit output pin. 27 X2 O 28 X1 I The pins for connecting a 3.579545 MHz crystal. The capacitors and the feedback resistor are internally connected to these pins. When inputting an external clock, connect the input to the X1 pin via a 1000 pF capacitor and leave the pin X2 open. 29 XD I 30 RD O The modem transmit data input pin. 31 DETB O 32 SP O The “1” level corresponds to the mark data and the “0” level corresponds to the space data. The modem receive data output pin. The mark and space data are the same as for XD. A mark is output when no carrier is detected. The pin for outputting the carrier detect signal of the modem or the call progress tone detector output. The detection result corresponding to the respective operating mode is output from this pin. A “0” indicates detection and a “1” indicates non-detection. The DTMF reception detection output pin. A “0” indicates detection and a “1” indicates non-detection. 5/19 FEDL7020-02 1Semiconductor ML7020 TIO R1 C1 R2 Example: The cutoff frequency is fc = 10 kHz, when R1 = R2 = 30 kΩ (gain = 1), and C1 is 500 pF Input amplifier 1 TI– Terminal→ TI+ VREF SGO LI1O R3 C2 R4 Input amplifier 2 Example: The cutoff frequency is fc = 10 kHz, when R3 = R4 = 30 kΩ (gain = 1), and C2 is 500 pF LI1– Line 1→ LI2O R5 C3 R6 Input amplifier 3 Example: The cutoff frequency is fc = 10 kHz, when R5 = R6 = 30 kΩ (gain = 1), and C3 is 500 pF LI2– Line 2→ Figure 1 Input amplifier 1 to 3 interface 600 Ω LO– (–10.0 dBm) Output amplifier 2 600 Ω: 600 Ω 0.022 µF –10.0 dBm (–10.0 dBm) LO+ Output amplifier 3 Figure 2 (When the transformer loss is 0 dB) Output amplifier 2, 3 interface example 6/19 FEDL7020-02 1Semiconductor ML7020 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Power supply voltage VDD — –0.3 to +7.0 V Permissible power dissipation PD — to 130 mW Output short circuit current ISHT Shorted to VDD or ground. to 60 mA Analog input voltage VAIN — –0.3 to VDD + 0.3 V Digital input voltage VDIN — –0.3 to VDD + 0.3 V Storage temperature range Tstg — –55 to +150 °C RECOMMENDED OPERATING CONDITIONS (VDD = 4.5 to 5.5 V, Ta = –40 to +85°C) Parameter Symbol Condition Power supply voltage VDD Operating temperature range Ta High level input voltage VIH Digital input pins Low level input voltage VIL Digital input pins 0 — Digital input rise time tir Digital input pins — — Digital input fall time Min. Typ. — 4.5 5.0 5.5 V — –40 — +85 °C — VDD V 0.8 × VDD Max. 0.2 × VDD 50 Unit V ns tif Digital input pins — — 50 ns Digital output load CDL Digital output pins — — 100 pF Bypass capacitor for SGC CSG Between SGC and GND 1 — — µF Bypass capacitor for VDD CVG Between VDD and ground 10 — — µF Oscillating frequency — — — 3.579545 — MHz Frequency deviation 25 ±5°C –100 — +100 ppm — In the temperature range –40 to +85°C –50 — +50 ppm Equivalent series resistor — — — — 90 Ω Production load capacitance — — — 16 — pF Input clock frequency deviation fCLK –0.1 — +0.1 % Input clock duty ratio DUTY Values when an X1 external clock is input 40 — 60 % Crystal — Temperature characteristics 7/19 FEDL7020-02 1Semiconductor ML7020 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 4.5 to 5.5 V, Ta = –40 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit IDD1 During operation (modem transmission/reception mode)*1 0 5.0 10.0 mA IDD2 During operation (tone 1 mode)*1 0 5.0 10.0 mA IDD3 During operation (tone 2, tone 3 modes)*1 0 6.0 11.0 mA IDD4 During power down 0 7.0 100 µA IIH VI = VDD — — 2.0 µA IIL VI = 0 V — — 0.5 µA High level output voltage VOH IOH = –100 µA — VDD V Low level output voltage VOL IOL = 100 µA 0 0.05 0.1 V Input capacitance CIN — — 5 — pF Power supply current Input leak current VDD –0.1 *1: See Table 3 for details of the modes. Analog Interface (VDD = 4.5 to 5.5 V, Ta = –40 to +85°C) Parameter Input resistance Output load resistance Output load capacitance Output impedance Output DC voltage Out-of-band spurious response Symbol Condition Min. Typ. Max. Unit RIN TI–, TI+, LI1–, LI1+, LI2– 10 — — MΩ RL1 TIO, LI1O, LI2O 20 — — kΩ RL2 TO (Output amplitude 1 Vpp or less) 1.2 — — kΩ RL3 LO–, LO+ (differential outputs) 1.2 — — kΩ CL Analog outputs — — 100 pF ROX1 TIO, LI1O, LI2O, TO — 10 — Ω ROX2 LO–, LO+, SGO — 10 — Ω VO1 TIO, LI1O, LI2O, TO, LO–, LO+, SGC — VDD/2 — V VO2 SGO VS1 VS2 VS3 VDD/2 –0.1 4 to 8 kHz LO–, LO+ 8 to 12 kHz (Differential outputs) 12 kHz to (4 kHz each) VDD/2 VDD/2 +0.1 V — –60 –20 dBm — –80 –40 dBm — –80 –60 dBm SW3 impedance RSW3 SW3 — 15 30 Ω Output current ISGO SGO pin (including via SW3) –0.6 — 0.6 mA 8/19 FEDL7020-02 1Semiconductor ML7020 AC Characteristics (DTMF Section) (VDD = 4.5 to 5.5 V, Ta = –40 to +85°C) Parameter Symbol Condition VDTTL Transmit level LO–, LO+_Differential *1 VDTTH Transmit signal level relative value Transmit signal frequency deviation Transmit signal distortion rate DTMF detection level DTMF non-detection level Detection frequency band Non-detection frequency band Level difference between two received frequencies Permissible received noise level Received dial tone elimination ratio Signal repetition period Input signal persistence duration Signal quiet duration Instantaneous break protection period Detection delay time Detection hold time SP delay time Signal repetition period Input signal persistence duration Signal quiet duration Instantaneous break protection period Detection delay time Detection hold time SP delay time ATT attenuation Lower group tone Higher group tone Min. Typ. Max. Unit –7.0 –4.5 –3.0 dBm –5.5 –2.5 –1.0 dBm VDTDF (Higher group tone) – (lower group tone) 1 2 3 dB fDDT Relative to the nominal frequency –1.5 — +1.5 % THDDT (Harmonic waves) – (fundamental wave) — — –23 dB VDETDT VREJDT fDETDT For one frequency For one frequency Relative to the nominal frequency –42 — — — — — –6 –60 ±1.5 dBm dBm % fREJDT Relative to the nominal frequency ±3.8 —- — % VTWIST (Higher group tone) – (lower group tone) –6 — +6 dB LOSSR6 (Noise level) – (tone level) 0.3 to 3.4 kHz — –12 — dB VREJCP 380 to 420 Hz 37 53 — dB 120 49 — 30 — — 24 24 0.2 60 35 — 21 — — 12 15 0.2 –7.5 — — — — — — 41 28 0.6 — — — — — — 26 20 0.6 –6 — — 24 — 0.4 10 49 35 1.0 — — 10 — 0.4 3.0 37 27 1.0 –4.5 ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms dB tc ts tl tp tba tbb tg td tsp tc ts tl tp tba tbb tg td tsp VATT During the tone 1, tone 2, and loop back modes. See Figure 3 and Table 3 for details. During the tone 3 mode. See Figure 3 and Table 3 for details. Detection Non-detection SP = 0 SP = 1 Detection Non-detection SP = 0 SP = 1 Relative to the ATT = “0” reference Note: 0 dBm = 0.775 Vrms *1: The value will be 6 dB smaller for pin LO+ or pin LO– alone. 9/19 FEDL7020-02 1Semiconductor ML7020 tba tc tl tbb tp ts DTMF signal tg td DTMF receive data SP tsp Figure 3 DTMF reception timing ts: Input signal persistence duration (detection) Normal reception is made when the input signal persistence duration is equal to ts or more. tI: Input signal persistence duration (non-detection) The input signal is ignored when the input signal persistence duration is less than tI, and the SP and DTMF receive data are not output. tp: Signal quiet duration The DTMF receive data and SP are reset if the input continues to be in the no-signal condition for a duration equal to tp or longer. Also, even if the receive data changes during DTMF signal reception, SP continues to be “1” and the DTMF receive data may remain in the initial value and may not change, if the signal quiet duration is less than tp (including when it changes without any instantaneous break). tba: Instantaneous break protection period 1 This is applicable to the period after the input signal has arrived and until the timing when SP becomes “1”. In other words, SP and DTMF receive data are output normally even if a no-signal condition of a duration less than tba occurs. tbb: Instantaneous break protection period 2 This is applicable when SP is “1” (during output of the receive data). In other words, SP and the DTMF receive data are not reset even if a no-signal condition of a duration less than tbb occurs during signal reception. tc: For ensuring normal reception, make sure that the signal repetition period is equal to tc or more. tg: Detection delay time The DTMF receive data is output with a delay of tg relative to the appearance of the input signal. td: Detection hold time The output of SP or the DTMF receive data is stopped with a delay of td after the termination of the input signal. tsp: SP delay time SP is output after a delay of tsp relative to the output of the DTMF receive data. Therefore, latch the DTMF receive data when the rising edge of SP is detected. 10/19 FEDL7020-02 1Semiconductor ML7020 AC Characteristics (Modem Section) (VDD = 4.5 to 5.5 V, Ta = –40 to +85°C) Symbol Condition Min. Typ. Max. Unit Modem transmit level Parameter VAOM LO–, LO+ Differential –6.0 –4.0 –2.0 dBm Transmit signal level relative value VDM (Mark signal) – (space signal) –1.5 0 +1.5 dB Transmit carrier frequency Receive signal level Carrier detection level fM — XD = 1 1292 1300 1308 Hz fS — XD = 0 2092 2100 2108 Hz –51 — –6 dBm VON VAI Level of LI1O and LI2O Level of LI1O and LI2O OFF → ON — –44.5 –42 dBm VOFF 1700 Hz ON → OFF –51 –46.5 — dBm 2 — dB Carrier detection hysteresis vHYS — Carrier detection delay time tCDD OFF → –30 dBm 5 10 15 ms Carrier detection hold time tCDH –30 dBm → OFF 23 28 34 ms Demodulation bias distortion DBS 1200 bps, 1:1 pattern –10 — +10 % Note: RD is fixed at “1” when the carrier detector is OFF. AC Characteristics (CLKO) (VDD = 4.5 to 5.5 V, Ta = –40 to +85°C) Parameter Symbol Condition VCOH Output amplitude CL = 100 pF VCOL Min. Typ. Max. Unit 0.9 × VDD — VDD V 0 — 0.1 × VDD V 11/19 FEDL7020-02 1Semiconductor ML7020 AC Characteristics (Call Progress Tone Section) (VDD = 4.5 to 5.5 V, Ta = –40 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit Transmit level VCPT Pin TO –21.5 –20.0 –18.5 dBm Transmit frequency fCPT During 400 Hz output 380 400 420 Hz During 800 Hz output 780 800 820 Hz –23 dB Pin TO Distortion rate THDCPT Pin TO — — Detection level VDETCP 400 Hz, level of LI1O and LI2O –46 — –6 dBm Non-detection level VREJCP 400 Hz, level of LI1O and LI2O — — –60 dBm Detection frequency fDETCP — 360 — 440 Hz 510 — — Hz — — 300 Hz Detection 30 — — ms Non-detection — — 10 ms Non-detection frequency frejCP — Detection persistence period tDETCP Detection delay time tDELCP 10 17 30 ms Detection hold time tHOLCP 10 17 30 ms tREJCP See Figure 4. tREJCP tDETCP CPT input tDELCP tHOLCP DETB Figure 4 Call progress tone detection timing 12/19 FEDL7020-02 1Semiconductor ML7020 AC Characteristics (Processor Interface) (VDD = 4.5 to 5.5 V, Ta = –40 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit Write signal period PW 2000 — — ns Write signal width TW 100 — — ns Read signal width TR 200 — — ns TAW1 10 — — ns TAR1 80 — — ns TAW2 50 — — ns 10 — — ns 10 — — ns TCR1 80 — — ns TCW2 50 — — ns TCR2 10 — — ns Data setup time TDW1 110 — — ns Data hold time Address data setup time Address data hold time TAR2 TCW1 Chip select setup time Chip select hold time See Figure 5. TDW2 20 — — ns Data output delay time tpd1 20 60 150 ns Data output hold time tpd2 20 40 100 ns A1, A0 CSB Address TAW1 TCW1 Address TAW2 TAR1 TAR2 TCW2 TCR1 TCR2 WRB RDB TR TW tpd2 TDW1 TDW2 Write data D0 to D3 Figure 5 tpd1 Read data Processor interface timing 13/19 FEDL7020-02 1Semiconductor ML7020 FUNCTIONAL DESCRIPTION Description of Processor Interface • List of Registers Table 1 * * List of processor interface registers A1 A0 R/W D3 D2 D1 D0 0 0 W PBG3 PBG2 PBG1 PBG0 0 1 R/W SW1 CONT MODE2 MODE1 MODE0 1 0 R/W SW3 CONT SW2 CONT CPTG ON CPT800 1 1 R/W SW5 CONT SW4 CONT MOD-DT ON ATT 0 0 R PBR3 PBR2 PBR1 PBR0 Data written into the registers other than the register [(A1, A0) = (0,0)] can be read out. Immediately after switching ON the power, use the LSI only after clearing the control registers using the power down mode. • PBG3 to 0/PBR3 to 0 The registers PBG3 to 0 are used for setting the DTMF transmit data. The registers PBR3 to 0 are used for reading the DTMF receive data. The output frequency does not change even if the code is changed during transmission. Table 2 shows the data assignments. Table 2 DTMF transmit/receive data assignments D3 D2 D1 D0 PBG3/ PBG2/ PBG1/ PBG0/ PBR3 PBR2 PBR1 PBR0 0 0 0 0 0 1 0 0 0 0 CODE Lower group frequency (Hz) Higher group frequency (Hz) 1 1 697 1209 0 2 697 1336 1 1 3 697 1477 1 0 0 4 770 1209 1 0 1 5 770 1336 0 1 1 0 6 770 1477 0 1 1 1 7 852 1209 1 0 0 0 8 852 1336 1 0 0 1 9 852 1477 1 0 1 0 0 941 1336 1 0 1 1 ∗ 941 1209 1 1 0 0 # 941 1477 1 1 0 1 A 697 1633 1 1 1 0 B 770 1633 1 1 1 1 C 852 1633 0 0 0 0 D 941 1633 14/19 FEDL7020-02 1Semiconductor ML7020 • MODE2 to MODE0 These registers are used for setting the mode. Table 3 The contents of setting are shown in Table 3. List of mode settings Operation of different blocks MODE2 MODE1 MODE0 Mode name Modulator Demodulator DTMF DTMF CPT CPT section section transmission reception transmission reception Modem 0 0 0 O – – – O – transmission Modem reception 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 Test 1 1 1 Power down (Note 3) Tone 1 (Note 1) Tone 2 (Note 1) Tone 3 (Note 1) Loop back (Note 2) – O – – O – – – – O O – – – O O O O – – O O O O O O O O – – – – LSI internal test – – – – *[O]: Operating condition, [–]: Power down condition Note 1: Tone 1, 2, 3 modes The DTMF detection timing is different in the tone 1, 2, loop back modes from that in the tone 3 mode. In the tone 3 mode, the DTMF detection goes into the high speed detection mode. In this mode, since the detector can make incorrect detection due to voice signals or noise, avoid using the tone 3 mode if there is any margin available in the timing. Note 2: Loop back mode The modem loop back mode is initiated when SW5CONT is High and MOD-DT_ON is High. (The data input in XD is output from RD via the internal circuits.) The DTMF loop back mode is initiated when SW5CONT is Low and MOD-DT_ON is High. (The data set in PBG3 to PBG0 is latched at the rising edge of MOD-DT_ON, and is output at PBR3 to PBR0 via the internal circuits.) Note 3: Power down mode The conditions when the LSI is put in the power down mode are listed below. Each blocks: Stop operating and the internal circuits are reset. Analog output pins: Go to the high-impedance state DETB, RD, CLKO pins: High level SP, X2 pins: Low level Processor interface registers: Low level (excepting SW1CONT, MODE2, 1, 0) 15/19 FEDL7020-02 1Semiconductor ML7020 • SW1CONT This is the switch for selecting the DTMF reception input. 0: The input amplifier 1 is connected to the DTMF reception circuit. 1: The input amplifier 2 is connected to the DTMF reception circuit. • SW2CONT This is the switch for selecting the modem reception and CPT detection inputs. 0: The input amplifier 2 is connected to the modem reception circuit and the CPT detection circuit. 1: The input amplifier 3 is connected to the modem reception circuit and the CPT detection circuit. • SW3CONT This is the switch for external circuits, and can be used for connecting the termination, etc. 0: The switch goes into the OFF state. 1: The switch goes into the ON state. (The SWI pin and the SGO pin are connected together.) • SW4CONT This is the switch for selecting the signal (TO) of the output amplifier 1. 0: The CPT transmit output is connected to the output amplifier 1. 1: The output signal of SW2 is connected to the output amplifier 1. • SW5CONT This is the switch for selecting the signal (LO–, LO+) of the output amplifier 2. 0: The DTMF transmit output is connected to the output amplifier 2. 1: The modem transmit output is connected to the output amplifier 2. Set this to “1” during the modem transmit mode and set this to “0” during the DTMF transmit mode. • CPTG_ON This register is used for the ON/OFF control of call progress tone transmission. 0: CPT transmission becomes OFF and the signal is not output. 1: CPT transmission becomes ON and the signal is output. • CPT800 This selects the frequency of call progress tone transmission. 0: A 400 Hz signal is output. 1: An 800 Hz signal is output. • MOD-DT_ON This is used for the ON/OFF control of modem transmission or DTMF transmission. The transmission function is made ON/OFF of the block corresponding to the selected mode. 0: Modem transmission or DTMF transmission become OFF and the signal is not output. 1: Modem transmission or DTMF transmission become ON and the signal is output. In the DTMF transmission mode or in the DTMF loop back mode, PBG3 to 0 are latched at the rising edge of MOD-DT_ON. Set this to “0” during the modem reception mode and the tone 1 mode. • ATT This controls the attenuator of the DTMF transmission section. 0: No attenuator is inserted. The DTMF transmit signal is output as it is. 1: A –6 dB attenuator is inserted in the DTMF transmission section. 16/19 FEDL7020-02 1Semiconductor ML7020 APPLICATION CIRCUIT EXAMPLE 500 pF 30 kΩ From terminal 30 kΩ 500 pF 30 kΩ From line 30 kΩ To terminal To line 10 µF 1 µF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD TIO TI– TI+ LI1O LI1– LI1+ SWI SGO LI2O LI2– TO LO+ LO– SGC GND ML7020 SP DETB RD XD X1 X2 CLKO D3 D2 D1 D0 A1 A0 WRB RDB CSB 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 3.579545 MHz MCU I/F 17/19 FEDL7020-02 1Semiconductor ML7020 PACKAGE DIMENSIONS (Unit: mm) SSOP32-P-430-1.00-K Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 0.60 TYP. 3/Dec. 5, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/19 FEDL7020-02 1Semiconductor ML7020 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-todate. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd. 19/19