NEC UPD75P316AGF-3B9

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P316A
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD75P316A is a product of the µPD75316 with on-chip ROM having been replaced with the one-time PROM
or EPROM.
It is most suitable for test production during system development and for production in small amounts since it
can operate under the same supply voltage as mask products.
The one-time PROM product is capable of writing only once and is effective for production of many kinds of sets
in small quantities and early startup. The EPROM product allows program writing and rewriting, and is therefore
suitable for system evaluation. The on-chip RAM has twice the capacity of the µPD75316/75P316, enabling large
amounts of data to be processed.
Details of functions are described in the User's Manual shown below. Be sure to read in design.
µPD75308 User's Manual : IEM-5016
FEATURES
• Compatible (excluding mask option) with the mask products
• Memory capacity
• Program memory (PROM) : 16256 × 8 bits
• Data memory (RAM)
: 1024 × 4 bits
• Low-voltage operation capability: 2.7 to 6.0 V
ORDERING INFORMATION
Ordering Code
µ PD75P316AGF-3B9
µ PD75P316AK
Package
80-pin plastic QFP (14 × 20 mm)
80-pin ceramic WQFN (LCC with window)
On-Chip ROM
One-time PROM
EPROM
Package
80-pin plastic QFP (14 × 20 mm)
80-pin ceramic WQFN (LCC with window)
Quality Grade
Standard
Standard
QUALITY GRADE
Ordering Code
µ PD75P316AGF-3B9
µ PD75P316AK
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
In descriptions common to one-time PROM products and EPROM products in this document, the term "PROM" is
used.
The information in this document is subject to change without notice.
Document No. IC-2524A
(O. D. No. IC-7950B)
Date Published October 1993 P
Printed in Japan
The mark ★ shows major revised points.
© NEC Corporation 1992
µPD75P316A
80797877767574737271706968676665
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25262728293031323334353637383940
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43
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41
VLC0
VLC1
VLC2
P40
P41
P42
P43
VSS
P50
P51
P52
P53
P00/INT4
P01/SCK
P02/SO/SB0
BIAS
µPD75P316AGF
µPD75P316AK
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24/BP0
S25/BP1
S26/BP2
S27/BP3
S28/BP4
S29/BP5
S30/BP6
S31/BP7
COM0
COM1
COM2
COM3
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
RESET
P73/KR7
P72/KR6
P71/KR5
S11
PIN CONFIGURATION (Top View)
P70/KR4
P63/KR3
P62/KR2
P61/KR1
P60/KR0
X2
X1
VPP
XT2
XT1
VDD
P33 (MD3)
P32 (MD2)
P31/SYNC (MD1)
P30/LCDCL (MD0)
P23/BUZ
P22/PCL
P21
P20/PTO0
P13/TI0
P12/INT2
P11/INT1
P10/INT0
P03/SI/SB1
m
INTBT
TI0/P13
PTO0/P20
BUZ/P23
PROGRAM
COUNTER (14)
SP(8)
m
4
P00-P03
PORT1
4
P10-P13
PORT2
4
P20-P23
PORT3
4
P30-P33
/MD0-MD3
PORT4
4
P40-P43
PORT5
4
P50-P53
PORT6
4
P60-P63
PORT7
4
P70-P73
24
S0-S23
CY
ALU
TIMER/EVENT
COUNTER
#0
INTT0
BANK
WATCH
TIMER
INTW
fLCD
GENERAL REG.
PROGRAM
MEMORY
DECODE
AND
CONTROL
(PROM)
SI/SB1/P03
SO/SB0/P02
SCK/P01
PORT0
SERIAL BUS
INTERFACE
BLOCK DIAGRAM
BASIC
INTERVAL
TIMER
16256 × 8 BITS
DATA
MEMORY
(RAM)
1024 × 4 BITS
INTCSI
INT0/P10
INT1/P11
INT2/P12
INTERRUPT
CONTROL
INT4/P00
KR0/P60
–KR7/P73
LCD
CONTROLLER
/DRIVER
N
fX / 2
BIT SEQ.
BUFFER (16)
SYSTEM CLOCK
CLOCK
CLOCK
GENERATOR STAND BY
OUTPUT
DIVIDER
SUB MAIN CONTROL
CONTROL
XT1 XT2 X1 X2
fLCD
VPP VDD VSS RESET
S24/BP0
–S31/BP7
4
COM0–COM3
3
VLC0–VLC2
BIAS
LCDCL/P30
SYNC/P31
3
µPD75P316A
PCL/P22
CPU
CLOCK
8
µPD75P316A
CONTENTS
1.
PIN FUNCTIONS ......................................................................................................................................... 5
1.1
1.2
1.3
1.4
★
PORT PINS ........................................................................................................................................................... 5
OTHER PINS ......................................................................................................................................................... 7
PIN INPUT/OUTPUT CIRCUITS ......................................................................................................................... 9
CAUTION ON USING P00/INT4 PIN AND RESET PIN .................................................................................. 11
2.
DIFFERENCES BETWEEN PRODUCTS IN SERIES ............................................................................... 11
3.
DATA MEMORY (RAM) ............................................................................................................................ 13
4.
PROGRAM MEMORY WRITE AND VERIFY ........................................................................................... 15
4.1
4.2
PROGRAM MEMORY WRITE/VERIFY OPERATING MODES ....................................................................... 15
PROGRAM MEMORY WRITING PROCEDURE ............................................................................................... 16
4.3
4.4
PROGRAM MEMORY READING PROCEDURE ............................................................................................... 17
ERASURE METHOD .......................................................................................................................................... 18
5.
ELECTRICAL SPECIFICATIONS ............................................................................................................... 19
6.
PACKAGE INFORMATION ....................................................................................................................... 35
7.
RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 37
APPENDIX A. DEVELOPMENT TOOLS ......................................................................................................... 38
★
APPENDIX B. RELATED DOCUMENTS ........................................................................................................ 39
4
µPD75P316A
1. PIN FUNCTIONS
1.1
PORT PINS (1/2)
Pin Name
Input/Output
DualFunction Pin
P00
Input
INT4
P01
Input/output
SCK
P02
Input/output
SO/SB0
P03
Input/output
SI/SB1
P11
INT1
Input
P12
INT2
P13
TI0
P20
PTO0
—
P21
Input/output
P22
PCL
P23
BUZ
P30 *2
LCDCL MD0
P31 *2
SYNC
MD1
Input/output
P32 *2
MD2
P33 *2
MD3
8-Bit I/O
Afer Reset
I/O Circuit
Type*1
B
4-bit input port (PORT0)
Internal pull-up resistor specification by software is possible for P01 to P03 as a 3-bit unit.
×
F -A
Input
F -B
M-C
With noise elimination circuit
INT0
P10
4-bit input port (PORT1)
Internal pull-up resistor specification by software is possible as a 4-bit unit.
×
Input
B -C
4-bit input/output port (PORT2)
Internal pull-up resistor specification by software is possible as a 4-bit unit.
×
Input
E-B
Programmable 4-bit input/output port (PORT3)
Input/output settable bit-wise.
Internal pull-up resistor specification by software is possible as a 4-bit unit.
×
Input
E-B
P40 to P43*2
Input/output
—
N-ch open-drain 4-bit input/output port (PORT
4).
Data input/output pins for program memory
(PROM) write/verify (low-order 4 bits).
High impedance
M-A
P50 to P53 *2
Input/output
—
N-ch open-drain 4-bit input/output port (PORT 5)
Data input/output pins for program memory
(PROM) write/verify (high-order 4 bits).
High impedance
M-A
Programmable 4-bit input/output port (PORT6).
Input/output settable bit-wise.
Internal pull-up resistor specification by software is possible as a 4-bit unit.
Input
F -A
4-bit input/output port (PORT7).
Internal pull-up resistor specification by software is possible as a 4-bit unit.
Input
F -A
P60
P61
KR0
Input/output
KR1
P62
KR2
P63
KR3
P70
KR4
P71
*
Function
Input/output
KR5
P72
KR6
P73
KR7
1.
: Indicates a Schmitt-triggered input.
2 . Direct LED drive capability.
5
µPD75P316A
1.1
PORT PINS (2/2)
Pin Name
Input/Output
BP0
DualFunction Pin
Function
8-Bit I/O
After Reset
I/O Circuit
TYPE
×
*
G-C
S24
BP1
S25
Output
BP2
S26
BP3
S27
BP4
S28
BP5
1-bit output port (BIT PORT)
Dual-function as segment output pins.
S29
Output
*
6
BP6
S30
BP7
S31
For BP0 to BP7, VLC1 is selected as the input source. The output level depends on BP0 to BP7 and the VLC1 external
circuit, however.
µPD75P316A
1.2
OTHER PINS
Input/Output
DualFunction Pin
TI0
Input
P13
External event pulse input pin for timer/event counter.
PTO0
output
P20
PCL
Input/output
BUZ
After Reset
I/O Circuit
Type *1
—
B -C
Timer/event counter output pin
Input
E-B
P22
Clock output pin
Input
E-B
Input/output
P23
Fixed frequency output pin (for buzzer or system clock
trimming)
Input
E-B
SCK
Input/output
P01
Serial clock input/output pin
Input
F -A
SO/SB0
Input/output
P02
Serial data output pin
Serial bus input/output pin
Input
F -B
SI/SB1
Input/output
P03
Serial data input pin
Serial bus input/output pin
Input
M-C
INT4
Input
P00
Edge-detected vectored interrupt input pin (rising or falling
edge detection).
—
B
Edge-detected vectored interrupt input pin (detection edge
selectable)
—
B -C
Edge-detected testable input pin (rising edge detection)
—
B -C
Pin Name
INT0
Input
INT1
P10
P11
Function
INT2
Input
P12
KR0 to KR3
Input/output
P60 to P63
Testable Input/output pins (parallel falling edge detection)
Input
F -A
KR4 to KR7
Input/output
P70 to P73
Testable Input/output pins (parallel falling edge detection)
Input
F -A
S0 to S23
Output
—
Segment signal output pins
*3
G-A
S24 to S31
Output
BP0 to 7
Segment signal output pins
*3
G-C
COM0 to COM3
Output
—
Common signal output pins
*3
G-B
VLC0 to VLC2
—
—
LCD drive power supply pins
—
—
BIAS
—
—
External split cutting output pin
High impedance
—
LCDCL*2
Input/output
P30
External extension driver drive clock output pin
Input
E-B
SYNC*2
Input/output
P31
External extension driver synchronization clock output pin
Input
E-B
X1, X2
Input
—
Main system clock oscillation crystal/ceramic connection
pins. When an external clock is used, the clock is input to
X1 and the inverted clock to X2.
—
—
XT1, XT2
Input
—
Subsystem clock oscillation crystal connection pins
When an external clock is used, the clock is input to XT1 and
the inverted clock to XT2. XT1 can be used as a 1-bit input
(test) pin.
—
—
RESET
Input
—
System reset input pin (low-level active).
—
B
MD0 to MD3
Input/output
P30 to P33
Mode selection pin for program memory (PROM) write/
verify.
Input
E-B
VPP
—
—
Program voltage application pin for program memory (PROM)
write/verify . Connected to VDD in normal operation. Applies
+12.5 V in program memory write/verify.
—
—
VDD
—
—
Positive power supply pin
—
—
VSS
—
—
GND potential pin
—
—
7
µPD75P316A
*
1.
: Indicates a Schmitt-triggered input.
2. Pins provided for future system expansion. Currently used only as pins 30 and 31.
3. VLCX shown below can be selected for display outputs.
S0 to S31: VLC1, COM0 to COM2: VLC2 , COM3: VLC0
However, display output levels depend on the display output and VLCX external circuit.
8
µPD75P316A
1.3 PIN INPUT/OUTPUT CIRCUITS
The input/output circuits of each pin of the µPD75P316A are shown by in abbreviated form.
TYPE A (For TYPE E-B)
TYPE D (For TYPE E-B, F-A)
VDD
VDD
data
P-ch
OUT
P-ch
IN
N-ch
CMOS standard input buffer
TYPE B
output
disable
N-ch
Push-pull output that can be made high-impedance
output (P-ch and N-ch OFF)
TYPE E-B
VDD
P.U.R.
P.U.R.
enable
IN
P-ch
data
IN/OUT
Type D
output
disable
Type A
P.U.R.:Pull-Up Resistor
Schmitt trigger input with hysteresis characteristic
TYPE B-C
TYPE F-A
VDD
VDD
P.U.R.
P.U.R.
P-ch
P.U.R.
enable
P-ch
P.U.R.
enable
data
IN/OUT
Type D
output
disable
IN
P.U.R. : Pull-Up Resistor
Schmitt trigger input with hysteresis characteristic
Type B
P.U.R.:Pull-Up Resistor
9
µPD75P316A
TYPE F-B
TYPE G-C
VDD
P.U.R.
P.U.R.
enable
VDD
P-ch
P-ch
VDD
output
disable
(P)
VLC0
P-ch
VLC1
IN/OUT
P-ch
data
output
disable
SEG
data/Bit Port data
N-ch
output
disable
(N)
OUT
N-ch
VLC2
N-ch
P.U.R.:Pull-Up Resistor
TYPE G-A
TYPE M-A
IN/OUT
VLC0
P-ch
data
N-ch
(+10 V
Withstand
Voltage)
VLC1
output
disable
P-ch
SEG
data
OUT
N-ch
VLC2
N-ch
Middle-High Voltage Input Buffer
(+10 V Withstand Voltage)
TYPE G-B
TYPE M-C
VDD
VLC0
P-ch
P.U.R.
VLC1
P.U.R.
enable
P-ch
P-ch N-ch
IN/OUT
OUT
COM
data
N-ch
P-ch
data
N-ch
output
disable
VLC2
N-ch
P.U.R.:Pull-Up Resistor
10
µPD75P316A
1.4 CAUTION ON USING P00/INT4 PIN AND RESET PIN
The P00/INT4 and RESET pins have a test mode setting function (IC test only) which tests internal operations of
the µPD75P316A in addition to those functions given in 1.1 and 1.2.
The test mode is set when voltage greater than VDD is applied to either pin. Therefore, even during normal
operation, the test mode is engaged when noise greater than VDD is added, thus causing interference with normal
operation.
For example, this problem may occure if the P00/INT4 and RESET pins wiring is too long, causing line noise.
To avoid this, try to suppress line noise in wiring. If line noise is still high, try elimminating the noise using the
exterior add-on components shown in the Figures below.
• Connect a diode with low VF between the VDD
and the pin.
• Connect a condenser between the VDD and the pin.
VDD
Diode with
Small VF
VDD
VDD
VDD
P00/INT4, RESET
P00/INT4, RESET
2. DIFFERENCES BETWEEN PRODUCTS IN SERIES
The µPD75P316A is a product of the µPD75316 with on-chip mask ROM having been replaced with the one-time
PROM or EPROM. If you use PROM for debugging the applied system or trial manufacturing, and proceed to use
masked ROM products for mass production, do so only with a full understanding of their differences beforehand.
Also, µPD75P316A functions are an extension of those of the µPD75P316. Table 2-1 shows the differences between
the series products. All products have the same functions except as indicated in this table.
For the details of the CPU functions and the built-in hardware, please refer to the µPD75308 User's Manual (IEM5016).
11
★
12
Table 2-1 Differences between Products in Series
Product Name
Comparison Item
ROM(× 8 bits)
µPD75304/75306/75308
Mask ROM
4K/6K/8K
µPD75312/75316
Mask ROM
12K/16K
RAM(× 4 bits)
Mask ROM
12K/16K
1024
µPD75P308
µPD75P316
One-time PROM,EPROM
8K
One-time PROM
16K
µPD75P316A
µPD75P316B*1
One-time PROM,EPROM
16K
512
One-time PROM
16K
1024
Port 4, 5 pull-up resistor incorporated
LCD driving power supplying split resistor
No. 50 to 53
Pin
connection
No. 57
Electrical specifications
Mask ROM
4K/6K/8K
512
Mask option
★
µPD75304B/75306B/75308B µ PD75312B/75316B
No
P30 to P33
P30/MD0 to P33/MD3
NC
IC
VPP
Masked ROM products and PROM products have different current dissipation and operating temperature range *2. For details, refer to the electrical specifications of
respective data sheet.
Power supply voltage range
2.7 to 6.0 V
Operating temperature
range
2.0 to 6.0 V
2.0 to 5.5 V
–40 to +85 °C
• 80-pin plastic QFP (14 × 20)
Package
µPD75P316
µPD75P316A
• 80-pin plastic QFP
QFP (■
■ 14)
• 80-pin plastic QFP
(14 × 20)
• 80-pin plastic TQFP
(■
■ 12)
µPD75P316A
µPD75P316B
• 80-pin plastic
QFP (■
■ 14)
• 80-pin plastic
TQFP (■
■ 12)
2.7 to 6.0 V
2.0 to 5.5 V
–10 to +70 °C
–40 to +85 °C
Under
investigation
• 80-pin plastic
QFP (14 × 20)
• 80-pin ceramic
WQFN (LCC with
window)
• 80-pin plastic
QFP (14 × 20)
• 80-pin plastic
QFP (14 × 20)
• 80-pin ceramic
WQFN (LCC with
window)
• 80 pin plastic
QFP (■
■ 14)
• 80 pin plastic
TQFP (■
■ 12)
★
On-chip PROM product
µPD75P308
★
Others
Masked ROM products and PROM products have different noise endurance limits and noise radiation due to differing circuit scales and mask layouts.
*
µPD75P316B
5 V ±5 %
––––
1. The µPD75P316B is under development.
2. The µPD75P316A is the same as the mask ROM products.
★
Note
PROM and masked ROM have different noise endurance limits and noise radiation. When considering replacement of masked ROM products after trial manufacturing
with PROM products, sufficient evaluation of CS products (not ES products) with masked ROM products should be performed.
µPD75P316
µPD75P316A
3. DATA MEMORY (RAM)
Fig. 3-1 shows the data memory configuration. It consists of a data area and a peripheral hardware area.
The data memory consists of memory banks 0 to 3 with each bank consisting of 256 words × 4 bits.
Peripheral hardware has been assigned to the area of memory bank 15.
(1) Data area
The data area comprises a static RAM. It is used to store program data and as a subroutine, interrupt execution
stack memory. Even if the CPU operation is stopped in the standby mode, it is possible to hold the memory content
for a long time by battery backup, etc. The data area is operated by memory manipulation instructions.
The static RAM has been mapped to memory banks 0, 1, 2 and 3 by 256 × 4 bits each. Bank 0 has been mapped
as a data area but is also available as a general register area (000H to 007H) and a stack area (000H to 0FFH) (banks
1, 2 and 3 are available only as a data area).
In the static RAM, 1 address consists of 4 bits. It can be operated in units of 8 bits by 8-bit memory manipulation
instructions or in bits by bit manipulation instructions, however. In an 8-bit manipulation instruction, an even
address should be specified.
(a) General register area
The general register area can be operated either by general register operation instructions or by memory
manipulation instructions. Up to eight 4-bit registers are available. That part of the 8 general registers which
is not used in the program is available as a data area or a stack area.
(b) Stack area
The stack area is set by an instruction. It is available as a subroutine execution or interrupt service execution
save area.
(2) Peripheral hardware area
The peripheral hardware area has been mapped to F80H to FFFH of memory bank 15.
It is operated by memory manipulation instructions just as the static RAM. In the peripheral hardware, however,
the operable bit unit differs from one address to another. An address to which peripheral hardware has not been
assigned is inaccessible since no data memory is built in.
13
µPD75P316A
µPD78012
Fig. 3-1 Data Memory Map
Data Memory
General
Register Area
Memory Bank
000H
(8 × 4)
007H
Stack
Area
008H
0
256 × 4
0FFH
100H
Data Area
Static RAM
(1024 × 4)
256 × 4
1
256 × 4
2
256 × 4
3
1FFH
200H
2FFH
300H
3FFH
Not On-Chip
F80H
128 × 4
Peripheral Hardware Area
FFFH
14
15
µPD75P316A
4. PROGRAM MEMORY WRITE AND VERIFY
The ROM built into the µPD75P316A is a 16256 × 8-bit electrically writable one-time PROM. The table below shows
the pins used to program this PROM. There is no address input; instead, a method to update the address by the
clock input via the X1 pin is adopted.
Pin Name
Function
VPP
Voltage applecation pin for program memory write/verify
(normally VDD potential).
X1, X2
Address update clock inputs for program memory write/
verify. Inverse of X1 pin signal is input to X2 pin.
MD0 to MD3
Operating mode selection pins for program memory write/
verify.
P40 to P43 (low-order 4 bits) 8-bit data input/output pins for progrm memory write/
P50 to P53 (high-order 4 bits) verify.
Supply voltage application pin.
Applies 2.7 to 6.0 V in normal operation, and 6 V for
program memory write/verify.
VDD
Note
1. A lightshield cover film should be applied to the µPD75P316AK provided
with an erasure window, except when erasing the EPROM.
2. The one-time PROM version of µ PD75P316AGF is not provided with an
erasure window, and therefore UV erasure is not possible.
4.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES
The µPD75P316A assumes the program memory write/verify mode when +6 V and +12.5 V are applied
respectively to the VDD and VPP pins. The table below shows the operating modes available by the MD0 to MD3 pin
setting in this mode. All the remaining pins are at the VSS potential by the pull-down resistor.
Operating Mode Setting
Operating Mode
VPP
+12.5 V
VDD
MD0
MD1
MD2
MD3
H
L
H
L
Program memory address zero-clear
L
H
H
H
Write mode
L
L
H
H
Verify mode
H
×
H
H
Program inhibit mode
+6 V
×: L or H
15
µPD75P316A
µPD78012
4.2 PROGRAM MEMORY WRITING PROCEDURE
The program memory writing procedure is shown below. High-speed write is possible.
(1) Pull down a pin which is not used to VSS via the resistor. The X1 pin is at the low level.
(2)
(3)
(4)
(5)
Supply 5 V to the VDD and VPP pins.
10 µs wait.
The program memory address 0 clear mode.
Supply 6 V and 12.5 V respectively to VDD and VPP.
(6)
(7)
(8)
(9)
The program inhibit mode.
Write data in the 1-ms write mode.
The program inhibit mode.
The verify mode. If written, proceed to (10); if not written, repeat (7) to (9).
(10)
(11)
(12)
(13)
(Number of times written in (7) to (9): X) × 1-ms additional write.
The program inhibit mode.
Update (+1) the program memory address by inputting 4 pulses to the X1 pin.
Repeat (7) to (12) up to the last address.
(14) The program memory address 0 clear mode.
(15) Change the VDD and VPP pins voltage to 5 V.
(16) Power off.
The diagram below shows the procedure of the above (2) to (12).
Repeated X Times
Write
Verify
Additional
Write
VPP
VPP
VDD
VDD + 1
VDD
VDD
X1
P40-P43
P50-P53
MD0
(P30)
MD1
(P31)
MD2
(P32)
MD3
(P33)
16
Data Input
Data Output
Data Input
Address
Increment
µPD75P316A
4.3 PROGRAM MEMORY READING PROCEDURE
The µPD75P316A can read the content of the program memory in the following procedure. It reads in the verify
mode.
(1)
(2)
(3)
(4)
Pull down a pin which is not used to VSS via the resistor. The X1 pin is at the low level.
Supply 5 V to the VDD and VPP pins.
10 µs wait.
The program memory address 0 clear mode.
(5) Supply 6 V and 12.5 V respectively to VDD and VPP.
(6) The program inhibit mode.
(7) The verify mode. If clock pulses are input to the X1 pin, data is output sequentially 1 address at a time at
the period of inputting 4 pulses.
(8)
(9)
(10)
(11)
The program inhibit mode.
The program memory address 0 clear mode.
Change the VDD and VPP pins voltage to 5 V.
Power off.
The diagram below shows the procedure of the above (2) to (9).
VPP
VPP
VDD
VDD + 1
VDD
VDD
X1
P40-P43
P50-P53
Data Output
Data Output
MD0
(P30)
MD1
(P31)
"L"
MD2
(P32)
MD3
(P33)
17
µPD75P316A
µPD78012
4.4 ERASING METHOD (µPD75P316AK ONLY)
The content of the data programmed in the µPD75P316A is erased as ultraviolet rays are irradiated to the window
in the upper part.
The erasable ultraviolet-ray wavelength is about 250 nm.
The dose required for complete erasure is 15 W•s/cm2 (ultraviolet-ray intensity × erasure time). If a commercially
available ultraviolet-ray lamp (wavelength 254 nm, intensity 12 mW/cm2) is used, it takes about 15 to 20 minutes
to erase.
Note
1. The content may be erased if exposed to direct sunlight or fluorescent lamp light for a long time. To
protect the content, the window in the upper part should be masked with a lightshield cover film.
NEC attaches such a lightshield cover film to each UV EPROM product.
2. When erasing, the distance between the ultraviolet-ray lamp and the µ PD75P316A should be kept
normally within 2.5 cm.
Remarks
18
It may take longer to erase if the ultraviolet-ray lamp has deteriorated or if the package window is dirty
and so on.
µPD75P316A
5. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C)
PARAMETER
TEST CONDITIONS
SYMBOL
Input voltage
V
VPP
–0.3 to +13.5
V
VI1
Except ports 4, 5
–0.3 to VDD +0.3
V
VI2
Ports 4, 5
–0.3 to +11
V
–0.3 to VDD +0.3
V
Output voltage
VO
Output current high
IOH
Open-drain
1 pin
–15
mA
All pins
–30
mA
Peak value
30
mA
Effective value
15
mA
100
mA
60
mA
100
mA
60
mA
1 pin
Output current low
Peak value
IOL*
Total of ports 0, 2, 3, 5
Total of ports 4, 6, 7
*
UNIT
–0.3 to +7.0
VDD
Power supply voltage
RATING
Effective value
Peak value
Effective value
Operating temperature
Topt
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Calculate the effective value with the formula [Effective value] = [Peak value] × √duty.
CAPACITANCE (Ta = 25 °C, VDD = 0 V)
PARAMETER
Input capacitance
Output capacitance
Input /output
capacitance
SYMBOL
TEST CONDITIONS
CIN
COUT
CIO
f = 1 MHz
Unmeasured pin returned to 0 V
MIN.
TYP.
MAX.
UNIT
15
pF
15
pF
15
pF
19
µPD75P316A
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
RESONATOR RECOMMENDED CIRCUIT
X1
Ceramic
resonator
C2
Oscillation stabilization
time *2
VDD
X1
TEST CONDITIONS
Oscillator frequency
(fX) *1
X2
C1
PARAMETER
Crystal
resonator
TYP.
1.0
After VDD reaches the
minimum value in the
oscillation voltage
range
Oscillator frequency
(fX) *1
X2
MIN.
1.0
4.19
VDD = 4.5 to 6.0 V
C1
C2
Oscillation stabilization
time *2
VDD
X1
X2
External
clock
µPD74HCU04
*
MAX.
UNIT
5.0*3
MHz
4
ms
5.0*3
MHz
10
ms
30
ms
X1 input frequency
(fX) *1
1.0
5.0*3
MHz
X1 high and low level
widths (tXH, tXL)
100
500
ns
1. Oscillator characteristics only. Refer to the description of AC characteristics for details of instruction execution
time.
2. Time required for oscillation to become stabilized after VDD reaches MIN. of the oscillation voltage range or
after STOP mode release.
3. When the oscillator frequency is 4.19 MHz < fX ≤ 5.0 MHz, do not select PPC = 0011 as instruction execution
time. If PCC = 0011 is selected, 1 machine cycle becomes less than 0.95 µs, with the result that specified MIN.
value 0.95 µs can not be observed.
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V)
RESONATOR RECOMMENDED CIRCUIT
XT1
R
C3
TEST CONDITIONS
Oscillator frequency
(fXT)
XT2
Crystal
resonator
PARAMETER
C4
MIN.
TYP.
MAX.
UNIT
32
32.768
35
kHz
1.0
2
s
10
s
VDD = 4.5 to 6.0 V
Oscillation stabilization
time*
VDD
X1
X2
XT1 input frequency
(fXT)
32
100
kHz
XT1 high and low level
widths (tXTH, tXTL )
5
15
µs
External
clock
20
µPD75P316A
*
Time required for oscillation to become stabilized after VDD reaches MIN. of the oscillation voltage range or after
STOP made release.
Note
When the main system clock and subsystem clock oscillation circuit are used, the area enclosed by dotted
line in the figure should be wired as follows to prevent influence from the wiring capacitance, etc..
• Wiring should be as short as possible.
• Do not cross other signal lines.
Do not place the circuit closed to a line in which varying high current flows.
• The connecting point of oscillation circuit capacitor should always be the same potential as VDD. Do
not connect it to the power supply pattern in which high current flows.
• Do not pick up a signal from the oscillation circuit.
The subsystem clock oscillation circuit is designed to be low amplification circuit for low dissipation
current, thus misoperation due to noise occurs more often than with the main system clock oscillation
circuit. Therefore, when the subsystem clock is used, care is needed especially for the wiring procedure.
21
µPD75P316A
DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) (1/2)
PARAMETER
Input voltage
high
Input voltage
low
SYMBOL
TEST CONDITIONS
UNIT
0.7 VDD
VDD
V
VIH2
Ports 0, 1, 6, 7, RESET
0.8 VDD
VDD
V
VIH3
Ports 4 and 5
0.7 VDD
10
V
VI H4
X1, X2, XT1
VDD –0.5
VDD
V
VIL1
Ports 2, 3, 4 and 5
0
0.3 VDD
V
VIL2
Ports 0, 1, 6, 7, RESET
0
0.2 VDD
V
VIL3
X1, X2, XT1
0
0.4
V
VOH1
Ports
0, 2, 3, 6, 7,
BIAS
BP0 to BP7
(with 2 IOH
outputs)
Ports
0, 2, 3, 4, 5, 6
and 7
VOL1
Output voltage
low
SB0, 1
VOL2
BP0 to BP7 (with 2
IOL outputs)
ILIH1
VIN = VDD
ILIH2
ILIH3
VIN = 10 V
ILIL1
VIN = 0 V
ILIL2
22
MAX.
Ports 2 and 3
V0H2
Input leakage
current low
TYP.
VIH1
Output voltage
high
Input leakage
current high
MIN.
Open-drain
VDD = 4.5 to
6.0 V
IOH = –1 mA
VDD –1.0
V
IOH = -100 µA
VDD –0.5
V
VDD = 4.5 to
6.0 V
IOH = –100 µA
VDD –2.0
V
IOH = –30 µA
VDD –1.0
V
Ports 3, 4 and 5
VDD = 4.5 to
6.0 V
IOL = 15 mA
0.4
2.0
V
VDD = 4.5 to
6.0 V
IOL = 1.6 mA
0.4
V
IOL = 400 µA
0.5
V
0.2 VDD
V
Open-drain
pull-up
resistor ≥ 1 kΩ
VDD = 4.5 to
6.0 V
IOL = 100 µA
1.0
V
IOL = 50 µA
1.0
V
Other than
below
3
µA
X1, X2, XT1
20
µA
Ports 4 and 5
(when opendrain)
20
µA
Other than
below
-3
µA
X1, X2, XT1
-20
µA
µPD75P316A
DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 2.7 to 6.0 V) (1/2)
PARAMETER
SYMBOL
TEST CONDITIONS
On-chip pull-up
resistor
TYP.
MAX.
UNIT
ILOH1
VOUT = VDD
Other than
below
3
µA
ILOH2
VOUT = 10 V
Ports 4 and 5
(when opendrain)
20
µA
ILOL
VOUT = 0 V
–3
µA
80
kΩ
RL1
Ports 0, 1, 2, 3, 6
and 7 (Except P00)
VIN = 0 V
Output leakage
current high
Output leakage
current low
MIN.
LCD drive voltage
VLCD
LCD output
voltage
deviation*1
(common)
VODC
IO = ±5 µA
LCD output
voltage
deviation*1
(segment)
VODC
IO = ±5µA
VDD = 5.0 V
±10%
15
VDD = 3.0 V
±10%
30
300
kΩ
2.5
VDD
V
0
±0.2
V
0
±0.2
V
VLCD0 = VLCD
VLCD1 =
VLCD × 2/3
VLCD2 = VLCD
× 1/3
2.7 V ≤ VLCD
≤ V DD
40
VDD = 5 V
±10%*4
4.5
14
mA
VDD = 3 V
±10%*5
0.9
3
mA
IDD1
4.19 MHz*3 crystal
oscillation C1=C2
22 pF
HALT
mode
VDD =
5V
±10%
700
2100
µA
VDD =
3V
±10%
300
900
µA
Operating
mode
VDD =
3V
±10%
100
300
µA
HALT
mode
VDD =
3V
±10%
20
60
µA
0.5
20
µA
0.1
10
µA
0.1
5
µA
5
15
µA
IDD2
Supply current*2
IDD3
32 kHz*6
crystal oscillation
IDD4
VDD = 5 V±10%
IDD5
XT1 =
0 V STOP mode
VDD =
3 V±10%
Ta = 25°C
IDD6
32 kHz
crystal oscillation
STOP mode
VDD = 3 V ±10%*7
23
µPD75P316A
*
24
1. The voltage deviation is a difference between the segment and common output ideal value (VLCDn; n = 0, 1,
2) and output voltage.
2. Current flowing in the internal pull-up resistor and LCD split resistor are not included.
3. Includes when the subsystem clock is oscillated.
4. When the processor clock control register (PCC) is set to 0011 and operated in high-speed mode.
5. When the PCC is set to 0000 and operated in low-speed mode.
6. When operated by the subsystem clock with the system clock control register (SCC) set to 1011 and the main
system clock stops.
7. When the STOP instruction is executed during the main system clock operation and the subsystem clock is
oscillated.
µPD75P316A
AC CHARACTERISTICS (Ta = –40 to +85 °C , VDD = 2.7 to 6.0 V)
PARAMETER
SYMBOL
tCY
TI0 input frequency
fTI
TI0 input high and lowlevel widths
tTIH,
Interrupt input high and
low-level widths
tINTH,
* 1.
TYP.
MAX.
UNIT
0.95
64
µs
3.8
64
µs
125
µs
Operation with
subsystem clock
114
VDD = 4.5 to 6.0 V
0
1
MHZ
0
275
kHz
122
0.48
µs
1.8
µs
INT0
*2
µs
INT1, 2, 4
10
µs
KR0–7
10
µs
10
µs
VDD = 4.5 to 6.0 V
tTIL
tINTL
tRSL
tCY
CPU clock (Φ) cycle time is determined by oscillator
frequency of the connected resonator, system clock
VS VDD
(Main System Clock in Operation)
70
control register (SCC) and processor clock control
register (PCC). Characteristics for power supply
voltage VDD vs • cycle time tCY in main system clock
operation is shown below.
64
30
6
5
It becomes 2tCY or 128/fX by interrupt mode register
(IM0) setting.
4
Cycle Time tCY [µs]
2.
MIN.
VDD = 4.5 to 6.0 V
Operation with main
system clock
CPU clock cycle time
(minimum instruction
execution time = 1
machine cycle )*1
RESET low-level width
TEST CONDITIONS
3
2
1
0.5
0
1
2
3
4
5
6
Power Supply Voltage VDD [V]
25
µPD75P316A
Serial Transfer Operation
2-wire and 3-wire serial I/O mode (SCK...Internal clock output)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
VDD = 4.5 to 6.0 V
SCK cycle time
TYP.
MAX.
UNIT
1600
ns
3800
ns
tKCY1/2–50
ns
tKCY1
tKL1
VDD = 4.5 to 6.0 V
SCK high and low level
widths
tKH1
tKCY1/2–150
ns
SI setup time (to SCK↑)
tSIK1
150
ns
SI hold time (from SCK↑)
tKSI1
400
ns
SO output delay time
from SCK↓
tKSO1
*
RL = 1 k Ω, CL = 100 pF*
VDD = 4.5 to 6.0 V
250
ns
1000
ns
RL and CL are SO output line load resistance and load capacitance, respectively.
2-wire and 3-wire serial I/O mode (SCK...External clock input)
PARAMETER
SYMBOL
TEST CONDITIONS
VDD = 4.5 to 6.0 V
SCK cycle time
MIN.
TYP.
MAX.
UNIT
800
ns
3200
ns
400
ns
tKCY2
tKL2
VDD = 4.5 to 6.0 V
SCK high and low level
widths
tKH2
1600
ns
SI setup time (to SCK↑)
tSIK2
100
ns
SI hold time (from SCK↑)
tKSI2
400
ns
SO output delay time
from SCK↓
tKSO2
*
26
RL = 1 k Ω, CL = 100 pF*
VDD = 4.5 to 6.0 V
RL and CL are SO output line load resistance and load capacitance, respectively.
300
ns
1000
ns
µPD75P316A
SBI mode (SCK...Internal clock output (master))
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
VDD = 4.5 to 6.0 V
SCK cycle time
TYP.
MAX.
UNIT
1600
ns
3800
ns
tKCY3/2–50
ns
tKCY3
tKL3
VDD = 4.5 to 6.0 V
SCK high and low level
widths
tKH3
t KCY3/2–150
ns
SB0 and SB1 setup time (to SCK↑)
tSIK3
150
ns
SB0 and SB1 hold time (from SCK↑)
tKSI3
tKCY3/2
ns
SB0 and SB1 output
delay time from SCK↓
tKSO3
SB0, SB1↓ from SCK↑
tKSB
tKCY3
ns
SCK from SB0, SB1↓
tSBK
tKCY3
ns
SB0 and SB1 low-level widths
tSBL
tKCY3
ns
SB0 and SB1 high-level widths
tSBH
tKCY3
ns
*
RL = 1 k Ω, CL = 100 pF*
VDD = 4.5 to 6.0 V
0
250
ns
0
1000
ns
RL and CL are SO output line load resistance and load capacitance, respectively.
SBI mode (SCK...External clock input (slave))
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
VDD = 4.5 to 6.0 V
SCK cycle time
TYP.
MAX.
UNIT
800
ns
3200
ns
400
ns
tKCY4
tKL4
VDD = 4.5 to 6.0 V
SCK high and low level
widths
tKH4
1600
ns
SB0 and SB1 setup time (to SCK↑)
tSIK4
100
ns
SB0 and SB1 hold time (from SCK↑)
tKSI4
tKCY3/2
ns
SB0 and SB1 output
delay time from SCK↓
tKSO4
SB0, SB1↓ from SCK↑
tKSB
tKCY4
ns
SCK from SB0, SB1↓
tSBK
tKCY4
ns
SB0 and SB1 low-level widths
tSBL
tKCY4
ns
SB0 and SB1 high-level widths
tSBH
tKCY4
ns
*
RL = 1 k Ω, CL = 100 pF*
VDD = 4.5 to 6.0 V
0
300
ns
0
1000
ns
RL and CL are SO output line load resistance and load capacitance, respectively.
27
µPD75P316A
AC Timing Test Points (Except X1 and XT1 Inputs)
0.8 VDD
0.8 VDD
Test Points
0.2 VDD
0.2 VDD
Clock Timing
1/fX
tXL
tXH
X1 Input
V DD - 0.5 V
0.4 V
1/fXT
tXTL
tXTH
XT1 Input
VDD - 0.5 V
0.4 V
TI0 Timing
1/fT1
tTIL
TI0
28
tTIH
µPD75P316A
Serial Transfer Timing
3-wire serial I/O mode:
tKCY1
tKH1
tKL1
SCK
tSIK1
SI
tKSI1
Input Data
tKSO1
SO
Output Data
2-wire serial I/O mode:
tKCY2
tKL2
tKH2
SCK
tSIK2
tKS12
SB0,1
tKSO2
29
µPD75P316A
Serial Transfer Timing
Bus release signal transfer:
tKCY3,4
tKL3,4
tKH3,4
SCK
tSBL
tKSB
tSBH
tSIK3,4
tSBK
SB0,1
tKSO3,4
Command signal transfer:
tKCY3,4
tKL3,4
tKH3,4
SCK
tKSB
tSIK3,4
tSBK
SB0,1
tKSO3,4
Interrupt Input Timing
tINTL
INT0,1,2,4
KR0-7
RESET Input Timing
tRSL
RESET
30
tINTH
tKSI3,4
tKSI3,4
µPD75P316A
DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40
to +85 °C)
PARAMETER
SYMBOL
Data retention power supply voltage
VDDDR
Data retention power supply current *1
IDDDR
Release signal set time
tSREL
3.
MIN.
TYP.
2.0
VDDDR = 2.0 V
0.1
MAX.
UNIT
6.0
V
10
µA
µs
0
Release by RESET
Oscillation stabilization wait
time *2
* 1.
2.
TEST CONDITIONS
17
2 /fX
ms
*3
ms
tWAIT
Release by interrupt request
Current to the internal pull-up resistor is not included.
Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation
start.
According to the setting of the basic interval timer mode register (BTM) (see below).
Wait Time
BTM3
BTM2
BTM1
BTM0
(Values at fXX = 4.19 MHz in parentheses)
—
0
0
0
220/fXX (approx. 250 ms)
—
0
1
1
217/fXX (approx. 31.3 ms)
—
1
0
1
215/fXX (approx. 7.82 ms)
—
1
1
1
213/fXX (approx. 1.95 ms)
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
31
µPD75P316A
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
DC PROGRAMMING CHARACTERISTICS (Ta = –25 to ±5 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V, VSS = 0 V)
PARAMETER
TEST CONDITIONS
SYMBOL
MIN.
TYP.
MAX.
UNIT
VIH1
Except X1, X2
0.7 VDD
VDD
V
VIH2
X1, X2
VDD –0.5
VDD
V
VIL1
Except X1, X2
0
0.3 VDD
V
VIL2
X1, X2
0
0.4
V
10
µA
Input voltage high
Input voltage low
Input leakage current
ILI
Output voltage high
VOH
IOH = –1mA
Output voltage low
VOL
IOL = 1.6 mA
VDD power supply current
IDD
VPP power supply current
IPP
Note
32
VIN = VIL or VIH
MD0 = VIL, MD1 = VIH
1. VPP including overshoot should not exceed +13.5 V.
2. VDD should be applied before VPP and should be cut after VPP.
VDD –1.0
V
0.4
V
30
mA
30
mA
µPD75P316A
AC PROGRAMMING CHARACTERISTICS (Ta = 25 to ±5 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V, VSS = 0 V)
PARAMETER
*1
Address setup time*2 (to MD0 ↓)
tAS
tAS
2
µs
MD1 setup time (to MD0 ↓)
tM1S
tOES
2
µs
Data setup time (to MD0 ↓)
tDS
tDS
2
µs
Address hold time*2 (from MD0 ↑)
tAH
tAH
2
µs
Data hold time (to MD0 ↑)
tDH
tDH
2
µs
Data output float delay time from MD0 ↑
tDF
tDF
0
VPP setup time (to MD3 ↑)
tVPS
tVPS
2
µs
VDD setup time (to MD3 ↑)
tVDS
tVCS
2
µs
Initial program pulse width
tPW
tPW
0.95
Additional program pulse width
tOPW
tOPW
0.95
MD1 setup time (to MD1 ↑)
tMOS
tCES
2
Data output delay time from MD0 ↓
tDV
tDV
MD1 hold time (from MD0 ↑)
tM1H
tOEH
MIN.
TYP.
MAX.
MD1 recovery time (from MD0 ↓)
tM1R
tOR
Program counter reset time
tPCR
130
1.0
ns
1.05
ms
21.0
ms
µs
1
MD0 = MD1 = VIL
UNIT
µs
2
µs
2
µs
–
10
µs
tXH, tXL
–
0.125
µs
X1 input frequency
fX
–
Initial mode set time
tI
–
2
µs
MD3 setup time (to MD1 ↑)
tM3S
–
2
µs
MD3 hold time (from MD1 ↓)
tM3H
–
2
µs
MD3 setup time (to MD0 ↓)
tM3SR
–
When reading program memory
2
µs
Data output delay time from address*2
tDAD
tACC
When reading program memory
Data output hold time from address*2
tHAD
tOH
When reading program memory
0
MD3 hold time (from MD0 ↑)
tM3HR
–
When reading program memory
2
Data output float delay time from MD3 ↓
tDFR
–
When reading program memory
X1 input high/low level width
*
TEST CONDITIONS
SYMBOL
tM1H + tM1R ≥ 50 µs
4.19
MHz
2
µs
130
ns
µs
2
µs
1. Symbol of the corresponding µPD27C256A.
2. The internal address signal is incremented (+1) at the rising edge of the fourth X1 input. The signal is not
connected to pins.
33
µPD75P316A
Program Memory Write Timing
tVPS
VPP
VPP
VDD
VDD
VDD + 1
VDD
tVDS
tXH
X1
tXL
P40 – P43
P50 –P53
Data Input
Data Output
tDS
tI
tOH
tDV
tDF
Data Input
Data Input
tDH
tAH
tDS
tAS
MD0
tMOS
tM1R
tPW
tOPW
MD1
tPCR
tM1S
tM1H
MD2
tM3H
tM3S
MD3
Program Memory Read Timing
tVPS
VPP
VPP
VDD
tVDS
VDD
VDD + 1
VDD
tXH
X1
tXL
tDAD
tHAD
P40 – P43
P50 –P53
Data Output
tM3HR
MD0
MD1
tPCR
MD2
tM3SR
34
tDFR
tDV
tI
MD3
Data Output
µPD75P316A
6. PACKAGE INFORMATION
80 PIN PLASTIC QFP (14×20)
A
B
41
40
64
65
F
Q
5°±5°
S
D
C
detail of lead end
25
24
80
1
G
H
I M
J
M
P
K
N
L
P80GF-80-3B9-2
NOTE
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
23.6 ± 0.4
0.929 ± 0.016
B
20.0 ± 0.2
0.795 +0.009
–0.008
C
14.0 ± 0.2
0.551+0.009
–0.008
D
17.6 ± 0.4
0.693 ± 0.016
F
1.0
0.039
G
0.8
0.031
H
0.35 ± 0.10
0.014 +0.004
–0.005
0.006
I
0.15
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8 ± 0.2
0.071 –0.009
L
0.8 ± 0.2
0.031+0.009
–0.008
M
0.15+0.10
–0.05
0.006+0.004
–0.003
N
0.15
0.006
P
2.7
Q
0.1 ± 0.1
S
3.0 MAX.
+0.008
0.106
0.004 ± 0.004
0.119 MAX.
35
µPD75P316A
80 PIN CERAMIC WQFN
A
Q
K
C
D
B
T
W
S
80
I
H
U
1
M
E
F
G
J
X80KW-80A-1
NOTE
Each lead centerline is located within 0.08
mm (0.003 inch) of its true position (T.P.) at
maximum material condition.
36
ITEM
MILLIMETERS
INCHES
A
20.0 ± 0.4
0.787+0.017
–0.016
B
19.0
0.748
C
13.2
0.520
D
14.2 ± 0.4
0.559 ± 0.016
E
1.64
0.065
F
2.14
0.084
G
4.064 MAX.
0.160 MAX.
H
0.51 ± 0.10
0.020 ± 0.004
I
0.08
0.003
J
0.8 (T.P.)
0.031 (T.P.)
K
1.0 ± 0.2
0.039 –0.008
Q
C 0.5
C 0.020
R
0.8
0.031
S
1.1
0.043
T
R 3.0
R 0.118
U
12.0
0.472
W
0.75 ± 0.2
0.030 –0.009
+0.009
+0.008
R
µPD75P316A
7. RECOMMENDED SOLDERING CONDITIONS
The µPD75P316A should be soldered and mounted under the conditions recommended in the table below.
For detail of recommended soldering conditions, refer to the information document “Semiconductor Device
Mount Manual” (IEI-1207).
For soldering methods and conditions other than those recommended below, contact our salesman.
Table 7-1 Surface Mounting Type Soldering Conditions
µPD75P316AGF-3B9 : 80-pin plastic QFP (14 × 20 mm)
Solderring Method
*
Solderring Conditions
Recommended
Condition Symbol
Wave soldering
Solder bath temperature: 260 °C or below. , Duration: 10 sec. max.
Number of times: Once, Time limit: 7 days*(thereafter 20 hours prebaking required
at 125 °C)
WS60-207-1
Infrared reflow
Package peak temperature: 230 °C, Duration: 30 sec. max. (at 210 °C or above),
Number of times: Once, Time limit: 7 days*(thereafter 20 hours prebaking required
at 125 °C)
IR30-207-1
VPS
Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or above),
Number of times: Once, Time limit: 7 days* (thereafter 20 hours prebaking required
at 125 °C)
VP15-207-1
Pin part heating
Pin part temperature: 300 °C or below , Duration: 3 sec. max. (per device side)
–––
For the storage period after dry-pack decapsulation, storage conditions are max. 25 °C, 65 % RH.
Note
Use more than one soldering method should be avoided (except in the case of pin part heating).
For Your Information
Products to improve the recommended soldering conditions are available.
(Improvements : Extension of the infrared reflow peak temperature to 235 °C, doubled frequency, increased
life, etc.)
For further details, consult our sales personnel.
37
µPD75P316A
APPENDIX A. DEVELOPMENT TOOLS
Software
Hardware
The following development tools are available for system development using the µPD75P316A.
*
IE-75000-R*1
IE-75001-R
In-circuit emulator for use with the 75X series
IE-75000-R-EM*2
Emulation board for use with the IE-75000-R and the IE-75001-R
EP-75308GF-R
Emulation probe for use with the µPD75P308GF 80-pin conversion socket EV-9200G-80
included
EV-9200G-80
PG-1500
PROM programmer
PA-75P308GF
Connect to PG-1500 with PROM programmer adapter for use with the µPD75P308GF
PA-75P308K
Connect to PG-1500 with PROM programmer adapter for use wtih the µPD75P308K
IE-control program
PG-1500 controller
RA75X relocatable assembler
1. Maintenance product
2. Not a built-in component in the IE-75001-R
3. Ver. 5.00/5.00A has a task swaping function, which cannot be used with this software.
Remarks
38
Host machine
• PC-9800 series (MS-DOS Ver. 3.30 to Ver.5.00A *3)
• IBM PC/AT (PC DOS Ver. 3.1)
Refer to the 75X Series Selection Guide (IF-151) for third-party development tools.
µPD75P316A
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name
Document Number
User's Manual
IEM-5016
Instruction Application Table
IEM-994
75X Series Selection Guide
IF-151
Development Tools Documents
Software
Hardware
Document Name
Document Number
IE-75000-R/IE-75001-R User's Manual
EEU-846
IE-75000-R-EM User's Manual
EEU-673
EP-75308GF-R User's Manual
EEU-689
PG-1500 User's Manual
EEU-651
Operation Volume
EEU-731
Language Volume
EEU-730
RA75X Assembler Package User's Manual
PG-1500 Controller User's Manual
EEU-704
Other Documents
Document Name
Document Number
Package Manual
IEI-635
Surface Mount Technology Manual
IEI-1207
Quality Grade on NEC Semiconductor Devices
IEI-1209
NEC Semiconductor Device Reliability & Quality Control
IEM-5068
Electrostatic Discharge (ESD) Test
MEM-539
Semiconductor Devices Quality Guide Guarantee Guide
MEI-603
Microcomputer Related Products Guide Other
Other Manufacturers Volume
MEI-604
Note
The information in these related documents is subject to change without notice. For design purpose, etc.,
check if your documents are the latest ones and be sure to use the latest ones.
39
µPD75P316A
40
µPD75P316A
41
µPD75P316A
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special
: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime systems, etc.
M4 92.6
MS-DOS is a trademark of MicroSoft Corporation.
PC DOS and PC/AT are trademarks of IBM Corporation.