Pr
E2B0055-19-61
el
im
ar
This version: Jun.
1999
ML9044
in
y
¡ Semiconductor
ML9044
¡ Semiconductor
DOT MATRIX LCD CONTROLLER DRIVER
GENERAL DESCRIPTION
The ML9044 used in combination with an 8–bit or 4–bit microcontroller controls the operation
of a character type dot matrix LCD.
FEATURES
• Easy interfacing with 8–bit or 4–bit microcontroller
• Switchable between serial and parallel interfaces
• Dot–matrix LCD controller/driver for a small (5 ¥ 7 dots) or large (5 ¥ 10 dots) font
• Built–in circuit allowing automatic resetting at power–on
• Built–in 17 common signal drivers and 120 segment signal drivers
• Built–in character generation ROM capable of generating 160 small characters (5 ¥ 7 dots) or
32 large characters (5 ¥ 10 dots)
• Creation of character patterns by programming: up to 8 small character patterns (5 ¥ 8 dots) or
up to 4 large character patterns (5 ¥ 11 dots)
• Built–in RC oscillation circuit using external or internal resistors
• Program–selectable duties: 1/9 duty (1 line: 5 ¥ 7 dots + cursor + arbitrator), 1/12 duty (1 line:
5 ¥ 10 dots + cursor + arbitrator), or 1/17 duty (2 lines: 5 ¥ 7 dots + cursor + arbitrator)
• Built–in bias dividing resistors to drive the LCD
• Bi–directional transfer of segment outputs
• Bi–directional transfer of common outputs
• Equipped with a 120–dot arbitrator
• Display shifting on each line
• Built–in contrast control circuit
• Built–in voltage multiplier circuit
• Chip (Gold Bump) Product name : ML9044CVWA
1/54
Timing
7
Instruction
decoder
(ID)
8
Character
5
generator
I/O
RAM
buffer
signal
register
driver
COM1
COM17
SEG1
(CGRAM)
5
4
8
Data
Character
8
register
generator
(DR)
4
ROM
Address
(ADC)
Busy flag
8
Expansion
LCD
Expansion
Instruction
register (ER)
bias
dividing
circuit
Display
data RAM
(BF)
voltage
(CGROM)
counter
Test
circuit
8
8
(DDRAM)
5
Instruction
decoder (ED)
Arbitrator
SEG120
RAM
5
Segment Signa - driver
8
120-bit latch
V1
V2
V3A
V3B
V4
V5
V5IN
Instruction
register
(IR)
Common
shift
120-bit shift register
T1
T2
T3
8
17-bit
Rarallelserial
converter
RS1
RS0
R/W
E
CS
P/S
SHT
SI
SO
DB0 to DB3
DB4 to DB7
Cursor
blink
controller
generator
¡ Semiconductor
OSC1
OSCR
OSC2
BLOCK DIAGRAM
VDD
GND
(ABRAM)
Voltage
multiplier
circuit
VIN
BEB
ML9044
2/54
CSR SSR
VCC VC
¡ Semiconductor
ML9044
I/O CIRCUITS
VDD
VDD
VDD
P
P
P
N
N
Applied to pins E, SSR, CSR, BEB, CS
P/S, SHT, and SI
VDD
VDD
P
P
Applied to pins T1, T2, and T3
VDD
N
Applied to pins R/W, RS1, and RS0
VDD
N
P
N
Output Enable signal
Applied to pins DB0 to DB7
VDD
VDD
P P
N
Output Enable signal
Applied to pins SO
3/54
¡ Semiconductor
ML9044
PIN DESCRIPTIONS
Symbol
R/W
Description
The input pin with a pull–up resistor to select Read (“H”) or Write (“L”) in the Parallel
I/F Mode.
This pin should be open in the Serial I/F Mode.
RS0, RS1
The input pins with a pull–up resistor– to select a register in the Parallel I/F Mode.
RS1
RS0
H
H
Data register
Name of register
H
L
Instruction register
L
L
Expansion Instruction register
This pin should be open in the Serial I/F Mode.
E
The input pin for data input/output between the CPU and the ML9044 and for activating
instructions in the Parallel I/F Mode.
This pin should be open in the Serial I/F Mode.
DB0 to DB3
The input/output pins to transfer data of lower–order 4 bits between the CPU and the
ML9044 in the Parallel I/F Mode. Each pin is equipped with a pull–up resistor. These 4
lines are not used for the 4–bit interface.
This pin should be open in the Serial I/F Mode.
DB4 to DB7
The input/output pins to transfer data of upper 4 bits between the CPU and the ML9044
in the Parallel I/F Mode. Each pin is equipped with a pull–up resistor.
This pin should be open in the Serial I/F Mode.
OSC1
The clock oscillation pins required for LCD drive signals and the operation of the
OSC2
ML9044 by instructions sent from the CPU.
OSCR
To input external clock, the OSC1 pin should be used. The OSCR and the OSC2 pins
should be open.
To start oscillation with an external resistor, the resistor should be connected between
the OSC1 and OSC2 pins. The OSCR pin should be open.
To start oscillation with an internal resistor, the OSC2 and OSCR pins should be
short–circuited outside the ML9044. The OSC1 pin should be open.
COM1 to COM17
The LCD common signal output pins.
For 1/9 duty, non–selectable voltage waveforms are output via COM10 to COM17. For
1/12 duty, non–selectable voltage waveforms are output via COM13 to COM17.
SEG1 to SEG120
The LCD segment signal output pins.
4/54
¡ Semiconductor
ML9044
Symbol
CSR
Description
The input pin to select the transfer direction of the common signal output data.
Refer to the Expansion Instruction Codes section about the AS bit.
CSR
SSR
duty
AS bit
shift direction
arbitrator's common pin
L
1/9
L
COM1 Æ COM9
COM9
L
1/9
H
COM2 Æ COM9, COM1
COM1
L
1/12
L
COM1 Æ COM12
COM12
L
1/12
H
COM2 Æ COM12, COM1
COM1
L
1/17
L
COM1 Æ COM17
COM17
L
1/17
H
COM2 Æ COM17, COM1
COM1
H
1/9
L
COM9 Æ COM1
COM1
H
1/9
H
COM8 Æ COM1, COM9
COM9
H
1/12
L
COM12 Æ COM1
COM1
H
1/12
H
COM11 Æ COM1, COM12
COM12
H
1/17
L
COM17 Æ COM1
COM1
H
1/17
H
COM16 Æ COM1, COM17
COM17
The input pin to select the transfer direction of the segment signal output data.
“L”: Data transfer from SEG1 to SEG120
“H”: Data transfer from SEG120 to SEG1
V1, V2, V3A, V3B, V4
The pins to output bias voltages to the LCD.
For 1/4 bias : The V2 and V3B pins are shorted.
For 1/5 bias : The V3A and V3B pins are shorted.
BEB
The input pin to enable or disable the voltage multiplier circuit.
“L” disables the voltage multiplier circuit. “H” enables the voltage multiplier circuit.
The voltage multiplier circuit doubles the input voltage VIN and outputs it to the V5IN pin.
The voltage multiplier circuit can be used only when generating a level lower than GND.
VIN
V5, V5IN
The pin to input voltage to the voltage multiplier.
The pins to supply the LCD drive voltage.
The LCD drive voltage is supplied to the V5 pin when the voltage multiplier is not used
(BEB = 0) and the internal contrast adjusting circuit is also not used. At this time, the
V5IN pin should be open.
The LCD drive voltage is supplied to the V5IN pin when the voltage multiplier is not used
(BEB = 0) but the internal contrast adjusting circuit is used. At this time, the V5 pin
should be open.
When the voltage multiplier is used (BEB = 1), the V5IN and V5 pins should be open (the
multiplied voltage is output to the V5IN pin). In this case, the internal contrast adjusting
circuit is used automatically.
VC
The pin to connect the positive pin of the capacitor for the voltage multiplier.
VCC
The pin to connect the negative pin of the capacitor used for the voltage multiplier.
5/54
¡ Semiconductor
Symbol
T1, T2, T3
ML9044
Description
The input pins for test circuits (normally open). Equipped with a pull–down resistor.
VDD
The power supply pin.
GND
The ground level input pin.
P/S
The input pin to select the parallel or serial interface.
“L” selects the parallel interface.
“H” selects the serial interface.
CS
The pin to enable this IC in the serial I/F mode.
“L” enables this IC.
“H” disables this IC.
This pin should be open in the parallel I/F mode.
SHT
The pin to input shift clock in the serial I/F mode.
Data inputting to the SI pin is carried out synchronizing with the rising edge of this
clock signal.
Data outputting from the SO pin is carried out synchronizing with the falling edge of this
clock signal.
This pin should be open in the parallel I/F mode.
SI
The pin to input DATA in the serial I/F mode.
Data inputting to this pin is carried out synchronizing with the rising edge of the SHT
signal.
This pin should be open in the parallel I/F mode.
SO
The pin to output DATA in the serial I/F mode.
Data inputting to this pin is carried out synchronizing with the falling edge of the SHT
signal.
This pin should be open in the parallel I/F mode.
6/54
¡ Semiconductor
ML9044
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
LCD Driving Voltage
Symbol
Condition
Rating
Unit
VDD
Ta = 25°C
–0.3 to +6.5
V
Ta = 25°C
VDD – 7.5 to VDD+0.3
V
V1, V2, V3,
V4, V5
(GND = 0V)
Applicable pins
VDD – GND
V1, V4, V5, V5IN,
V2, V3A, V3B
R/W, E, SHT, CSR,
P/S, SSR, SI, RS0,
Input Voltage
VI
Ta = 25°C
–0.3 to VDD+0.3
V
RS1, BEB, CS,
T1 to T3, DB0 to DB7,
VIN
Storage Temperature
TSTG
—
–55 to +125
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
LCD Driving Voltage
—
(GND = 0V)
Unit Applicable pins
Symbol
Condition
Range
VDD
—
2.5 to 5.5
V
—
2.8 to 7.0
V
VDD–V5
(See Note)
Input Voltage
VIN
BEB = 1
Operating Temperature
Top
—
Note:
°C
VDD–1.40 to
VDD–3.5
–40 to +85
VDD–GND
VDD–V5
(V5IN)
V
VDD–VIN
°C
—
This voltage should be applied across VDD and V5. The following voltages are output
to the V1, V2, V3A (V3B) and V4 pins:
• 1/4 bias
V1 = {VDD–(VDD–V5)/4} ±0.15V
V2 = V3B= {VDD–(VDD–V5)/2} ±0.15V
V4 = {VDD–3 ¥ (VDD–V5)/4 } ±0.15V
• 1/5 bias
V1 = {VDD–(VDD–V5)/5} ±0.15V
V2 = {VDD–2 ¥ (VDD–V5)/5} ±0.15V
V3A = V3B= {VDD–3 ¥ (VDD–V5)/5} ±0.15V
V4 = {VDD–4 ¥ (VDD–V5)/5} ±0.15V
The voltages at the V1, V2, V3A (V3B), V4 and V5 pins should satisfy
VDD>V1>V2>V3A(V3B)>V4>V5.
(Higher ¨
Æ Lower)
* Do not apply short–circuiting across output pins and across an output pin and an
input/output pin or the power supply pin in the output mode.
7/54
¡ Semiconductor
ML9044
ELECTRICAL CHARACTERISTICS
DC Characteristics
(GND = 0V, VDD = 2.5V to 5.5V, Ta = –40 to +85°C)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
“H” Input Voltage 1
VIH1
—
0.8VDD
—
VDD
V
“L” Input Voltage 1
VIL1
–0.3
—
0.2VDD
Applicable pin
R/W, RS0, RS1,
E, DB0 to DB7
SHT, P/S, SI, CS
“H” Input Voltage 2
VIH2
“L” Input Voltage 2
VIL2
—
“H” Output Voltage 1 VOH1
IOH = –0.1mA
“L” Output Voltage 1
—
VDD
–0.3
—
0.2VDD
0.75VDD
—
—
IOL = +0.1mA
—
—
0.2VDD
“H” Output Voltage 2 VOH2
IOH = –13mA
0.9VDD
—
—
“L” Output Voltage 2
VOL2
IOL = +13mA
—
—
0.1VDD
COM Voltage
VCH
IOCH = –4mA VDD – V5 = 5V
Drop
SEG Voltage
Drop
Input Leakage
VOL1
0.8VDD
VDD – 0.3
VDD
VCMH
IOCMH = ±4mA
Note 1 V1 – 0.3
V1 + 0.3
VCML
IOCML = ±4mA
V4 – 0.3
V4 + 0.3
VCL
IOCL = +4mA
VSH
IOSH = –4mA VDD – V5 = 5V
V5
SSR, CSR, BEB
V
DB0 to DB7, SO
V
OSC2
V
COM1 to COM17
VDD
V
SEG1 to SEG120
IOSMH = ±4mA
Note 1 V2 – 0.3
VSML
IOSML = ±4mA
V3 – 0.3
V3 + 0.3
VSL
IOSL = +4mA
V5
V5 + 0.3
VDD = 5V, VIN = 5V or 0V
—
mA
E, SSR, CSR, BEB,
V2 + 0.3
—
1.0
SHT, P/S, CS, SI
Current
Input Current 1
OSC1,
V5 + 0.3
VDD – 0.3
VSMH
| IIL |
V
| II1|
VDD = 5V, VIN = GND
10
25
61
VDD = 5V, VIN = VDD,
—
—
2.0
VDD = 5V, VIN = VDD
15
45
105
VDD = 5V, VIN = VDD,
—
—
2.0
—
1.2
mA
R/W, RS0, RS1
DB0 to DB7, SO
Excluding current flowing
through the pull-up resistor
and the output driving MOS
Input Current 2
| II2|
mA
T1, T2, T3
Excluding current flowing
through the pull-down resistor
Supply Current
IDD
LCD Bias Resistor
RLB
VDD = 5V
Note 2
—
Oscillation Frequency of
fosc1
Rf = 120kW±2%
Note 3
175
270
350
kHz
OSC1, OSC2
fosc2
OSC1: Open
Note 4
140
270
480
kHz
OSC1, OSC2,
480
kHz
4.0
mA
VDD – GND
kW
VDD, V1, V2
V3A, V3B, V4, V5
External Resistor Rf
Oscillation Frequency of
External Clock
Clock Input
OSCR
OSC2 and OSCR: Short-circuited
Internal Resistor Rf
fin
Frequency
OSC2, OSCR: Open
125
Input from OSC1
fduty
Note 5
45
50
55
%
Input Clock Rise Time
frf
Note 6
—
—
0.2
mS
Input Clock Fall Time
fff
Note 6
—
—
0.2
mS
Input Clock Duty
OSC1
8/54
¡ Semiconductor
ML9044
(GND = 0V, VDD = 2.5V to 5.5V, Ta = –40 to +85°C)
Parameter
Symbol
Control Range of
LCD Driving
Voltage (by internal
variable resistor)
VLCD
Bias Voltage for Driving
LCD by External Input
Voltage Multiplier
MAX
V5IN = 0V
VLCD
VDD = 5V, 1/5 bias
MIN
V5IN = 0V
VLCD1
VDD – V5
VLCD2
1/5 bias
Note 7 1/4 bias
V5OUT VDD = 3V, VIN = 0V
Output Voltage
Voltage Multipler
Condition
VDD = 5V, 1/5 bias
BEB = H
VIN
Min
Typ
TBD
—
Max
Unit
Applicable pin
VDD – V5
—
TBD
2.8
—
7.0
2.8
—
7.0
VDD – 2VIN
—
VDD – 2VIN
V
V5
V
V5, V5IN
V
VIN
+1.2V
VDD/2
Input Voltage
9/54
¡ Semiconductor
Note 1:
ML9044
Applied to the voltage drop occurring between any of the VDD, V1, V4 and V5 pins and
any of the common pins (COM1 to COM17) when the current of 4mA flows in or flows
out at one common pin.
Also applied to the voltage drop occurring between any of the VDD, V2, V3A (V3B) and
V5 pins and any of the segment pins (SEG1 to SEG120) when the current of 4mA flows
in or flows out at one common pin.
The current of 4mA flows out when the output level is VDD or flows in when the output
level is V5.
Note 2:
Applied to the current flowing into the VDD pin when the external clock (fosc2 = fin =
270 kHz) is fed to the internal Rf oscillation or OSC1 under the following conditions:
VDD = 5V
GND = V5 = 0V,
V1, V2, V3A (V3B) and V4: Open
E, SSR, CSR, and BEB: “L” (fixed)
Other input pins: “L” or “H” (fixed)
Other output pins: No load
Note 3:
Note 4:
OSC1
OSC1
OSCR
OSCR
Rf = 120kW±2%
OSC2
OSC2
The wire between OSC1 and Rf and the wire between
The wire between OSC2 and OSCR should be as short
OSC2 and Rf should be as short as possible.
as possible. Keep OSC1 open.
Keep OSCR open.
Note 5:
tHW
fIN
waveform
tLW
VDD
VDD
VDD
2
2
2
Applied to the pulses entering from the OSC1 pin
fduty = tHW/ (tHW + tLW) ¥ 100 (%)
10/54
¡ Semiconductor
ML9044
Note 6:
0.7VDD
0.7VDD
0.3VDD
0.3VDD
trf
tff
Applied to the pulses entering from the OSC1 pin
Note 7:
For 1/4 bias, V2 and V3B pins are short–circuited. V3A pin is open.
For 1/5 bias, V3A and V3B pins are short–circuited. V2 pin is open.
11/54
¡ Semiconductor
ML9044
Switching Characteristics (The following ratings are subject to change after ES evaluation.)
• Parallel Interface Mode
The timing for the input from the CPU (see 1) and the timing for the output to the CPU (see 2)
are as shown below:
1) WRITE MODE (Timing for input from the CPU)
(VDD = 2.5 to 5.5V, Ta = –40 to +85°C)
Parameter
Symbol
Min
Typ
Max
Unit
R/W, RS0, RS1 Setup time
tB
40
—
—
ns
E Pulse Width
tW
450
—
—
ns
R/W, RS0, RS1 Hold time
tA
10
—
—
ns
E Rise Time
tr
—
—
25
ns
E Fall Time
tf
—
—
25
ns
E Pulse Width
tL
430
—
—
ns
E Cycle Time
tC
1000
—
—
ns
DB0 to DB7 Input Data Hold time
tI
195
—
—
ns
DB0 to DB7 Input Data Setup time
tH
10
—
—
ns
VIH
VIL
RS1, RS0
R/W
VIH
VIL
VIL
VIL
tr
tB
tL
E
VIL
tf
tW
VIH
tA
VIH
VIL
VIL
tI
VIH
VIL
DB0 to DB7
tH
Input
Data
VIH
VIL
tc
12/54
¡ Semiconductor
ML9044
2) READ MODE (Timing for output to the CPU)
(VDD = 2.5 to 5.5V, Ta = –40 to +85°C)
Parameter
Symbol
Min
Typ
Max
Unit
R/W, RS1, RS0 Setup Time
tB
40
—
—
ns
E Pulse Width
tW
450
—
—
ns
R/W, RS1, RS0 Hold Time
tA
10
—
—
ns
E Rise Time
tr
—
—
25
ns
E Fall Time
tf
—
—
25
ns
E Pulse Width
tL
430
—
—
ns
E Cycle Time
tC
1000
—
—
ns
DB0 to DB7 Output Data Delay Time
tD
—
—
350
ns
DB0 to DB7 Output Data Hold Time
tO
20
—
—
ns
RS1, 0
VIH
VIL
R/W
VIH
VIH
VIL
VIH
tr
tB
tL
E
VIL
tW
VIH
tf
tA
VIH
VIL
VIL
tD
tO
VOH
VOL
DB0 to DB7
Output
Data
VOH
VOL
tc
13/54
¡ Semiconductor
ML9044
• Serial Interface Mode
(VDD = 2.5 to 5.5V, Ta = –40 to +85°C)
Symbol
Min
Typ
Max
Unit
SHT Cycle Time
Parameter
tSCY
500
—
—
ns
CS Setup Time
tCSU
100
—
—
ns
CS Hold Time
tCH
100
—
—
ns
SHT Setup Time
tSSU
60
—
—
ns
SHT Hold Time
tSH
200
—
—
ns
SHT "H" Pulse Width
tSWH
200
—
—
ns
SHT "L" Pulse Width
tSWL
200
—
—
ns
SHT Rise Time
tSR
—
—
50
ns
SHT Fall Time
tSF
—
—
50
ns
SI Setup Time
tDISU
100
—
—
ns
SI Hold Time
tDIH
100
—
—
ns
Data Output Delay Time
tDOD
—
—
160
ns
Data Output Hold Time
tCDH
0
—
—
ns
tSCY
CS
VIL
tCSU
SHT
tSSU
tSWL
VIH
VIL
tDISU
VIH
VIL
SI
tDOD
SO
tSR
tSWH
VIH
tSF
VIH
tSH
VIH
VIL
tDIH
VIH
VIL
tDOD
VOL
tCH
tCDH
VOH
VOH
14/54
¡ Semiconductor
ML9044
FUNCTIONAL DESCRIPTION
Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER)
These registers are selected by setting the level of the Register Selection input pins RS0 and RS1.
The DR is selected when both RS0 and RS1 are “H”. The IR is selected when RS0 is “L” and RS1
is “H”. The ER is selected when both RS0 and RS1 are “L”. (When RS0 is “H” and RS1 is “L”, the
ML9044 is not selected.)
The IR stores an instruction code and the address code of the display data RAM (DDRAM) or the
character generator RAM (CGRAM).
The microcontroller (CPU) can write to the IR but cannot read from the IR.
The ER stores a contrast adjusting code and the address code of the arbitrator RAM (ABRAM).
The CPU can write to or read from the ER.
The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read
from the DDRAM, AMRAM and CGRAM.
The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or
CGRAM.
When an address code is written in the IR or ER, the data of the specified address is automatically
transferred from the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM
and CGRAM can be checked by allowing the CPU to read the data stored in the DR.
After the CPU writes data in the DR, the data of the next address in the DDRAM, ABRAM or
CGRAM is selected to be ready for the next writing by the CPU. Similarly, after the CPU reads
the data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is set in the
DR to be ready for the next reading by the CPU.
Writing in or reading from these 3 registers is controlled by changing the status of the R/
W(Read/Write) pin.
Table 1 R/W pin status and register operation
R/W
RS0
RS1
L
L
H
Writing in the IR
Operation
H
L
H
Reading the Busy flag (BF) and the address counter (ADC)
L
H
H
Writing in the DR
H
H
H
Reading from the DR
L
L
L
Writing in the ER
H
L
L
Reading the contrast code
Busy Flag (BF)
The status “1” of the Busy Flag (BF) indicates that the ML9044 is carrying out internal operation.
When the BF is “1”, any new instruction is ignored.
When R/W = “H”, RS0 = “L” and RS1 = “H”, the data in the BF is output to the DB7.
New instructions should be input when the BF is “0”.
When the BF is “1”, the output code of the address counter (ADC) is undefined.
15/54
¡ Semiconductor
ML9044
Address Counter (ADC)
The address counter provides a read/write address for the DDRAM, ABRAM or CGRAM and
also provides a cursor display address.
When an instruction code specifying DDRAM, ABRAM or CGRAM address setting is input to
the pre–defined register, the register selects the specified DDRAM, ABRAM or CGRAM and
transfers the address code to the ADC. The address data in the ADC is automatically incremented
(or decremented) by 1 after the display data is written in or read from the DDRAM, ABRAM or
CGRAM.
The data in the ADC is output to DB0 to DB6 when R/W = “H”, RS0 = “L”, RS1 = “H” and BF =
“0”.
Timing Generator
The timing generator generates timing signals for the internal operation of the ML9044 activated
by the instruction sent from the CPU or for the operation of the internal circuits of the ML9041
such as DDRAM, ABRAM, CGRAM and CGROM. Timing signals are generated so that the
internal operation carried out for LCD displaying will not be interfered by the internal operation
initiated by accessing from the CPU. For example, when the CPU writes data in the DDRAM,
the display of the LCD not corresponding to the written data is not affected.
16/54
¡ Semiconductor
ML9044
Display Data RAM (DDRAM)
This RAM stores the display data represented in 8–bit character coding (see Table 2).
The DDRAM addresses correspond to the display positions (digits) of the LCD as shown below.
The DDRAM addresses (to be set in the ADC) are represented in hexadecimal.
DB6 DB5 DB4 DB3 DB2 DB1 DB0
ADC
MSB
LSB
Hexadecimal
Hexadecimal
(Example) Representation of DDRAM address = 12
ADC
0
0
1
0
1
0
1
0
2
1) Relationship between DDRAM addresses and display positions (1–line display mode)
Digit
1 2
3
4
5
00 01 02 03 04
23 24
Display position
16 17
DD RAM address (hexadecimal)
Left
end
Right
end
In the 1–line display mode, the ML9044 can display up to 24 characters from digit 1 to digit 24.
While the DDRAM has addresses “00” to “4F” for up to 80 character codes, the area not used for
display can be used as a RAM area for general data. When the display is shifted by instruction,
the relationship between the LCD display and the DDRAM address changes as shown below:
Digit
1 2
3
4
23 24
(Display shifted to the right) 4 F 0 0 0 1 0 2
Digit
1 2
(Display shifted to the left)
3
4
15 16
5
01 02 03 04 05
23 24
17 18
17/54
¡ Semiconductor
ML9044
2) Relationship between DDRAM addresses and display positions (2–line display mode)
In the 2–line mode, the ML9044 can display up to 48 characters (24 characters per line) from digit
1 to digit 24.
Digit
1 2 3 4 5
Line 1 0 0 0 1 0 2 0 3 0 4
23 24
16 17
DD RAM
Line 2 4 0 4 1 4 2 4 3 4 4
56 57
address (hexadecimal)
Display position
Note:
The DDRAM address at digit 24 in the first line is not consecutive to the DDRAM address at digit
1 in the second line.
When the display is shifted by instruction, the relationship between the LCD display and the
DDRAM address changes as shown below:
(Display shifted to the right)
(Display shifted to the left)
Digit
1 2 3 4 5
Line 1 2 7 0 0 0 1 0 2 0 3
23 24
15 16
Line 2 6 7 4 0 4 1 4 2 4 3
55 56
Digit
1 2 3 4 5
Line 1 0 1 0 2 0 3 0 4 0 5
23 24
17 18
Line 2 4 1 4 2 4 3 4 4 4 5
57 58
18/54
¡ Semiconductor
ML9044
Character Generator ROM (CGROM)
The CGROM generates small character patterns (5 ¥ 7 dots, 160 patterns) or large character
patterns (5 ¥ 10 dots, 32 patterns) from the 8–bit character code signals in the DDRAM. See Table
2 for the relationship between the 8–bit character codes and the character patterns.
When the 8–bit character code corresponding to a character pattern in the CGROM is written
in the DDRAM, the character pattern is displayed in the display position specified by the
DDRAM address.
19/54
¡ Semiconductor
ML9044
Character Generator RAM (CGRAM)
The CGRAM is used to generate user–specific character patterns that are not in the CGROM.
CGRAM (64 bytes = 512 bits) can store up to 8 small character patterns (5 ¥ 8 dots) or up to 4 large
character patterns (5 ¥ 11 dots).
When displaying a character pattern stored in the CGRAM, write an 8–bit character code (00 to
07 or 08 to 0F; hex.) assigned in Table 2 to the DDRAM. This enables outputting the character
pattern to the LCD display position corresponding to the DDRAM address.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC.
Therefore, the cursor or blink display should be inhibited while the ADC is holding a CGRAM
or ABRAM address.
The following describes how character patterns are written in and read from the CGRAM.
1) Small character patterns (5 ¥ 8 dots) (See Table 3–1.)
(1) A method of writing character patterns to the CGRAM from the CPU
The three CGRAM address bits 0 to 2 select one of the lines constituting a character pattern.
First, set the mode to increment or decrement from the CPU, and then input the CGRAM address.
Write each line of the character pattern code in the CGRAM through DB0 to DB7.
The data lines DB0 to DB7 correspond to the CGRAM data bits 0 to 7, respectively (see Table 3.1).
Input data “1” represents the ON status of an LCD dot and “0” represents the OFF status. Since
the ADC is automatically incremented or decremented by 1 after the data is written to the
CGRAM, it is not necessary to set the CGRAM address again.
The bottom line of a character pattern (the CGRAM address bits 0 to 2 are all “1”, which means
7 in hexadecimal) is the cursor line. The ON/OFF pattern of this line is ORed with the cursor
pattern for displaying on the LCD. Therefore, the pattern data for the cursor position should be
all zeros to display the cursor.
Whereas the data given by the CGRAM data bits 0 to 4 is output to the LCD as display data, the
data given by the CGRAM data bits 5 to 7 is not. Therefore, the CGRAM data bits 5 to 7 can be
used as a RAM area.
(2) A method of displaying CGRAM character patterns on the LCD
The CGRAM is selected when the higher–order 4 bits of a character code are all zeros. Since bit
3 of a character code is not used, the character pattern “0” in Table 3–1 can be selected using the
character code “00” or “08” in hexadecimal.
When the 8–bit character code corresponding to a character pattern in the CGRAM is written to
the DDRAM, the character pattern is displayed in the display position specified by the DDRAM
address. (The DDRAM data bits 0 to 2 correspond to the CGRAM address bits 3 to 5,
respectively.)
20/54
¡ Semiconductor
ML9044
2) Large character patterns (5 ¥ 11 dots) (See Table 3–2.)
(1) A method of writing character patterns to the CGRAM from the CPU
The four CGRAM address bits 0 to 3 select one of the lines constituting a character pattern.
First, set the mode to increment or decrement from the CPU, and then input the CGRAM address.
Write each line of the character pattern code in the CGRAM through DB0 to DB7.
The data lines DB0 to DB7 correspond to the CGRAM data bits 0 to 7, respectively (see Table 3–
2). Input data “1” represents the ON status of an LCD dot and “0” represents the OFF status.
Since the ADC is automatically incremented or decremented by 1 after the data is written to the
CGRAM, it is not necessary to set the CGRAM address again.
The bottom line of a character pattern (the CGRAM address bits 0 to 3 are all “1”, which means
A in hexadecimal) is a cursor line. The ON/OFF pattern of this line is ORed with the cursor
pattern for displaying on the LCD. Therefore, the pattern data for the cursor position should be
all zeros to display the cursor.
Whereas the data given by the CGRAM data bits 0 to 4 with the CGRAM addresses 0 to A in
hexadecimal (set by the CGRAM address bits 0 to 3) is output as display data to the LCD, the data
given by the CGRAM data bits 5 to 7 or the CGRAM addresses B to F in hexadecimal is not. These
bits can be written and read as a RAM area.
(2) A method of displaying CGRAM character patterns on the LCD
The CGRAM is selected when the higher–order 4 bits of a character code are all zeros. Since bits
0 and 3 of a character code are not used, the character pattern “b” in Table 3–2 can be selected with
a character code “00”, “01”, “08” or “09” in hexadecimal.
When the 8–bit character code corresponding to a character pattern in the CGRAM is written to
the DDRAM, the character pattern is displayed in the display position specified by the DDRAM
address. (The DDRAM data bits 1 and 2 correspond to the CGRAM address bits 4 and 5,
respectively.)
21/54
¡ Semiconductor
ML9044
Arbitrator RAM (ABRAM)
The arbitrator RAM(ABRAM) stores arbitrator display data.
The ABRAM address is set at the ADC with the relationship illustrated below. Its valid address
area is 00 to 23 (00H to 17H).
Although an address exceeding 23 (17H) can be set or the address already set may exceed it due
to automatic increment or decrement processing, any address out of the valid address area is
ignored.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC.
Therefore, the cursor or blink display should be inhibited while the ADC is hoding a CGRAM
or ABRAM address.
DB6 DB5 DB4 DB3 DB2 DB1 DB0
ADC
MSB
Hexadecimal
LSB
Hexadecimal
The arbitrator RAM can store a maximum of 120 dots of the arbitrator Display–ON data in units
of 5 dots.
The arbitrator display is not shifted by any instructions and has the following relationship with
the LCD display positions:.
Configuration of input display data
Input data
Relationship between display-ON
data and segment pins
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
*
*
*Don't Care
*
E4
E3
E2
E1
5XSn+1
5XSn+5
E4
E4
E0
Display - ON data
Sn = ABRAM address (0 to 23)
22/54
Lower
4 bits
Upper
4 bits
MSB
0000
0000
LSB
CG
RAM (1)
0001
(2)
0010
(3)
0011
(4)
0100
0010
0011
0100
0101
0110
0111
1010
1011
1100
1101
1110
1111
@
P
/
p
a
R
1
A
Q
a
q
ä
q
2
B
R
b
r
b
Q
#
3
C
S
c
s
e
•
(5)
$
4
D
T
d
t
m
W
0101
(6)
%
5
E
U
e
u
s
ü
0110
(7)
&
6
F
V
f
v
r
S
0111
(8)
7
G
W
n
w
g
p
1000
(1)
(
8
H
X
h
x
√
X
1001
(2)
)
9
I
Y
i
y
–1
1010
(3)
*
:
J
Z
j
z
j
1011
(4)
+
;
K
[
k
{
x
1100
(5)
<
L
¥
l
Ù
¢
1101
(9)
–
=
M
]
m
}
£
1110
(7)
.
>
N
^
n
Æ
n
1111
(8)
/
?
O
_
o
¨
!
°
ö
÷
ML9044
23/54
0
¡ Semiconductor
Table 2 Relationship between character codes and character patterns of the ML9044
¡ Semiconductor
Table 3–1
ML9044
Relationship between CGRAM address bits, CGRAM data bits (character pattern)
and DDRAM data bits (character code) in 5 ¥ 7 dot character mode. (Examples)
CG RAM
address
CG RAM data
(Character pattern)
DD RAM data
543210
7 6 5 4 3 2 1 0
76543210
MSB
LSB MSB
LSB
0000
0
0
0
1
1
1
1
0010
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0 ¥ ¥ ¥01110
1
10001
0
10001
1
10001
0
10001
1
10001
0
01110
1
00000
0 ¥ ¥ ¥10001
1
10010
0
10100
1
11000
0
10100
1
10010
0
10001
1
00000
1110
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 ¥ ¥ ¥01110
1
00100
0
00100
1
00100
0
00100
1
00100
0
01110
1
00000
(Character code)
MSB
LSB
0000¥000
0000¥001
0000¥111
¥: Don't Care
24/54
¡ Semiconductor
Table 3–2
ML9044
Relationship between CGRAM address bits, CGRAM data bits (character pattern)
and DDRAM data bits (character code) in 5 ¥ 10 dot character mode (Examples)
CG RAM
address
CG RAM data
(Character pattern)
DD RAM data
543210
76543210
76543210
MSB
LSB MSB
LSB
000
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
000
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0 ¥ ¥ ¥01000
1
01111
0
10010
1
01111
0
01 0 10
1
11111
0
00010
1
00000
0
00000
1
00000
0
00000
1
¥¥¥¥¥
0
1
0
1
0 ¥ ¥ ¥00000
00000
1
01111
0
10001
1
10001
0
10001
1
01111
0
00001
1
00001
0
01110
1
00000
0
¥¥¥¥¥
1
0
1
0
1
000
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0 ¥ ¥ ¥00000
00000
1
0
11011
1
01010
0
10001
1
10001
0
01110
1
00000
0
00000
1
00000
0
00000
1
¥¥¥¥¥
0
1
0
1
(Character code)
MSB
LSB
0000¥00¥
0000¥00¥
0000¥11¥
¥: Don't Care
25/54
¡ Semiconductor
ML9044
Cursor/Blink Control Circuit
This circuit generates the cursor and blink of the LCD.
The operation of this circuit is controlled by the program of the CPU.
The cursor/blink display is carried out in the position corresponding to the DDRAM address set
in the ADC (Address Counter).
For example, when the ADC stores a value of “07” (hexadecimal), the cursor or blink is displayed
as follows:
DB6
ADC
0
DB0
0 0
0
1
0
Digit
1 2
In 1-line display mode
1
1
7
9
23 24
00 01 02 03 04 05 06 07 08
16 17
3
4
5
6
7
8
Cursor/blink position
Digit
1 2
In 2-line display mode
9
23 24
00 01 02 03 04 05 06 07 08
16 17
Second line 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8
56 57
First line
3
4
5
6
7
8
Cursor/blink position
Note:
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set
in the ADC. Therefore, the cursor or blink display should be inhibited while the ADC
is holding a CGRAM or ABRAM address.
26/54
¡ Semiconductor
ML9044
LCD Display Circuit (COM1 to COM17, SEG1 to SEG120, SSR and CSR)
The ML9044 has 17 common signal outputs and 120 segment signal outputs to display 24
characters (in the 1–line display mode) or 48 characters (in the 2–line display mode).
The character pattern is converted into serial data and transferred in series through the shift
register.
The transfer direction of serial data is determined by the SSR pin. The shift direction of common
signals is determined by the CSR pin. The following tables show the transfer and shift directions:
SSR
Transfer direction
L
SEG1 Æ SEG120
H
SEG120 Æ SEG1
CSR
duty
AS bit
Shift direction
arbitrator's common pin
L
1/9
L
COM1 Æ COM9
COM9
L
1/9
H
COM2 Æ COM9, COM1
COM1
L
1/12
L
COM1 Æ COM12
COM12
L
1/12
H
COM2 Æ COM12, COM1
COM1
L
1/17
L
COM1 Æ COM17
COM17
L
1/17
H
COM2 Æ COM17, COM1
COM1
H
1/9
L
COM9 Æ COM1
COM1
H
1/9
H
COM8 Æ COM1, COM9
COM9
H
1/12
L
COM12 Æ COM1
COM1
H
1/12
H
COM11 Æ COM1, COM12
COM12
H
1/17
L
COM17 Æ COM1
COM1
H
1/17
H
COM16 Æ COM1, COM17
COM17
* Refer to the Expansion Instruction Codes section about the AS bit.
Signals to be input to the SSR and CSR pins should be determined at power–on and be kept
unchanged.
27/54
¡ Semiconductor
ML9044
Built–in Reset Circuit
The ML9044 is automatically initialized when the power is turned on.
During initialization, the Busy Flag (BF) is “1” and the ML9041 does not accept any instruction
from the CPU (other than the Read BF instruction).
The Busy Flag is “1” for about 15 ms after the VDD becomes 2.5 V or higher.
During this initialization, the ML9044 performs the following instructions:
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
11)
Display clearing
CPU interface data length = 8 bits
(DL = “1”)
1–line LCD display
(N = “0”)
Font size = 5 ¥ 7 dots
(F = “0”)
ADC counting = Increment
(I/D = “1”)
Display shifting = None
(S = “0”)
Display = Off
(D = “0”)
Cursor = Off
(C = “0”)
Blinking = Off
(B = “0”)
Arbitrator = Displayed in the lower line
(AS = “0”)
Setting 1FH (hexadecimal) to the Contrast Data
To use the built–in reset circuit, the power supply conditions shown below should be satisfied.
Otherwise, the built–in reset circuit may not work properly. In such a case, initialize the ML9044
with the instructions from the CPU. The use of a battery always requires such initialization from
the CPU. (See “Initial Setting of Instructions”)
2.5V
0.2V
0.2V
tON
0.2V
tOFF
0.1ms£ tON £ 100ms
1ms£ tOFF
Figure 1 Power–on and Power–off Waveform
28/54
¡ Semiconductor
ML9044
I/F with CPU
Parallel interface mode
The ML9044 can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any
8–bit or 4–bit microcontroller (CPU).
1) 8–bit interface data length
The ML9044 uses all of the 8 data bus lines DB0 to DB7 at a time to transfer data to and from the
CPU.
2) 4–bit interface data length
The ML9044 uses only the higher–order 4 data bus lines DB4 to DB7 twice to transfer 8–bit data
to and from the CPU.
The ML9044 first transfers the higher–order 4 bits of 8–bit data (DB4 to DB7 in the case of 8–bit
interface data length) and then the lower–order 4 bits of the data (DB0 to DB3 in the case of 8–bit
interface data length).
The lower–order 4 bits of data should always be transferred even when only the transfer of the
higher–order 4 bits of data is required. (Example: Reading the Busy Flag)
Two transfers of 4 bits of data complete the transfer of a set of 8–bit data. Therefore, when only
one access is made, the following data transfer cannot be completed properly.
29/54
¡ Semiconductor
ML9044
RS1
RS0
R/W
E
Busy
(Internal operation)
No
Busy
DR7
IR6
ADC6
DR6
DB5
IR5
ADC5
DR5
DB4
IR4
ADC4
DR4
DB3
IR3
ADC3
DR3
DB2
IR2
ADC2
DR2
DB1
IR1
ADC1
DR1
DB0
IR0
ADC0
DR0
DB7
IR7
DB6
Busy
Writing In IR
(Instruction
Register)
Writing In DR
(Data Register)
Reading BF (Busy Flag)
and ADC (Address Counter)
Figure 2 8-Bit Data Transfer
RS1
RS0
R/W
E
Busy
(Internal operation)
No
Busy
ADC3
DR7
DR3
IR2
ADC6
ADC2
DR6
DR2
IR5
IR1
ADC5
ADC1
DR5
DR1
IR4
IR0
ADC4
ADC0
DR4
DR0
DB7
IR7
IR3
DB6
IR6
DB5
DB4
Writing In IR
(Instruction
Register)
Busy
Reading BF (Busy Flag)
and ADC (Address Counter)
Writing In DR
(Data Register)
Figure 3 4-Bit Data Transfer
30/54
¡ Semiconductor
ML9044
Serial Interface Mode
In the Serial I/F Mode, the ML9044 interfaces with the CPU via the CS, SHT, SI and SO pins.
Writing and reading operations are executed in units of 16 bits after the CS signal falls down. If
the CS signal rises up before the completion of 16–bit unit access, this access is ignored.
When the BF bit is “1”, the ML9044 cannot accept any other instructions. Before inputting a new
instruction, check that the BF bit is “0”. Any access when the BF bit is “1” is ignored.
Data format is LSB–first.
Examples of Access in the Serial I/F Mode
1) WRITE MODE
CS
1
2
3
4
5
6
1
1
1
1
1
1
2
3
4
5
6
1
1
1
1
1
R/W
7
8
9
10
11
12
13
14
15
16
SHT
SI
R/W RS0 RS1
D0
D1
D2
D3
D4
D5
D6
D7
SO
2) READ MODE
CS
7
8
9
10
11
12
13
14
15
16
SHT
SI
SO
RS0 RS1
D0
D1
D2
D3
D4
D5
D6
D7
31/54
¡ Semiconductor
ML9044
Instruction Codes
Table of Instruction Codes
Instruction
Code
Execution
Time
f = 270kHz
Function
RS1 RS0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Clears all the displayed digits of the LCD and
1
Display Clear
0
0
0
0
0
0
0
0
0
1
sets the DDRAM address 0 in the address
1.52 ms
counter. The arbitrator data is cleared.
Sets the DDRAM address 0 in the address
1
Cursor Home
0
0
0
0
0
0
0
0
1
*
counter and shifts the display back to the
original. The content of the DDRAM
1.52 ms
remains unchanged.
Determines the direction of movement of
Entry Mode Setting
1
0
0
0
0
0
0
0
1
I/D
S
the cursor and whether or not to shift the
display. This instruction is executed when
37 ms
data is written or read.
Sets LCD display ON/OFF (D), cursor
Displya ON/OFF Control
1
0
0
0
0
0
0
1
D
C
B
ON/OFF or cursor-position character
37 ms
blinking ON/OFF.
Cursor/Display Shift
1
0
0
0
0
0
1
S/C
R/L
*
*
Function Setting
1
0
0
0
0
1
DL
N
F
*
*
Moves the cursor or shifts the display
without changing the content of the DDRAM.
37 ms
Sets the interface data length (DL), the
number of display lines (N) or the type of
37 ms
character font (F).
Sets on CGRAM address. After that,
CGRAM Address Setting
1
0
0
0
1
CGRAM data is transferred to and from
ACG
37 ms
the CPU.
Sets a DDRAM address. After that DDRAM
DDRAM Address Setting
1
0
0
1
ADD
Busy Flag/Address Read
1
0
1
BF
ADC
data is transferred to and from the CPU.
37 ms
Reads the Busy Flag (indicating that the
RAM Data Write
1
1
0
WRITE DATA
RAM Data Read
1
1
1
READ DATA
Arbitrator Display Line Set
0
0
0
0
0
0
0
Contrast Control Data Write
0
0
0
0
0
1
Contrast Control Data Read
0
0
1
0
0
0
0
ML9044 is operating) and the content of
the address counter.
Writes data in DDRAM, ABRAM or CGRAM.
Reads data from DDRAM, ABRAM or CGRAM.
0
1
AS
0 ms
37 ms
37 ms
Sets the arbitrator display line.
37 ms
WRITE (Contrast Data) DATA
Writes data to control the contrast of the LCD.
37 ms
READ (Contrast Data) DATA
Reads data to control the contrast of the LCD.
37 ms
Sets an ABRAM address. After that
ABRAM address setting
0
0
0
0
1
1
AAB
ABRAM data is transferred to and from
37 ms
the CPU.
—
I/D = "1" (Increment)
S = "1" (Shifts the display.)
S/C = "1" (Shifts display.)
R/L = "1" (Right shift)
D/L = "1" (8-bit data)
N = "1" (2 lines)
F = "1" (5 ¥ 10 dots)
BF = "1" (Busy)
B = "1"
C = "1"
D = "1"
AS = "1"
I/D = "0" (Decrement)
S/C = "0" (Moves the cursor.)
R/L = "0" (Left shift)
DL = "0" (4-bit data)
N = "0" (1 line)
F = "0" (5 ¥ 7 dots)
BF = "0" (Ready to accept
an instruction)
DD RAM : Display data RAM
CG RAM : Character generator RAM
ABRAM : Arbitrator data RAM
ACG
: CGRAM address
ADD
: DDRAM address (Corresponds to
the cursor address)
AAB
: ABRAM address
ADC
: Address counter (Used by DDRAM,
ABRAM and CGRAM)
The
execution
time is
dependent
upon
frequencies
(Enables blinking.)
(Displyas the corsor.)
(Displays a character pattern.)
(Arbitrator Displays arbitrator AS = "0" (Arbitrator Displays
on the upper line)
arbitrator on the lower line)
¥: Don't Care
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¡ Semiconductor
ML9044
Instruction Codes
An instruction code is a signal sent from the CPU to access the ML9044. The ML9044 starts
operation as instructed by the code received. The busy status of the ML9044 is rather longer than
the cycle time of the CPU, since the internal processing of the ML9044 starts at a timing which
does not affect the display on the LCD. In the busy status (Busy Flag is “1”), the ML9044 executes
the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is “0”
before sending an instruction code to the ML9044.
1) Display Clear
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
0
0
0
1
Instruction Code :
When this instruction is executed, the LCD display including arbitrator display is cleared and the
I/D entry mode is set to “Increment”. The value of “S” (Display shifting) remains unchanged.
The position of the cursor or blink being displayed moves to the left end of the LCD (or the left
end of the line 1 in the 2–line display mode).
Note:
All DDRAM and ABRAM data turn to “20” and “00” in hexadecimal, respectively. The
value of the address counter (ADC) turns to the one corresponding to the address “00”
(hexadecimal) of the DDRAM.
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency
of 270 kHz.
2) Cursor Home
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
0
0
1
¥
¥: Don't Care
When this instruction is executed, the cursor or blink position moves to the left end of the LCD
(or the left end of line 1 in the 2–line display mode). If the display has been shifted, the display
returns to the original display position before shifting.
Note:
The value of the address counter (ADC) goes to the one corresponding to the address
“00” (hexadecimal) of the DDRAM).
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency
of 270 kHz.
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¡ Semiconductor
ML9044
3) Entry Mode Setting
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
0
1
I/D
S
(1) When the I/D is set, the cursor or blink shifts to the right by 1 character position (ID= “1”;
increment) or to the left by 1 character position (I/D= “0”; decrement) after an 8–bit character
code is written to or read from the DDRAM. At the same time, the address counter (ADC) is also
incremented by 1 (when I/D = “1”; increment) or decremented by 1 (when I/D = “0”; decrement).
After a character pattern code is written to or read from the CGRAM, the address counter (ADC)
is incremented by 1 (when I/D = “1”; increment) or decremented by 1 (when I/D = “0”;
decrement).
Also after data is written to or read from the ABRAM, the address counter (ADC) is incremented
by 1 (when I/D = “1”; increment) or decremented by 1 (when I/D = “0”; decrement).
(2) When S = “1”, the cursor or blink stops and the entire display shifts to the left (I/D = “1”) or
to the right (I/D = “0”) by 1 character position after a character code is written to the DDRAM.
In the case of S = “1”,when a character code is read from the DDRAM, when a character pattern
data is written to or read from the CGRAM or when data is written to or read from the ABRAM,
normal read/write is carried out without shifting of the entire display. (The entire display does
not shift, but the cursor or blink shifts to the right (I/D = “1”) or to the left (I/D = “0”) by 1
character position.)
When S = “0”, the display does not shift, but normal write/read is performed.
Note:
The execution time of this instruction is 37 ms (maximum) at an oscillation frequency
of 270 kHz.
4) Display Mode Setting
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
1
D
C
B
(1) The “D” bit (DB2) of this instruction determines whether or not to display character patterns
on the LCD.
When the “D” bit is “1”, character patterns are displayed on the LCD.
When the “D” bit is “0”, character patterns are not displayed on the LCD and the cursor/blink
setting is also canceled.
Note:
Unlike the Display Clear instruction, this instruction does not change the character
code in the DDRAM and ABRAM.
(2 ) When the “C” bit (DB1) is “0”, the cursor turns off. When both the “C” and “D” bits are “1”,
the cursor turns on.
(3) When the “B” bit (DB0) is “0”, blinking is canceled. When both the “B” and “D” bits are “1”,
blinking is performed.
In the Blinking mode, all dots including those of the cursor, the character pattern and the cursor
are alternately displayed.
Note:
The execution time of this instruction is 37 ms (maximum) at an oscillation frequency
of 270kHz.
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¡ Semiconductor
ML9044
5) Cursor/Display Shift
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
1
S/C
R/L
¥
¥
Instruction code:
¥: FDon't Care
S/C = “0”, R/L = “0” This instruction shifts left the cursor and blink positions by 1 (decrements
the content of the ADC by 1).
S/C = “0”, R/L = “1” This instruction shifts right the cursor and blink positions by 1 (increments
the content of the ADC by 1).
S/C = “1”, R/L = “0” This instruction shifts left the entire display by 1 character position. The
cursor and blink positions move to the left together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)
S/C = “1”, R/L = “1” This instruction shifts right the entire display by 1 character position. The
cursor and blink positions move to the right together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)
In the 2–line mode, the cursor or blink moves from the first line to the second line when the cursor
at digit 40 (27; hex) of the first line is shifted right.
When the entire display is shifted, the character pattern, cursor or blink will not move between
the lines (from line 1 to line 2 or vice versa).
Note:
The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
6) Function Setting
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
1
DL
N
F
¥
¥
¥: Don't Care
(1) When the “DL” bit (DB4) of this instruction is “1”, the data transfer to and from the CPU is
performed once by the use of 8 bits DB7 to DB0.
When the “DL” bit (DB4) of this instruction is “0”, the data transfer to and from the CPU is
performed twice by the use of 4 bits DB7 to DB4.
(2) The 2–line display mode is selected when the “N” bit (DB3) of this instruction is “1”. The 1–
line display mode is selected when the “N” bit is “0”.
(3) The character font represented by 5 ¥ 7 dots is selected when the “F” bit (DB2) of this
instruction is “1”. The character font represented by 5 ¥ 10 dots is selected when the “F” bit is “1”
and the “N” bit is “0”.
After the ML9044 is powered on, this initial setting should be carried out before execution of any
instruction except the Busy Flag Read. After this initial setting, no instructions other than the DL
Set instruction can be executed. In the Serial I/F Mode, DL setting is ignored.
N
F
0
0
0
1
1
Note:
Number of
Number of
Number of
biases
common signals
4
9
1/12
4
12
1/17
5
17
1/17
5
17
Font size
Duty
1
5¥7
1/9
1
1
5¥10
0
2
5¥7
1
2
5¥7
display lines
The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
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¡ Semiconductor
ML9044
7) CGRAM Address Setting
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
1
C5
C4
C3
C2
C1
C0
This instruction sets the character data corresponding to the CGRAM address represented by the
bits C5 to C0 (binary).
The CGRAM addresses are valid until DDRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the CGRAM
address bits C5 to C0 set in the instruction code at that time.
Note:
The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
8) DDRAM Address Setting
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
D6
D5
D4
D3
D2
D1
D0
This instruction sets the character data corresponding to the DDRAM address represented by the
bits D6 to D0 (binary).
The DDRAM addresses are valid until CGRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the DDRAM
address bits D6 to D0 set in the instruction code at that time.
In the 1–line mode (the “N” bit is “1”), the DDRAM address represented by bits D6 to D0 (binary)
should be in the range “00” to “4F” in hexadecimal.
In the 2–line mode (the “N” bit is “2”), the DDRAM address represented by bits D6 to D0 (binary)
should be in the range “00” to “27” or “40” to “67” in hexadecimal.
If an address other than above is input, the ML9044 cannot properly write a character code in or
read it from the DDRAM.
Note:
The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
9) DDRAM/ABRAM/CGRAM Data Write
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
0
E7
E6
E5
E4
E3
E2
E1
E0
This instruction writes data represented by bits E7 to E0 (binary) to DDRAM, ABRAM or
CGRAM.
After data is written, the cursor, blink or display shifts according to the Cursor/Display Shift
instruction (see 5)).
Note:
The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
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¡ Semiconductor
ML9044
10) Busy Flag/Address Counter Read (Execution time: 1 ms)
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
BF
O6
O5
O4
O3
O2
O1
O0
The “BF” bit (DB7) of this instruction tells whether the ML9044 is busy in internal operation (BF
= “1”) or not (BF = “0”).
When the “BF” bit is “1”, the ML9044 cannot accept any other instructions. Before inputting a
new instruction, check that the “BF” bit is “0”.
When the “BF” bit is “0”, the ML9044 outputs the correct value of the address counter. The value
of the address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the
DDRAM, ABRAM and CGRAM addresses is set in the counter is determined by the preceding
address setting.
When the “BF” bit is “1”, the value of the address counter is not always correct because it may
have been incremented or decremented by 1 during internal operation.
11) DDRAM/ABRAM/CGRAM Data Read
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
1
P7
P6
P5
P4
P3
P2
P1
P0
A character code (P7 to P0) is read from the DDRAM, Display–ON data (P7 to P0) from the
ABRAM or a character pattern (P7 to P0) from the CGRAM.
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is read, the address counter (ADC) is incremented or decremented as set by the
Transfer Mode Setting instruction (see 3).
Note:
Conditions for reading correct data
(1) The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read
instruction is input.
(2) When reading a character code from the DDRAM, the Cursor/Display Shift instruction (see
5) is input before this Data Read instruction is input.
(3) When two or more consecutive RAM Data Read instructions are executed, the following read
data is correct.
Correct data is not output under conditions other than the cases (1), (2) and (3) above.
Note:
The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
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¡ Semiconductor
ML9044
Expansion Instruction Codes
The busy status of the ML9044 is rather longer than the cycle time of the CPU, since the internal
processing of the ML9044 starts at a timing which does not affect the display on the LCD. In the
busy status (Busy Flag is “1”), the ML9041 executes the Busy Flag Read instruction only.
Therefore, the CPU should ensure that the Busy Flag is “0” before sending an expansion
instruction code to the ML9044.
1) Arbitrator Display Line Set
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
1
AS
Exparsion Instruction codes:
This expansion instruction code sets the Arbitrator display line. The relationship between the
status of this bit and the common outputs is as follows:
CSR
duty
AS bit
Shift direction
Arbitrator's comon pin
L
1/9
L
COM1 Æ COM9
COM9
L
1/9
H
COM2 Æ COM9, COM1
COM1
L
1/12
L
COM1 Æ COM12
COM12
L
1/12
H
COM2 Æ COM12, COM1
COM1
L
1/17
L
COM1 Æ COM17
COM17
L
1/17
H
COM2 Æ COM17, COM1
COM1
H
1/9
L
COM9 Æ COM1
COM1
H
1/9
H
COM8 Æ COM1, COM9
COM9
H
1/12
L
COM12 Æ COM1
COM1
H
1/12
H
COM11 Æ COM1, COM12
COM12
H
1/17
L
COM17 Æ COM1
COM1
H
1/17
H
COM16 Æ COM1, COM17
COM17
2) Contrast Adjusting Data Write
Exparsion Instraction codes:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
F4
F3
F2
F1
F0
This instruction writes contrast adjusting data (F4 to F0) to the contrast register.
After contrast adjusting data is written in the register, the potential (VLCD) output to the V5 pin
varies according to the data written.
The VLCD becomes maximum when the content of the contrast register is “1F” (hexadecimal)
and becomes minimum when it is “00” (hexadecimal).
Note:
The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
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¡ Semiconductor
ML9044
3) Contrast Adjusting Data Read
Exparsion Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
0
0
G4
G3
G2
G1
G0
This instruction reads contrast adjusting data (G4 to G0) from the contrast register.
Note:
The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
4) ABRAM Address Setting
Exparsion Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
1
H4
H3
H2
H1
H0
This instruction sets the character data corresponding to the ABRAM address represented by the
bits H4 to H0 (binary).
The ABRAM addresses are valid until CGRAM or DDRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the ABRAM
address bits H4 to H0 set in the instruction code at that time.
The ABRAM address represented by bits H4 to H0 (binary) should be in the range “00” to “13”
in hexadecimal.
If an address other than above is input, the ML9044 cannot properly write a character code in or
read it from the DDRAM.
Note:
The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
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¡ Semiconductor
ML9044
LCD Drive Waveforms
The COM and SEG waveforms (AC signal waveforms for display) vary according to the duty (1/
9, 1/12 and 1/17 duties). See 1) to 3) below.
The relationship between the duty ratio and the frame frequency is as follows:
Note:
Duty ratio
Frame Frequency
1/9
75.0Hz
1/12
56.3Hz
1/17
79.4Hz
At an oscillation frequency (OSC) of 270 kHz
(1) Driving the LCD of one 24–character line (1/9 duty, CSR = L, AS = 0) under the conditions
of the 1–line display mode and the character font of 5 ¥ 7 dots
COM1
Character
COM8
COM9
Cursor
Arbitrator
SEG1
SEG120
ML9044
• COM10 to COM17 output Display–OFF common signals.
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¡ Semiconductor
ML9044
(2) Driving the LCD of one 24–character line (1/12 duty, CSR = L, AS = 0) under the conditions
of the 1–line display mode and the character font of 5 ¥ 10 dots
COM1
Character
COM11
COM12
Cursor
Arbitrator
SEG1
SEG120
MSM9044
• COM13 to COM17 output Display–OFF common signals.
(3) Driving the LCD of two 24–character line (1/17 duty, CSR = L, AS = 0) under the conditions
of the 2–line display mode and the character font of 5 ¥ 7 dots
COM1
Character
COM8
Cursor
COM9
Character
COM16
COM17
Cursor
Arbitrator
SEG1
SEG120
MSM9044
41/54
¡ Semiconductor
ML9044
EXAMPLES OF VLCD GENERATION CIRCUITS
• With 1/4bias, a built–in contrast adjusting circuit and a voltage multiplier
ML9044
VDD
V1
V2
V3A
V3B
V4
V5
V5IN
VC
VCC
VIN
BEB
Reference potential for
voltage multiplien
• With 1/5 bias, a built–in contrast adjusting circuit and the V5 level input from an external
circuit
ML9044
VDD
V1
V2
V3A
V3B
V4
V5
V5IN
VC
VCC
VIN
BEB
V5 level
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¡ Semiconductor
ML9044
1) COM and SEG Waveforms on 1/9 Duty
8 9 1 2 3 4
COM1 (CSR = L, AS = L)
COM2 (CSR = L, AS = H)
COM9 (CSR = H, AS = L)
COM8 (CSR = H, AS = H)
(first character line)
7 8 9 1 2 3 4
7 8 9 1 2
VDD
V1
V2, V3B
V4
V5
1 frame
COM2 (CSR = L, AS = L)
COM3 (CSR = L, AS = H)
COM8 (CSR = H, AS = L)
COM7 (CSR = H, AS = H)
(second character line)
VDD
V1
V2, V3B
V4
V5
COM8 (CSR = L, AS = L)
COM9 (CSR = L, AS = H)
COM2 (CSR = H, AS = L)
COM1 (CSR = H, AS = H)
(cursor line)
VDD
V1
V2, V3B
V4
V5
COM9 (CSR = L, AS = L)
COM1 (CSR = L, AS = H)
COM1 (CSR = H, AS = L)
COM9 (CSR = H, AS = H)
(arbitrator line)
VDD
V1
V2, V3B
V4
V5
COM10 to
COM17
VDD
V1
V2, V3B
V4
V5
SEG
VDD
V1
V2, V3B
V4
V5
Display
turning-off
waveform
Display
turning-on
waveform
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¡ Semiconductor
ML9044
2) COM and SEG Waveforms on 1/12 Duty
11 12 1 2 3 4 5 6
COM1 (CSR = L, AS = L)
COM2 (CSR = L, AS = H)
COM12 (CSR = H, AS = L)
COM11 (CSR = H, AS = H)
(first character line)
9 10 11 12 1 2 3 4 5 6
VDD
V1
V2, V3B
V4
V5
1 frame
COM2 (CSR = L, AS = L)
COM3 (CSR = L, AS = H)
COM11 (CSR = H, AS = L)
COM10 (CSR = H, AS = H)
(second character line)
VDD
V1
V2, V3B
V4
V5
COM11 (CSR = L, AS = L)
COM12 (CSR = L, AS = H)
COM2 (CSR = H, AS = L)
COM1 (CSR = H, AS = H)
(cursor line)
VDD
V1
V2, V3B
V4
V5
COM12 (CSR = L, AS = L)
COM1 (CSR = L, AS = H)
COM1 (CSR = H, AS = L)
COM12 (CSR = H, AS = H)
(arbitrator line)
VDD
V1
V2, V3B
V4
V5
COM13 to
COM17
VDD
V1
V2, V3B
V4
V5
SEG
VDD
V1
V2, V3B
V4
V5
Display
turning-off
waveform
Display
turning-on
waveform
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¡ Semiconductor
ML9044
3) COM and SEG Waveforms on 1/17 Duty
16 17 1 2 3 4 5 6 7 8 9 10 11 12 13
COM1 (CSR = L, AS = L)
COM2 (CSR = L, AS = H)
COM17 (CSR = H, AS = L)
COM16 (CSR = H, AS = H)
(first character line)
COM2 (CSR = L, AS = L)
COM3 (CSR = L, AS = H)
COM16 (CSR = H, AS = L)
COM15 (CSR = H, AS = H)
(second character line)
COM16 (CSR = L, AS = L)
COM17 (CSR = L, AS = H)
COM2 (CSR = H, AS = L)
COM1 (CSR = H, AS = H)
(corsor line)
COM17 (CSR = L, AS = L)
COM1 (CSR = L, AS = H)
COM1 (CSR = H, AS = L)
COM17 (CSR = H, AS = H)
(arbitrator line)
SEG
VDD
V1
V2
V3A (V3B)
V4
V5
16 17 1 2 3 4
1 frame
VDD
V1
V2
V3A (V3B)
V4
V5
VDD
V1
V2
V3A (V3B)
V4
V5
VDD
V1
V2
V3A (V3B)
V4
V5
VDD
V1
V2
V3A (V3B)
V4
V5
Display
turning-off
waveform
Display
turning-on
waveform
45/54
¡ Semiconductor
ML9044
Initial Setting of Instructions
(a) Data transfer from and to the CPU using 8 bits of DB0 to DB7
1) Turn on the power.
2) Wait for 15 ms or more after VDD has reached 2.5V or higher.
3) Set “8 bits” with the Function Setting instruction.
4) Wait for 4.1 ms or more.
5) Set “8 bits” with the Function Setting instruction.
6) Wait for 100 ms or more.
7) Set “8 bits” with the Function Setting instruction.
8) Check the Busy Flag for No Busy (or wait for 100 ms or more).
9) Set “8 bits”, “Number of LCD lines” and “Font size” with the Function Setting instruction.
(After this, the number of LCD lines and the font size cannot be changed.)
10) Check the Busy Flag for No Busy.
11) Execute the Display Mode Setting Instruction, Display Clear Instruction, Entry Mode
Setting instruction and Arbitrator Display Line Setting Instruction.
12) Check the Busy Flag for No Busy.
13) Initialization is completed.
An example of instruction code for 3), 5) and 7)
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
1
1
¥
¥
¥
¥
¥ : Don't Care
(b) Data transfer from and to the CPU using 8 bits of DB4 to DB7
1) Turn on the power.
2) Wait for 15 ms or more after VDD has reached 2.5V or higher.
3) Set “8 bits” with the Function Setting instruction.
4) Wait for 4.1 ms or more.
5) Set “8 bits” with the Function Setting instruction.
6) Wait for 100 ms or more.
7) Set “8 bits” with the Function Setting instruction.
8) Check the Busy Flag for No Busy (or wait for 100 ms or longer).
9) Set “4 bits” with the Function Setting instruction.
10) Wait for 100 ms or longer.
11) Set “4 bits”, “Number of LCD lines” and “Font size” with the Initial Setting instruction.
(After this, the number of LCD lines and the font size cannot be changed.)
12) Check the Busy Flag for No Busy.
13) Execute the Display Mode Setting Instruction, Display Clear Instruction, Entry Mode
Setting instruction and Arbitrator Display Line Setting Instruction
14) Check the Busy Flag for No Busy.
15) Initialization is completed.
An example of instruction code for 3), 5) and 7)
RS1
RS0
R/W
DB7
DB6
DB5
DB4
1
0
0
0
0
1
1
46/54
¡ Semiconductor
ML9044
An example of instruction code for 9)
RS1
RS0
R/W
DB7
DB6
DB5
DB4
1
0
0
0
0
1
0
*: In 13), check the Busy Flag for No Busy before executing each instruction.
(c) Data transfer from and to the CPU using the serial I/F
1) Turn on the power.
2) Wait for 15 ms or more after VDD has reached 2.5V or higher.
3) Set “Number of LCD lines” and “Font size” with the Function Setting Instruction.
4) Execute the Display Mode Setting Instruction, the Display Clear Instruction, the Entry Mode
Instruction and the Arbitrator Display Line Setting Instruction.
5) Check the busy flag for No Busy.
6) Initialization is completed.
*: In 3) and 4), check the Busy Flag for No Busy before executing each instruction.
47/54
¡ Semiconductor
ML9044
Relationship Between Character Codes and Character patterns
00H
08H
10H
18H
20H
28H
30H
38H
01H
09H
11H
19H
21H
29H
31H
39H
02H
0AH
12H
1AH
22H
2AH
32H
3AH
03H
0BH
13H
1BH
23H
2BH
33H
3BH
04H
0CH
14H
1CH
24H
2CH
34H
3CH
05H
0DH
15H
1DH
25H
2DH
35H
3DH
06H
0EH
16H
1EH
26H
2EH
36H
3EH
07H
0FH
17H
1FH
27H
2FH
37H
3FH
48/54
¡ Semiconductor
ML9044
40H
48H
50H
58H
60H
68H
70H
78H
41H
49H
51H
59H
61H
69H
71H
79H
42H
4AH
52H
5AH
62H
6AH
72H
7AH
43H
4BH
53H
5BH
63H
6BH
73H
7BH
44H
4CH
54H
5CH
64H
6CH
74H
7CH
45H
4DH
55H
5DH
65H
6DH
75H
7DH
46H
4EH
56H
5EH
66H
6EH
76H
7EH
47H
4FH
57H
5FH
67H
6FH
77H
7FH
49/54
¡ Semiconductor
ML9044
80H
88H
90H
98H
A0H
A8H
B0H
B8H
81H
89H
91H
99H
A1H
A9H
B1H
B9H
82H
8AH
92H
9AH
A2H
AAH
B2H
BAH
83H
8BH
93H
9BH
A3H
ABH
B3H
BBH
84H
8CH
94H
9CH
A4H
ACH
B4H
BCH
85H
8DH
95H
9DH
A5H
ADH
B5H
BDH
86H
8EH
96H
9EH
A6H
AEH
B6H
BEH
87H
8FH
97H
9FH
A7H
AFH
B7H
BFH
50/54
¡ Semiconductor
ML9044
C0H
C8H
D0H
D8H
E0H
E8H
F0H
F8H
C1H
C9H
D1H
D9H
E1H
E9H
F1H
F9H
C2H
CAH
D2H
DAH
E2H
EAH
F2H
FAH
C3H
CBH
D3H
DBH
E3H
EBH
F3H
FBH
C4H
CCH
D4H
DCH
E4H
ECH
F4H
FCH
C5H
CDH
D5H
DDH
E5H
EDH
F5H
FDH
C6H
CEH
D6H
DEH
E6H
EEH
F6H
FEH
C7H
CFH
D7H
DFH
E7H
EFH
F7H
FFH
51/54
¡ Semiconductor
ML9044
PAD CONFIGURATION
Y
Pad Layout
Chip Size
Chip Thickness
Bump Size (1)
Bump Size (2)
: 10.62 ¥ 2.55mm
: 625±20mm
: 72 ¥ 72mm
: 54 ¥ 96mm
63
182
62
183
X
56
189
55
1
Pad Coordinates
Pad
Symbol
X (mm)
Y (mm)
Pad
Symbol
X (mm)
Y (mm)
1
V1
–5103
–1099.8
21
DB3
–1323
–1099.8
2
V2
–4914
–1099.8
22
DB2
–1134
–1099.8
3
V3A
–4725
–1099.8
23
DB1
–945
–1099.8
4
V3B
–4536
–1099.8
24
DB0
–756
–1099.8
5
V4
–4347
–1099.8
25
E
–567
–1099.8
6
V5
–4158
–1099.8
26
R/W
–378
–1099.8
7
V5IN
–3969
–1099.8
27
RS0
–189
–1099.8
8
VCC
–3780
–1099.8
28
RS1
0
–1099.8
9
VC
–3591
–1099.8
29
SO
189
–1099.8
10
VIN
–3402
–1099.8
30
SI
378
–1099.8
11
BEB
–3213
–1099.8
31
SHT
567
–1099.8
12
VDD
–3024
–1099.8
32
CS
756
–1099.8
13
CSR
–2835
–1099.8
33
OSC2
945
–1099.8
14
SSR
–2646
–1099.8
34
OSCR
1134
–1099.8
15
P/S
–2457
–1099.8
35
OSC1
1323
–1099.8
16
VSS
–2268
–1099.8
36
T3
1512
–1099.8
17
DB7
–2079
–1099.8
37
T2
1701
–1099.8
18
DB6
–1890
–1099.8
38
T1
1890
–1099.8
19
DB5
–1701
–1099.8
39
COM1
2079
–1099.8
20
DB4
–1512
–1099.8
40
COM2
2268
–1099.8
52/54
¡ Semiconductor
Pad
Symbol
ML9044
X (mm)
Y (mm)
Pad
Symbol
X (mm)
Y (mm)
41
COM3
2457
–1099.8
81
SEG102
3486
1087.8
42
COM4
2646
–1099.8
82
SEG101
3402
1087.8
43
COM5
2835
–1099.8
83
SEG100
3318
1087.8
44
COM6
3024
–1099.8
84
SEG99
3234
1087.8
45
COM7
3213
–1099.8
85
SEG98
3150
1087.8
46
COM8
3402
–1099.8
86
SEG97
3066
1087.8
47
COM9
3591
–1099.8
87
SEG96
2982
1087.8
48
COM10
3780
–1099.8
88
SEG95
2898
1087.8
49
COM11
3969
–1099.8
89
SEG94
2814
1087.8
50
COM12
4158
–1099.8
90
SEG93
2730
1087.8
51
COM13
4347
–1099.8
91
SEG92
2646
1087.8
52
COM14
4536
–1099.8
92
SEG91
2562
1087.8
53
COM15
4725
–1099.8
93
SEG90
2478
1087.8
54
COM16
4914
–1099.8
94
SEG89
2394
1087.8
55
COM17
5103
–1099.8
95
SEG88
2310
1087.8
56
DUMMY
5184
–720
96
SEG87
2226
1087.8
57
DUMMY
5184
–480
97
SEG86
2142
1087.8
58
DUMMY
5184
–240
98
SEG85
2058
1087.8
59
DUMMY
5184
0
99
SEG84
1974
1087.8
60
DUMMY
5184
240
100
SEG83
1890
1087.8
61
DUMMY
5184
480
101
SEG82
1806
1087.8
62
DUMMY
5184
720
102
SEG81
1722
1087.8
63
SEG120
4998
1087.8
103
SEG80
1638
1087.8
64
SEG119
4914
1087.8
104
SEG79
1554
1087.8
65
SEG118
4830
1087.8
105
SEG78
1470
1087.8
66
SEG117
4746
1087.8
106
SEG77
1386
1087.8
67
SEG116
4662
1087.8
107
SEG76
1302
1087.8
68
SEG115
4578
1087.8
108
SEG75
1218
1087.8
69
SEG114
4494
1087.8
109
SEG74
1134
1087.8
70
SEG113
4410
1087.8
110
SEG73
1050
1087.8
71
SEG112
4326
1087.8
111
SEG72
966
1087.8
72
SEG111
4242
1087.8
112
SEG71
882
1087.8
73
SEG110
4158
1087.8
113
SEG70
798
1087.8
74
SEG109
4074
1087.8
114
SEG69
714
1087.8
75
SEG108
3990
1087.8
115
SEG68
630
1087.8
76
SEG107
3906
1087.8
116
SEG67
546
1087.8
77
SEG106
3822
1087.8
117
SEG66
462
1087.8
78
SEG105
3738
1087.8
118
SEG65
378
1087.8
79
SEG104
3654
1087.8
119
SEG64
294
1087.8
80
SEG103
3570
1087.8
120
SEG63
210
1087.8
53/54
¡ Semiconductor
Pad
Symbol
ML9044
X (mm)
Y (mm)
Pad
Symbol
X (mm)
Y (mm)
121
SEG62
126
1087.8
156
SEG27
–2814
1087.8
122
SEG61
42
1087.8
157
SEG26
–2898
1087.8
123
SEG60
–42
1087.8
158
SEG25
–2982
1087.8
124
SEG59
–126
1087.8
159
SEG24
–3066
1087.8
125
SEG58
–210
1087.8
160
SEG23
–3150
1087.8
126
SEG57
–294
1087.8
161
SEG22
–3234
1087.8
127
SEG56
–378
1087.8
162
SEG21
–3318
1087.8
128
SEG55
–462
1087.8
163
SEG20
–3402
1087.8
129
SEG54
–546
1087.8
164
SEG19
–3486
1087.8
130
SEG53
–630
1087.8
165
SEG18
–3570
1087.8
131
SEG52
–714
1087.8
166
SEG17
–3654
1087.8
132
SEG51
–798
1087.8
167
SEG16
–3738
1087.8
133
SEG50
–882
1087.8
168
SEG15
–3822
1087.8
134
SEG49
–966
1087.8
169
SEG14
–3906
1087.8
135
SEG48
–1050
1087.8
170
SEG13
–3990
1087.8
136
SEG47
–1134
1087.8
171
SEG12
–4074
1087.8
137
SEG46
–1218
1087.8
172
SEG11
–4158
1087.8
138
SEG45
–1302
1087.8
173
SEG10
–4242
1087.8
139
SEG44
–1386
1087.8
174
SEG9
–4326
1087.8
140
SEG43
–1470
1087.8
175
SEG8
–4410
1087.8
141
SEG42
–1554
1087.8
176
SEG7
–4494
1087.8
142
SEG41
–1638
1087.8
177
SEG6
–4578
1087.8
143
SEG40
–1722
1087.8
178
SEG5
–4662
1087.8
144
SEG39
–1806
1087.8
179
SEG4
–4746
1087.8
145
SEG38
–1890
1087.8
180
SEG3
–4830
1087.8
146
SEG37
–1974
1087.8
181
SEG2
–4914
1087.8
147
SEG36
–2058
1087.8
182
SEG1
–4998
1087.8
148
SEG35
–2142
1087.8
183
DUMMY
–5184
720
149
SEG34
–2226
1087.8
184
DUMMY
–5184
480
150
SEG33
–2310
1087.8
185
DUMMY
–5184
240
151
SEG32
–2394
1087.8
186
DUMMY
–5184
0
152
SEG31
–2478
1087.8
187
DUMMY
–5184
–240
153
SEG30
–2562
1087.8
188
DUMMY
–5184
–480
154
SEG29
–2646
1087.8
189
DUMMY
–5184
–720
155
SEG28
–2730
1087.8
54/54
E2Y0002-29-62
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
9.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan