OKI ML9042

OKI Semiconductor
ML9042-xx
FEDL9042-01
Issue Date: Nov. 19, 2003
DOT MATRIX LCD CONTROLLER DRIVER
GENERAL DESCRIPTION
The ML9042 used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type
dot matrix LCD.
FEATURES
•
•
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•
•
•
•
•
•
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•
Easy interfacing with an 8-bit or 4-bit microcontroller
Switchable between serial and parallel interfaces
Dot-matrix LCD controller driver for a 5 × 8 dot font
Built-in circuit allowing automatic resetting at power-on
Built-in 17 common signal drivers and 100 segment signal drivers
Two built-in character generator ROMs each capable of generating 240 characters (5 × 8 dots)
The character generator ROM can be selected by bank switching (ROM1S) pin.
Creation of character patterns by programming: up to 8 character patterns (5 × 8 dots)
Built-in RC oscillation circuit using external or internal resistors
Program-selectable duties
When ABE bit is “L”: 1/8 duty (1 line: 5 × 8 dots), or 1/16 duty (2 lines: 5 × 8 dots)
When ABE bit is “H”: 1/9 duty (1 line: 5 × 8 dots + arbitrator), or 1/17 duty (2 lines: 5 × 8 dots + arbitrator)
Cursor display
Built-in bias dividing resistors to drive the LCD
Bi-directional transfer of segment outputs
Bi-directional transfer of common outputs
100-dot arbitrator display
Line display shifting
Built-in voltage multiplier circuit
Gold Bump Chip
ML9042-xx CVWA/DVWA
*xx indicates a character generator ROM code number.
*01, 11 and 21 indicate general character generator ROM code numbers.
CVWA indicates a bump chip with high hardness, and DVWA indicates a bump chip with low
hardness.
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4
LCD bias
voltage
dividing
circuit
Test
circuit
8
8
8
8
VCC VC
Address
counter
(ADC)
8
Instruction
decoder
(ID)
BE
Expansion
instruction
register (ED)
VIN
Voltage
multiplier
circuit
Expansion
instruction
register (ER)
Busy flag
(BF)
Data
register
(DR)
Instruction
register
(IR)
7
Arbitrator RAM
(AB RAM)
Display data RAM
(DD RAM)
8
8
RAM
(CG RAM)
Character
generator
Cursor
blink
controller
5
5
ROM1S
ROM
(CG ROM)
Character
generator
5
17-bit
shift register
bi-directional
Common
signal
driver
SEG100
SEG1
COM17
COM1
OKI Semiconductor
VOUT
V0
V4
V3B
V3A
V2
V1
T3
T1
T2
DB4 to DB7
4
I/O
Buffer
8
Timing
generator
Parallelserial converter
DB0(SO) to
DB3
RS0/CSB
RW/SI
E/SHTB
SP
RS1
OSC2
OSCR5
OSCR3
OSC1
VDD
GND
FEDL9042-01
ML9042-xx
BLOCK DIAGRAM
Segment Signal driver
100-bit latch
100-bit bi-directional shift register
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ML9042-xx
I/O CIRCUITS
VDD
VDD
VDD
P
P
N
N
Applied to pins T1, T2, and T3
Applied to pins RW/SI, RS1, and
RS0/CSB
Applied to pins E/SHTB, SP, ROM1S, and BE
VDD
P
VDD
P
VDD
N
P
N
Output Enable signal
Applied to pins DB0(SO) to DB7
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PIN DESCRIPTIONS
Symbol
RW/SI
Description
The input pin with a pull-up resistor to select Read (“H”) or Write (“L”) in the Parallel I/F
Mode.
The pin to input data in the Serial l/F Mode. Each instruction code and each data are
read in by the rising edge of the E/SHTB signal.
The input pins with a pull-up resistor to select a register in the Parallel l/F Mode.
RS0/CSB, RS1
RS1
RS0/CSB
Name of register
H
H
H
L
Instruction register
L
L
Expansion Instruction register
Data register
The RSo/CSB pin is configured as a chip enable input in the Serial I/F Mode. Setting
the RSo/CSB pin to “L” allows the I/F to be provided.
The input pin for data input/output between the CPU and the ML9042 and for
activating instructions in the Parallel l/F Mode.
E/SHTB
This pin is configured as a shift clock input in the Serial I/F Mode. The data input to the
PW/SI pin is synchronized to the rising edge of the clock, and the data output from the
DB0(SO) pin is synchronized to the falling edge of the shift clock.
The input/output pins to transfer data of lower-order 4 bits between the CPU and the
ML9042 in the Parallel l/F Mode. The pins are not used for the 4-bit interface.
DB0(SO) to DB3
Only the DB0(SO) pin is configured as a data output in the Serial I/F Mode. Busy flag
& address and data are output synchronized to the falling edge of the E/SHTB signal.
These pins remain pulled up when data is not output.
Each pin is equipped with a pull-up resistor, so this pin should be open when not used.
DB4 to DB7
The input/output pins to transfer data of upper 4 bits between the CPU and the
ML9042 in the Parallel l/F Mode. The pins are not used for the serial interface.
Each pin is equipped with a pull-up resistor, so this pin should be open in the Serial I/F
Mode when not used.
The clock oscillation pins required for LCD drive signals and the operation of the
ML9042 by instructions sent from the CPU.
To input external clock, the OSC1 pin should be used. The OSCR3, OSCR5, and OSC2
pins should be open.
OSC1
OSC2
OSCR3
OSCR5
To start oscillation with an external resistor, the resistor should be connected between
the OSC1 and OSC2 pins. The OSCR3 and OSCR5 pins should be open.
To start oscillation at 5 V using an internal resistor, the OSC2 and OSCR5 pins should
be short-circuited outside the ML9042. The OSC1 and OSCR3 pins should be open.
To start oscillation at 3 V using an internal resistor, the OSC2 and OSCR3 pins should
be short-circuited outside the ML9042. The OSC1 and OSCR5 pins should be open.
(The OSC2, OSCR3, and OSCR5 pins can also be short-circuited outside the ML9042,
and the OSC1 pin can be open.)
The LCD common signal output pins.
COM1 to COM17
SEG1 to SEG100
For 1/8 duty, non-selectable voltage waveforms are output via COM9 to COM17. For
1/9 duty, non-selectable voltage waveforms are output via COM10 to COM17. For 1/16
duty, a non-selectable voltage waveform is output via COM17.
The LCD segment signal output pins.
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ML9042-xx
Symbol
ROM1S
Description
The input pin to switch the ROM bank. “H” selects ROM1 and “L” selects ROM0.
Switching after power-on is prohibited.
The pins to output bias voltages to the LCD.
V1 , V2, V3A, V3B, V4
For 1/4 bias : The V2 and V3B pins are shorted.
For 1/5 bias : The V3A and V3B pins are shorted.
The input pin to enable or disable the voltage multiplier circuit.
"L" disables the voltage multiplier circuit. "H" enables the voltage multiplier circuit.
BE
TESTIN
TESTOUT
VIN
The voltage multiplier circuit doubles the input voltage between the VIN pin and the
GND pin, and the multiplied voltage referenced to the GND is output to the VOUT pin.
The voltage multiplier circuit can be used only when generating a level higher than the
VDD.
The input pin for test circuits. Normally connect this pin to VDD.
The output pin for the test circuits. Normally leave this pin open.
The pin to input voltage to the voltage multiplier.
The pins to supply the LCD drive voltage.
V0, VOUT
The same potential as the VDD potential is supplied to the VOUT and V0 pins when the
voltage multiplier is not used (BE = “0” or BE = “1”, and the capacitor is not connected
to the VC and VCC pins)
When the voltage multiplier is used (BE = “1”), the multiplied voltage is output to the
VOUT pin, so that the VOUT pin and V0 pin should be connected.
Capacitors for the voltage multiplier should be connected between the GND and the
VOUT pin.
VC
The pin to connect the negative pin of the capacitor for the voltage multiplier. Leave the
pin open when the voltage multiplier circuit is not used.
VCC
The pin to connect the positive pin of the capacitor used for the voltage multiplier.
Leave the pin open when the voltage multiplier circuit is not used.
T 1, T 2, T 3
The input pins for test circuits (normally open). Each of these pins is equipped with a
pull-down resistor, so this pin should be left open.
VDD
The power supply pin.
GND
The ground level input pin.
The input pin to select the serial or parallel interface.
SP
“L” selects the parallel interface.
“H” selects the serial interface.
DUMMYVDD
The output pin to fix the adjacent input pin to the VDD level. Use this pin only for this
purpose.
DUMMYGND
The output pin to fix the adjacent input pin to the GND level. Use this pin only for this
purpose.
DUMMY
NC (No Connection) pin.
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ML9042-xx
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V)
Parameter
Supply Voltage
LCD Driving Voltage
Input Voltage
Storage Temperature
Symbol
Condition
Rating
Unit
Applicable pins
VDD
Ta = 25°C
–0.3 to +6.5
V
VDD
V0, V1, V2,
V3, V4,
Ta = 25°C
–0.3 to +6.5
V
VOUT, V0, V1, V2, V3A, V3B, V4,
GND
VI
Ta = 25°C
–0.3 to VDD+0.3
V
RW/SI, E/SHTB, SP,
RS0/CSB, RS1, BE,
ROM1S, T1 to T3, DB0(SO)
to DB7, VIN
TSTG
—
–55 to +150
°C
—
RECOMMENDED OPERATING CONDITIONS
(GND = 0 V)
Parameter
Supply Voltage
LCD Driving Voltage
Voltage Multipler
Input Voltage
Operating Temperature
Note:
Symbol
Condition
Range
Unit
Applicable pins
VDD
—
2.7 to 5.5
V
VDD
—
2.7 to 5.5
V
VOUT, V0
VMUL
BE = “1”
1.8 to 2.75
V
VIN
Top
—
–40 to +85
°C
—
V0
(See Note)
This voltage should be applied across V0 and GND. The following voltages are output to the V1,
V2, V3A (V3B) and V4 pins:
• 1/4 bias (V2 and V3B are short-circuited)
V1 =3 V0/4 ±0.15 V
V2 = V3B = V0/2 ±0.15 V
V4 = V0/4 ±0.15 V
• 1/5 bias (V3A and V3B are short-circuited)
V1 = 4 V0/5 ±0.15 V
V2 = 3 V0/5 ±0.15 V
V3A = V3B = 2 V0/5 ±0.15 V
V4 = V0/5 ±0.15 V
The voltages at the V0, V1, V2, V3A (V3B), V4 and GND pins should satisfy
V0 > V1 > V2 > V3A (V3B) > V4 > GND
(Higher ←
→ Lower)
* If the chip is attached on a substrate using COG technology, the chip tends to be susceptible
to electrical characteristics of the chip due to trace resistance on the glass substrate. It is
recommended to use the chip by confirming that it operates on the glass substrate properly.
Trace resistance, especially, VDD and VSS trace resistance, between the chip on the LCD
panel and the flexible cable should be designed as low as possible. Trace resistance that
cannot be very well decreased, larger size of the LCD panel, or greater trace capacitance
between the microcontroller and the ML9042 device can cause device malfunction. In order
to avoid the device malfunction, power noise should be reduced by serial interfacing of the
microcontroller and the ML9042 device.
* Do not apply short-circuiting across output pins and across an output pin and an input/output
pin or the power supply pin in the output mode.
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ML9042-xx
ELECTRICAL CHARACTERISTICS
DC Characteristics
(GND = 0 V, VDD = 2.7 to 5.5 V, Ta = –40 to +85°C)
Parameter
“H” Input Voltage
Symbol
Condition
VIH
Min.
Typ.
Max.
0.8VDD
—
VDD
—
“L” Input Voltage
“H” Output Voltage 1
“L” Output Voltage 1
“H” Output Voltage 2
“L” Output Voltage 2
VIL
0.2VDD
—
—
—
—
—
0.1VDD
—
0.1VDD
IOH = –0.1 mA
IOL = +0.1 mA
IOH = –13 µA
IOL = +13 µA
0.9VDD
—
0.9VDD
—
VCH
lOCH = –4 µA
V0–0.3
VCMH
lOCMH = ±4 µA
V0 –GND = 5 V
Note 1
V1–0.3
VCML
lOCML = ±4 µA
VCL
lOCL = +4 µA
GND
VSH
lOSH = –4 µA
V0–0.3
VSMH
lOSMH = ±4 µA
SEG Voltage Drop
Input Current 1
—
VOH1
VOL1
VOH2
VOL2
COM Voltage Drop
Input Leakage Current
0
VSML
lOSML = ±4 µA
VSL
lOSL = +4 µA
| IIL |
| II1 |
V0 –GND = 5 V
Note 1
V4–0.3
V2–0.3
V3–0.3
GND
V0–
0.012
V1±
0.012
V4±
0.012
GND+
0.012
V0–
0.012
V2±
0.012
V3±
0.012
GND+
0.012
Unit
Applicable pin
V
RW/SI,
RS0/CSB, RS1,
E/SHTB,
DB0(SO) to
DB7, SP,
OSC1, BE,
ROM1S
V
DB0(SO) to
DB7
V
OSC2
V
COM1 to
COM17
V
SEG1 to
SEG100
µA
E/SHTB, BE,
SP, VIN
µA
RW/SI,
RS0/CSB, RS1,
DB0(SO) to
DB7
µA
T 1, T 2, T 3
VDD–GND
V0
V1+0.3
V4+0.3
GND+0.3
V0
V2+0.3
V3+0.3
GND+0.3
VDD = 5 V, VI = 5 V or 0 V
—
—
1.0
VDD = 5 V, VI = GND
10
25
61
—
—
2.0
15
45
105
—
—
2.0
—
—
1.2
mA
175
270
400
kHz OSC1, OSC2
VDD = 5 V, VI = VDD,
Excluding current flowing
through the pull-up resistor
and the output driving MOS
VDD = 5 V, VI = VDD
Input Current 2
| II2 |
Supply Current
lDD
VDD = 5 V, VI = GND
Excluding current flowing
through the pull-down resistor
VDD = 5 V
Note 2
Oscillation Frequency
of External Resistor Rf
fosc1
Rf = 85 kΩ±2%
Note 3
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External Clock
Oscillation Frequency of
Internal Resistor Rf
Clock Input
Frequency
Input Clock Duty
Input Clock Rise
Time
Input Clock Fall Time
LCD Bias Resistor
ML9042-xx
fosc2
fin
fduty
VDD = 4.0 to 5.5 V
Ta = -20 to 75°C
OSC1 and OSCR3: Open
OSC2 and OSCR5:
Short-circuited
Note 4
VDD = 2.7 to 3.6 V
Ta = -20 to 75°C
OSC1 and OSCR5: Open
OSC2 and OSCR3:
Short-circuited
Note 4
OSC2, OSCR: Open
Input from OSC1
Note 5
200
270
351
kHz
OSC1, OSC2,
OSCR5
200
280
364
kHz
OSC1, OSC2,
OSCR3
175
—
400
kHz
45
50
55
%
frf
Note 6
—
—
0.2
µs
fff
Note 6
—
—
0.2
µs
-0x code
1.4
2.0
2.6
kΩ
-1x code
2.8
4.0
5.2
kΩ
-2x code
7.0
10.0
13.0
kΩ
RLB
OSC1
V0, V1, V2, V3A,
V3B, V4, GND
V0, V1, V2, V3A,
V3B, V4, GND
V0, V1, V2, V3A,
V3B, V4, GND
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ML9042-xx
(GND = 0 V, VDD = 2.7 to 5.5 V, Ta = –40 to +85°C)
Parameter
Symbol
Voltage Multiplier
Input Voltage
VMUL
Condition
Note 7
VDD = 2.7 V, VIN = 2.25 V
f = 175 kHz
Voltage Multiplier
Output Voltage
VOUT
Max.
Unit
Applicable
pins
1.8
—
2.75
V
VIN
4.3
—
(VDD–VIN)
×2
V
VOUT
V
V0
VOUT load current = 54 µA
Applied to LCD bias
resistance of 10 kΩ (TYP)
only
Note 1:
Typ.
A capacitor for the voltage
multiplier = 1 to 4.7 µF
BE = “H”
Bias Voltage for
Driving LCD
1/5
bias
Min.
VLCD1
V0–GND
VLCD2
Note 8
1/4
bias
4.3
—
(VDD–VIN)
×2
1/5
bias
2.7
—
5.5
1/4
bias
2.7
—
5.5
Applied to the voltage drop occurring between any of the V0, V1, V4 and GND pins and any of
the common pins (COM1 to COM17) when the current of 4 µA flows in or flows out at one
common pin.
Also applied to the voltage drop occurring between any of the V0, V2, V3A (V3B) and GND pins
and any of the segment pins (SEG1 to SEG100) when the current of 4 µA flows in or flows out at
one segment pin.
The current of 4 µA flows out when the output level is VDD or flows in when the output level is
V5.
Note 2:
Applied to the current flowing into the VDD pin when the external clock (fOSC2 = fin = 270 kHz) is
fed to the internal Rf oscillation or OSC1 under the following conditions:
VDD = V0 = 5 V
GND = 0 V,
V1, V2, V3A (V3B) and V4: Open
E/SHTB and BE: “L” (fixed)
Other input pins: “L” or “H” (fixed)
Other output pins: No load
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Note 3:
Note 4:
OSC1
OSC1
OSCR3
OSCR3
OSCR5
OSCR5
OSC2
OSC2
OSC1
OSCR3
Rf = 85 kΩ±2%
OSCR5
OSC2
The wire between OSC1 and Rf and the wire between The wire between OSCR3 and OSC2, or between OSCR5
OSC2 and Rf should be as short as possible.
and OSC2 should be as short as possible. Keep open
Keep OSCR3 and OSCR5 open.
between OSC1 and OSCR3, or between OSC1 and OSCR5.
Note 5:
tHW
tLW
VDD
VDD
VDD
2
2
2
fIN
waveform
Applied to the pulses entering from the OSC1 pin
fduty = tHW /(tHW + tLW ) ×100 (%)
Note 6:
0.8VDD
0.8VDD
0.2VDD
0.2VDD
trf
tff
Applied to the pulses entering from the OSC1 pin
Note 7:
The maximum value of the voltage multiplier input voltage should be set at 2.75 V, and the
minimum value of the voltage multiplier input voltage should be set by monitoring the voltage
of V0 in actual use so that the voltage multiplier output voltage meets the specification for the
bias voltage for driving LCD after contrast adjustment.
Note 8:
For 1/4 bias, V2 and V3B pins are short-circuited. V3A pin is open.
For 1/5 bias, V3A and V3B pins are short-circuited. V2 pin is open.
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I/O Characteristics
• Parallel Interface Mode
The timing for the input from the CPU and the timing for the output to the CPU are as shown below:
1) WRITE MODE (Timing for input from the CPU)
(VDD = 2.7 to 4.5 V, Ta = –40 to +85°C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
RW/SI, RS0/CSB, RS1 Setup Time
tB
40
—
—
ns
E/SHTB Pulse Width
tW
450
—
—
ns
RW/SI, RS0/CSB, RS1 Hold Time
tA
10
—
—
ns
E/SHTB Rise Time
tr
—
—
125
ns
E/SHTB Fall Time
tf
—
—
125
ns
E/SHTB Pulse Width
tL
430
—
—
ns
E/SHTB Cycle Time
tC
1000
—
—
ns
DB0(SO) to DB7 Input Data Setup Time
tI
195
—
—
ns
DB0(SO) to DB7 Input Data Hold Time
tH
10
—
—
ns
Symbol
Min.
Typ.
Max.
Unit
RW/SI, RS0/CSB, RS1 Setup Time
tB
40
—
—
ns
E/SHTB Pulse Width
tW
220
—
—
ns
RW/SI, RS0/CSB, RS1 Hold Time
tA
10
—
—
ns
E/SHTB Rise Time
tr
—
—
125
ns
(VDD = 4.5 to 5.5 V, Ta = –40 to +85°C)
Parameter
E/SHTB Fall Time
tf
—
—
125
ns
E/SHTB Pulse Width
tL
220
—
—
ns
E/SHTB Cycle Time
tC
500
—
—
ns
DB0(SO) to DB7 Input Data Setup Time
tI
60
—
—
ns
DB0(SO) to DB7 Input Data Hold Time
tH
10
—
—
ns
VIH
VIL
VIH
VIL
RS1, RS0/CSB
RW/SI
VIL
VIL
tr
tB
tL
E/SHTB
VIL
tf
tW
VIH
tA
VIH
VIL
VIL
tI
VIH
VIL
DB0(SO) to DB7
tH
Input
Data
VIH
VIL
tC
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2) READ MODE (Timing for output to the CPU)
(VDD = 2.7 to 4.5 V, Ta = –40 to +85°C)
Symbol
Min.
Typ.
Max.
Unit
RW/SI, RS1, RS0/CSB Setup Time
Parameter
tB
40
—
—
ns
E/SHTB Pulse Width
tW
450
—
—
ns
RW/SI, RS1, RS0/CSB Hold Time
tA
10
—
—
ns
E/SHTB Rise Time
tr
—
—
125
ns
E/SHTB Fall Time
tf
—
—
125
ns
E/SHTB Pulse Width
tL
430
—
—
ns
E/SHTB Cycle Time
tC
1000
—
—
ns
DB0(SO) to DB7 Output Data Delay Time
tD
—
—
350
ns
DB0(SO) to DB7 Output Data Hold Time
tO
20
—
—
ns
Note: A load capacitance of each of DB0(SO) to DB7 must be 50 pF or less.
(VDD = 4.5 to 5.5 V, Ta = –40 to +85°C)
Symbol
Min.
Typ.
Max.
Unit
RW/SI, RS1, RS0/CSB Setup Time
Parameter
tB
40
—
—
ns
E/SHTB Pulse Width
tW
220
—
—
ns
RW/SI, RS1, RS0/CSB Hold Time
tA
10
—
—
ns
E/SHTB Rise Time
tr
—
—
125
ns
E/SHTB Fall Time
tf
—
—
125
ns
E/SHTB Pulse Width
tL
220
—
—
ns
E/SHTB Cycle Time
tC
500
—
—
ns
DB0(SO) to DB7 Output Data Delay Time
tD
—
—
250
ns
DB0(SO) to DB7 Output Data Hold Time
tO
20
—
—
ns
Note: A load capacitance of each of DB0(SO) to DB7 must be 50 pF or less.
RS1, RS0/CSB
VIH
VIL
RW/SI
VIH
VIH
VIL
VIH
tr
tB
tL
E/SHTB
VIL
tW
VIH
tf
tA
VIH
VIL
VIL
tD
tO
0.8VDD Output
0.2VDD Data
DB0(SO) to DB7
0.8VDD
0.2VDD
tC
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• Serial Interface Mode
(VDD = 2.7 to 5.5 V, Ta = –40 to +85°C)
Symbol
Min.
Typ.
Max.
Unit
E/SHTB Cycle Time
Parameter
tSCY
500
—
—
ns
RS0/CSB Setup Time
tCSU
100
—
—
ns
RS0/CSB Hold Time
RS0/CSB “H” Pulse Width
tCH
100
—
—
ns
tCSWH
200
—
—
ns
E/SHTB Setup Time
tSSU
60
—
—
ns
E/SHTB Hold Time
tSH
200
—
—
ns
E/SHTB “H” Pulse Width
tSWH
200
—
—
ns
E/SHTB “L” Pulse Width
tSWL
200
—
—
ns
E/SHTB Rise Time
tSR
—
—
125
ns
E/SHTB Fall Time
tSF
—
—
125
ns
RW/Sl Setup Time
tDISU
100
—
—
ns
RW/Sl Hold Time
tDIH
100
—
—
ns
DB0(SO) Output Data Delay Time
tDOD
—
—
160
ns
DB0(SO) Output Data Hold Time
tCDH
0
—
—
ns
tCSWH
tSCY
RS0/CSB
VIH
tCSU
E/SHTB
RW/SI
VIL
VIL
tSSU
tSWL
VIH
VIL
tDISU
VIH
VIL
tDOD
DB0(SO)
tSR
tSF
tSWH
VIH
tDIH
VIH
tSH
VIH
VIL
VIH
tCH
VIH
VIH
VIL
tDOD
VOL
VIH
tCDH
VOH
VOH
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FUNCTIONAL DESCRIPTION
Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER)
These registers are selected by setting the level of the Register Selection input pins RS0/CSB and RS1. The DR is
selected when both RS0/CSB and RS1 are “H”. The IR is selected when RS0/CSB is “L” and RS1 is “H”. The ER
is selected when both RS0/CSB and RS1 are “L”. (When RS0/CSB is “H” and RS1 is “L”, the ML9042 is not
selected.)
The IR stores an instruction code and sets the address code of the display data RAM (DDRAM) or the character
generator RAM (CGRAM).
The microcontroller (CPU) can write but cannot read the instruction code.
The ER sets the display positions of the arbitrator and the address code of the arbitrator RAM (ABRAM).
The CPU can write but cannot read the display positions of the arbitrator.
The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read from the
DDRAM, ABRAM and CGRAM.
The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or CGRAM.
When an address code is written in the IR or ER, the data of the specified address is automatically transferred from
the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM and CGRAM can be checked
by allowing the CPU to read the data stored in the DR.
After the CPU writes data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is selected
to be ready for the next writing by the CPU. Similarly, after the CPU reads the data in the DR, the data of the next
address in the DDRAM, ABRAM or CGRAM is set in the DR to be ready for the next reading by the CPU.
Writing in or reading from these 3 registers is controlled by changing the status of the RW/SI pin.
Table 1 RW/SI pin status and register operation
RW/SI
RS0/CSB
RS1
Operation
L
L
H
Writing in the IR
H
L
H
Reading the Busy flag (BF) and the address counter (ADC)
L
H
H
Writing in the DR
H
H
H
Reading from the DR
L
L
L
Writing in the ER
H
L
L
Disabled (Not in a busy state, not performing the reads.
Note that the data bus goes into a high impedance state.)
L
H
L
Disabled (Not in a busy state, not performing the writes)
L
Disabled (Not in a busy state, not performing the reads.
Note that the data bus goes into a high impedance state.)
H
H
Busy Flag (BF)
The status “1” of the Busy Flag (BF) indicates that the ML9042 is carrying out internal operation.
When the BF is “1”, any new instruction is ignored.
When RW/SI = “H”, RS0/CSB = “L” and RS1 = “H”, the data in the BF is output to the DB7.
New instructions should be input when the BF is “0”.
When the BF is “1”, the output code of the address counter (ADC) is undefined.
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Address Counter (ADC)
The address counter provides a read/write address for the DDRAM, ABRAM or CGRAM and also provides a
cursor display address.
When an instruction code specifying DDRAM, ABRAM or CGRAM address setting is input to the pre-defined
register, the register selects the specified DDRAM, ABRAM or CGRAM and transfers the address code to the
ADC. The address data in the ADC is automatically incremented (or decremented) by 1 after the display data is
written in or read from the DDRAM, ABRAM or CGRAM.
The data in the ADC is output to DB0(SO) to DB6 when RW/SI = “H”, RS0/CSB = “L”, RS1 = “H” and BF = “0”.
Timing Generator
The timing generator generates timing signals for the internal operation of the ML9042 activated by the instruction
sent from the CPU or for the operation of the internal circuits of the ML9042 such as DDRAM, ABRAM,
CGRAM and CGROM. Timing signals are generated so that the internal operation carried out for LCD displaying
will not be interfered by the internal operation initiated by accessing from the CPU. For example, when the CPU
writes data in the DDRAM, the display of the LCD not corresponding to the written data is not affected.
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Display Data RAM (DDRAM)
This RAM stores the 8-bit character codes (see Table 2).
The DDRAM addresses correspond to the display positions (digits) of the LCD as shown below. The DDRAM
addresses (to be set in the ADC) are represented in hexadecimal.
DB6 DB5 DB4 DB3 DB2 DB1 DB0
ADC
LSB
MSB
Hexadecimal
Hexadecimal
(Example) Representation of DDRAM address = 12
ADC
0
0
1
0
0
1
0
2
1
1) Relationship between DDRAM addresses and display positions (1-line display mode)
Digit
1 2
3 4
5
00 01 02 03 04
Left
end
19 20
Display position
12 13
DD RAM address (hexadecimal)
Right
end
In the 1-line display mode, the ML9042 can display up to 20 characters from digit 1 to digit 20. While the
DDRAM has addresses “00” to “4F” for up to 80 character codes, the area not used for display can be used as a
RAM area for general data. When the display is shifted by instruction, the relationship between the LCD
display position and the DDRAM address changes as shown below:
Digit
1 2
3 4
19 20
(Display shifted to the right) 4F 00 01 02
Digit
1 2
3 4
5
(Display shifted to the left) 01 02 03 04 05
11 12
19 20
13 14
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2) Relationship between DDRAM addresses and display positions (2-line display mode)
In the 2-line mode, the ML9042 can display up to 40 characters (20 characters per line) from digit 1 to digit 20.
Digit
1 2 3 4 5
Line 1 00 01 02 03 04
19 20
12 13
Display position
Line 2 40 41 42 43 44
52 53
address (hexadecimal)
DD RAM
Note: The DDRAM address at digit 20 in the first line is not consecutive to the DDRAM address at
digit 1 in the second line.
When the display is shifted by instruction, the relationship between the LCD display position and the DDRAM
address changes as shown below:
(Display shifted to the right)
(Display shifted to the left)
Digit
1 2 3 4 5
Line 1 27 00 01 02 03
19 20
11 12
Line 2 67 40 41 42 43
51 52
Digit
1 2 3 4 5
Line 1 01 02 03 04 05
19 20
13 14
Line 2 41 42 43 44 45
53 54
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Character Generator ROM (CGROM)
The CGROM generates character patterns (5 × 8 dots, 240 patterns) from the 8-bit character code signals in the
DDRAM. The bank switching pin (ROM1S) can switch to the other ROM that generates character patterns (5 × 8
dots, 240 patterns), allowing a total of 480 characters to be controlled.
When the 8-bit character code corresponding to a character pattern in the CGROM is written in the DDRAM, the
character pattern is displayed in the display position specified by the DDRAM address.
Character codes 10 to FF are contained in the ROM area in the CG ROM.
The general character generator ROM codes are 01/11/21.
The relationship between character codes and general purpose character patterns in Bank0 (ROM0) and Bank1
(ROM1) are indicated in Table 2-1 and Table 2-2, respectively.
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Character Generator RAM (CGRAM)
The CGRAM is used to generate user-specific character patterns that are not in the CGROM. CGRAM (64 bytes =
512 bits) can store up to 8 character patterns (5 × 8 dots) .
When displaying a character pattern stored in the CGRAM, write an 8-bit character code (00 to 07 or 08 to 0F;
hex.) to the DDRAM. This enables outputting the character pattern to the LCD display position corresponding to
the DDRAM address.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the
cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
The following describes how character patterns are written in and read from the CGRAM. (See Tables 2-1 and
2-2.)
(1) A method of writing character patterns to the CGRAM from the CPU
The three CGRAM address bit weights 0 to 2 select one of the lines constituting a character pattern.
First, set the mode to increment or decrement from the CPU, and then input the CGRAM address.
Write each line of the character pattern in the CGRAM through DB0(SO) to DB7.
The data lines DB0(SO) to DB7 correspond to the CGRAM data bit weights 0 to 7, respectively (see Table
3-1). Input data “1” represents the ON status of an LCD dot and “0” represents the OFF status. Since the
ADC is automatically incremented or decremented by 1 after the data is written to the CGRAM, it is not
necessary to set the CGRAM address again.
The bottom line of a character pattern (the CGRAM address bit weights 0 to 2 are all “1”, which means 7
in hexadecimal) is the cursor line. The ON/OFF pattern of this line is ORed with the cursor pattern for
displaying on the LCD. Therefore, the pattern data for the cursor position should be all zeros to display
the cursor.
Whereas the data given by the CGRAM data bit weights 0 to 4 is output to the LCD as display data, the
data given by the CGRAM data bit weights 5 to 7 is not. Therefore, the CGRAM data bit weights 5 to 7
can be used as a RAM area.
(2) A method of displaying CGRAM character patterns on the LCD
The CGRAM is selected when the higher-order 4 bits of a character code are all zeros. Since bit weight 3
of a character code is not used, the character pattern “0” in Table 3-1 can be selected using the character
code “00” or “08” in hexadecimal.
When the 8-bit character code corresponding to a character pattern in the CGRAM is written to the
DDRAM, the character pattern is displayed in the display position specified by the DDRAM address.
(The DDRAM data bit weights 0 to 2 correspond to the CGRAM address bit weights 3 to 5, respectively.)
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Arbitrator RAM (ABRAM)
The arbitrator RAM (ABRAM) stores arbitrator display data.
100 dots can be displayed in both 1-line and 2-line display modes. The arbitrator RAM has the addresses
(hexadecimal) from “00” to “1F” and the valid display address area is from 00 to 19 (0H to 13H). The area of 20 to
31 (14H to 1FH) not used for display can be used as a data RAM area for general data. Even if the display is shifted
by instruction, the arbitrator display is not shifted.
A capacity of 8 bits by 32 addresses (= 256 bits) is available for data write.
First set the mode to increment or decrement from the CPU, and then input the ABRAM address.
Write Display-ON data in the ABRAM through DB0(SO) to DB7.
DB0(SO) to DB7 correspond to the ABRAM data bit weights 0 to 7 respectively. Input data “1” represents the ON
status of an LCD dot and “0” represents the OFF status.
Since ADC is automatically incremented or decremented by 1 after the data is written to the ABRAM, it is not
necessary to set the ABRAM address again.
Whereas ABRAM data bit weights 0 to 4 are output as display data to the LCD, the ABRAM data bit weights 5 to
7 are not. These bits can be used as a RAM area.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the
cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
DB6 DB5 DB4 DB3 DB2 DB1 DB0
ADC
MSB
LSB
Hexadecimal
Hexadecimal
The arbitrator RAM can store a maximum of 100 dots of the arbitrator Display-ON data in units of 5 dots.
The relationship with the LCD display positions is shown below.
Configuration of input display data
Input data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
*
*
*
Relationship between display-ON
data and segment pins
5XSn+1
5XSn+5
E4 E3 E2 E1 E0
* Don’t Care
Display - ON data
E4
E0
Sn = ABRAM address (0 to 19)
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Note: The same CGRAM character patterns are displayed in Bank0 and Bank1.
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Table 3-1
ML9042-xx
Relationship between CGRAM address bits, CGRAM data bits (character pattern)
and DDRAM data bits (character code) in 5 × 7 dot character mode. (Examples)
CG RAM CG RAM data
DD RAM data
address
(Character pattern)
(Character code)
5 4 3 2 1 0 76543210 76543210
MSB
LSB MSB
LSB MSB
LSB
0 0 0 0 0 0 ××× 0 1 1 1 0
10001
0 0 1
10001
0 1 0
10001
0 1 1
1 0 0
10001
0000×000
1 0 1
10001
1 1 0
01110
1 1 1
00000
×××
10001
0 0 1 0 0 0
10010
0 0 1
10100
0 1 0
11000
0 1 1
10100
0000×001
1 0 0
10010
1 0 1
1 1 0
10001
1 1 1
0 0 0 0 0
1 1 1 0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 ×××
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0000×111
×: Don’t Care
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Cursor/Blink Control Circuit
This circuit generates the cursor and blink of the LCD.
The operation of this circuit is controlled by the program of the CPU.
The cursor/blink display is carried out in the position corresponding to the DDRAM address set in the ADC
(Address Counter).
For example, when the ADC stores a value of “07” (hexadecimal), the cursor or blink is displayed as follows:
DB6
ADC
0
DB0
0 0
0
0
Digit
1 2
In 1-line display mode
1 1 1
7
9
19 20
00 01 02 03 04 05 06 07 08
12 13
3 4
5 6 7
8
Cursor/blink position
Digit
1 2
In 2-line display mode
9
19 20
00 01 02 03 04 05 06 07 08
12 13
Second line 40 41 42 43 44 45 46 47 48
52 53
First line
3 4
5 6 7
8
Cursor/blink position
Note:
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in
the ADC. Therefore, the cursor or blink display should be inhibited while the ADC is
holding a CGRAM or ABRAM address.
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LCD Display Circuit (COM1 to COM17, SEG1 to SEG100, SSR and CSR)
The ML9042 has 17 common signal outputs and 100 segment signal outputs to display 20 characters (in the 1-line
display mode) or 40 characters (in the 2-line display mode).
The character pattern is converted into serial data and transferred in series through the shift register.
The transfer direction of serial data is determined by the SSR bit. The shift direction of common signals is
determined by the CSR bit. The following tables show the transfer and shift directions:
SSR bit
Transfer direction
L
SEG1 → SEG100
H
SEG100 → SEG1
ABE bit
CSR bit
duty
AS bit
Shift Direction
Arbitrator’s common pin
L
L
1/8
L
COM1→COM8
None
L
L
1/8
H
COM1→COM8
None
L
L
1/16
L
COM1→COM16
None
L
L
1/16
H
COM1→COM16
None
L
H
1/8
L
COM8→COM1
None
L
H
1/8
H
COM8→COM1
None
L
H
1/16
L
COM16→COM1
None
L
H
1/16
H
COM16→COM1
None
H
L
1/9
L
COM1→COM9
COM9
H
L
1/9
H
COM1→COM9
COM1
H
L
1/17
L
COM1→COM17
COM17
H
L
1/17
H
COM1→COM17
COM1
H
H
1/9
L
COM9→COM1
COM1
H
H
1/9
H
COM9→COM1
COM9
H
H
1/17
L
COM17→COM1
COM1
H
H
1/17
H
COM17→COM1
COM17
* Refer to the Expansion Instruction Codes section about the ABE bit, SSR bit, CSR bit, and AS bit.
Signals to be input to the SSR bit, CSR bit, ABE bit, and AS bit should be initially determined at power-on and be
kept unchanged.
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Built-in Reset Circuit
The ML9042 is automatically initialized when the power is turned on.
During initialization, the Busy Flag (BF) is “1” and the ML9042 does not accept any instruction from the CPU
(other than the Read BF instruction).
The Busy Flag is “1” for about 15 ms after the VDD becomes 2.7 V or higher.
During this initialization, the ML9042 performs the following instructions:
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
11)
12)
Display clearing
CPU interface data length = 8 bits
1-line LCD display
ADC counting = Increment
Display shifting = None
Display = Off
Cursor = Off
Blinking = Off
Arbitrator = Displayed in the lower line
Arbitrator = Not displayed
Segment shift direction = SEG1 → SEG100
Common shift direction = COM1 → COM17
(DL = “1”)
(N = “0”)
(I/D = “1”)
(S = “0”)
(D = “0”)
(C = “0”)
(B = “0”)
(AS = “0”)
(ABE = “0”)
(SSR = “0”)
(CSR = “0”)
To use the built-in reset circuit, the power supply conditions shown below should be satisfied. Otherwise, the
built-in reset circuit may not work properly. In such a case, initialize the ML9042 with the instructions from the
CPU. The use of a battery always requires such initialization from the CPU. (See “Initial Setting of Instructions”)
2.7 V
0.2 V
0.2 V
tON
0.2 V
tOFF
0.1 ms ≤ tON ≤100 ms
1 ms ≤ tOFF
Figure 1 Power-on and Power-off Waveform
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I/F with CPU
Parallel interface mode
The ML9042 can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any 8-bit or 4-bit
microcontroller (CPU).
1) 8-bit interface data length
The ML9042 uses all of the 8 data bus lines DB0(SO) to DB7 at a time to transfer data to and from the CPU.
2) 4-bit interface data length
The ML9042 uses only the higher-order 4 data bus lines DB4 to DB7 twice to transfer 8-bit data to and from the
CPU.
The ML9042 first transfers the higher-order 4 bits of 8-bit data (DB4 to DB7 in the case of 8-bit interface data
length) and then the lower-order 4 bits of the data (DB0(SO) to DB3 in the case of 8-bit interface data length).
The lower-order 4 bits of data should always be transferred even when only the transfer of the higher-order 4
bits of data is required. (Example: Reading the Busy Flag)
Two transfers of 4 bits of data complete the transfer of a set of 8-bit data. Therefore, when only one access is
made, the following data transfer cannot be completed properly.
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RS1
RS0/CSB
RWB/SI
E/SHTB
Busy
(Internal operation)
No
Busy
DR7
IR6
ADC6
DR6
DB5
IR5
ADC5
DR5
DB4
IR4
ADC4
DR4
DB3
IR3
ADC3
DR3
DB2
IR2
ADC2
DR2
DB1
IR1
ADC1
DR1
IR0
ADC0
DR0
DB7
IR7
DB6
DB0/(SO)
Writing In IR
(Instruction
Register)
Busy
Reading BF (Busy Flag)
and ADC (Address Counter)
Writing In DR
(Data Register)
Figure 2 8-Bit Data Transfer
RS1
RS0/CSB
RWB/SI
E/SHTB
Busy
(Internal operation)
DB7
No
Busy
ADC3
DR7
DR3
IR2
ADC6
ADC2
DR6
DR2
IR5
IR1
ADC5
ADC1
DR5
DR1
IR4
IR0
ADC4
ADC0
DR4
DR0
IR7
IR3
DB6
IR6
DB5
DB4
Writing In IR
(Instruction
Register)
Busy
Reading BF (Busy Flag)
and ADC (Address Counter)
Writing In DR
(Data Register)
Figure 3 4-Bit Data Transfer
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Serial Interface Mode
In the Serial I/F Mode, the ML9042 interfaces with the CPU via the RS0/CSB, E/SHTB, RW/SI, and DB0(SO)
pins.
Writing and reading operations are executed in units of 16 bits after the RS0/CSB signal falls down. If the RS0/CSB
signal rises up before the completion of 16-bit unit access, this access is ignored.
When the BF bit is “1”, the ML9042 cannot accept any other instructions. Before inputting a new instruction,
check that the BF bit is “0”. Any access when the BF bit is “1” is ignored.
Data format is LSB-first.
Examples of Access in the Serial I/F Mode
1) WRITE MODE
RS0/CSB
1
2
3
4
5
6
1
1
1
1
1
R/W
1
2
3
4
5
6
1
1
1
1
R/W
7
8
9
10
11
12
13
14
15
16
1
E/SHTB
BUSY
(Internal operation)
RWB/SI
RS0 RS1
D0
7
9
D1
D2
D3
D4
D5
D6
D7
1
DB(SO)
2) READ MODE
RS0/CSB
8
10
11
12
13
14
15
16
1
E/SHTB
BUSY
(Internal operation)
RWB/SI
DB(SO)
1
RS0 RS1
1
D0
D1
D2
D3
D4
D5
D6
D7
Note 1: Higher 5 bits of each instruction must be input at a “H” level.
Note 2: Lower 8 bits are “don’t care” when the instructions in the READ MODE are set.
Note 3: After one instruction is input, the next instruction must be input after the RS0/CSB pin is pulled at a “H”
level.
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Instruction Codes
Table of Instruction Codes
Instruction
Code
DB0
RS0/ RW/
DB7 DB6 DB5 DB4 DB3 DB2 DB1
RS1
CSB SI
(SO)
Display Clear
1
0
0
0
0
0
Cursor Home
1
0
0
0
0
0
Entry Mode
Setting
1
0
0
0
0
0
Display
1
ON/OFF Control
0
0
0
0
0
Cursor/Display
Shift
1
0
0
0
0
0
Function Setting 1
0
0
0
0
1
CGRAM
Address Setting
1
0
0
0
1
DDRAM
Address Setting
1
0
0
1
Busy Flag/
Address Read
1
0
1
BF
RAM Data Write 1
1
0
RAM Data Read 1
1
1
Arbitrator
0
Display Line Set
0
0
0
0
0
ABRAM
Address Setting
0
0
0
1
1
0
Function
Execution
Time
f = 270 kHz
Clears all the displayed digits of the
LCD and sets the DDRAM address 00
1.52 ms
in the address counter. The arbitrator
data is cleared.
Sets the DDRAM address 00 in the
address counter and shifts the display
0
0
0
1
X
1.52 ms
back to the original. The content of the
DDRAM remains unchanged.
Determines the direction of movement
of the cursor and whether or not to shift
37 µs
0
0
1
I/D
S
the display. This instruction is
executed when data is written or read.
Sets LCD display ON/OFF (D), cursor
37 µs
0
1
D
C
B ON/OFF (C) or cursor-position
character blinking ON/OFF (B).
Moves the cursor or shifts the display
1 S/C R/L X
X without changing the content of the
37 µs
DDRAM.
Sets the interface data length (DL), the
number of display lines (N), the
37 µs
DL N ABE SSR CSR arbitrator display (ABE), the segment
data shift direction (SSR), or the
common data shift direction (CSR).
Sets on CGRAM address. After that,
37 µs
ACG
CGRAM data is transferred to and from
the CPU.
Sets a DDRAM address. After that,
ADD
DDRAM data is transferred to and from
37 µs
the CPU.
Reads the Busy Flag (indicating that
0 µs
ADC
the ML9042 is operating) and the
content of the address counter.
Writes data in DDRAM, ABRAM or
WRITE DATA
37 µs
CGRAM.
Reads data from DDRAM, ABRAM or
READ DATA
37 µs
CGRAM.
0
0
0
0
0
0
0
1
AAB
1
AS Sets the arbitrator display line.
Sets an ABRAM address. After that,
ABRAM data is transferred to and from
the CPU.
37 µs
37 µs
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—
I/D = “1” (Increment)
I/D = “0” (Decrement)
S = “1” (Shifts the display.)
S/C = “1” (Shifts display.)
S/C = “0” (Moves the cursor.)
R/L = “1” (Right shift)
R/L = “0” (Left shift)
D/L = “1” (8-bit data)
DL = “0” (4-bit data)
N = “1” (2 lines)
N = “0” (1 line)
ABE = “1” (Arbitrator displayed)
ABE = “0” (Arbitrator not displayed)
SSR = “1” (Transfer direction: SEG100 → SEG1)
SSR = “0” (Transfer direction: SEG1 → SEG100)
CSR = “1” (Transfer direction: COMn → COM1)
CSR = “0” (Transfer direction: COM1 → COMn)
BF = “1” (Busy)
BF = “0” (Ready to accept
an instruction)
B = “1” (Enables blinking)
C = “1” (Displays the cursor.)
D = “1” (Displays a character pattern.)
AS = “1” (Arbitrator Displays AS = “0” (Arbitrator Displays
arbitrator on the
arbitrator on the
upper line)
lower line)
ML9042-xx
DD RAM:
CG RAM:
ABRAM:
ACG:
ADD:
AAB:
ADC:
Display data RAM
Character generator RAM
Arbitrator data RAM
CGRAM address
DDRAM address
(Corresponds to the cursor
address)
ABRAM address
Address counter (Used by
DDRAM, ABRAM and
CGRAM)
The
execution
time is
dependent
upon
frequencies.
×: Don't Care
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Instruction Codes
An instruction code is a signal sent from the CPU to access the ML9042. The ML9042 starts operation as
instructed by the code received. The busy status of the ML9042 is rather longer than the cycle time of the CPU,
since the internal processing of the ML9042 starts at a timing which does not affect the display on the LCD. In the
busy status (Busy Flag is “1”), the ML9042 cannot input the Busy Flag Read instruction only. Therefore, the CPU
should ensure that the Busy Flag is “0” before sending an instruction code to the ML9042.
1) Display Clear
Instruction Code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
0
0
0
1
When this instruction is executed, the LCD display including arbitrator display is cleared and the I/D entry
mode is set to “Increment”. The value of “S” (Display shifting) remains unchanged. The position of the cursor
or blink being displayed moves to the left end of the LCD (or the left end of the line 1 in the 2-line display
mode).
Note:
All DDRAM and ABRAM data turn to “20” and “00” in hexadecimal, respectively. The value of the
address counter (ADC) turns to the one corresponding to the address “00” (hexadecimal) of the
DDRAM.
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.
2) Cursor Home
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
0
0
1
×
×: Don’t Care
When this instruction is executed, the cursor or blink position moves to the left end of the LCD (or the left end
of line 1 in the 2-line display mode). If the display has been shifted, the display returns to the original display
position before shifting.
Note:
The value of the address counter (ADC) goes to the one corresponding to the address “00”
(hexadecimal) of the DDRAM).
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.
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3) Entry Mode Setting
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
0
1
I/D
S
(1) When the I/D is set, the cursor or blink shifts to the right by 1 character position (ID= “1”; increment) or to
the left by 1 character position (I/D= “0”; decrement) after an 8-bit character code is written to or read
from the DDRAM. At the same time, the address counter (ADC) is also incremented by 1 (when I/D =
“1”; increment) or decremented by 1 (when I/D = “0”; decrement). After a character pattern is written to
or read from the CGRAM, the address counter (ADC) is incremented by 1 (when I/D = “1”; increment) or
decremented by 1 (when I/D = “0”; decrement).
Also after data is written to or read from the ABRAM, the address counter (ADC) is incremented by 1
(when I/D = “1”; increment) or decremented by 1 (when I/D = “0”; decrement).
(2) When S = “1”, the cursor or blink stops and the entire display shifts to the left (I/D = “1”) or to the right
(I/D = “0”) by 1 character position after a character code is written to the DDRAM.
In the case of S = “1”, when a character code is read from the DDRAM, when a character pattern is
written to or read from the CGRAM or when data is written to or read from the ABRAM, normal
read/write is carried out without shifting of the entire display. (The entire display does not shift, but the
cursor or blink shifts to the right (I/D = “1”) or to the left (I/D = “0”) by 1 character position.)
When S = “0”, the display does not shift, but normal write/read is performed.
Note:
The execution time of this instruction is 37 µs (maximum) at an oscillation frequency of
270 kHz.
4) Display ON/OFF Control
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
1
D
C
B
(1) The “D” bit (DB2) of this instruction determines whether or not to display character patterns on the LCD.
When the “D” bit is “1”, character patterns are displayed on the LCD.
When the “D” bit is “0”, character patterns are not displayed on the LCD and the cursor/blinking also
disappear.
Note:
Unlike the Display Clear instruction, this instruction does not change the character code in the
DDRAM .
(2) When the “C” bit (DB1) is “0”, the cursor turns off. When both the “C” and “D” bits are “1”, the cursor
turns on.
(3) When the “B” bit (DB0) is “0”, blinking is canceled. When both the “B” and “D” bits are “1”, blinking is
performed.
In the Blinking mode, all dots including those of the cursor, the character pattern and the cursor are
alternately displayed.
Note:
The execution time of this instruction is 37 µs (maximum) at an oscillation frequency of
270 kHz.
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5) Cursor/Display Shift
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
1
S/C
R/L
×
×
×: Don’t Care
S/C = “0”, R/L = “0”
This instruction shifts left the cursor and blink positions by 1 (decrements the
content of the ADC by 1).
This instruction shifts right the cursor and blink positions by 1 (increments the
content of the ADC by 1).
This instruction shifts left the entire display by 1 character position. The cursor
and blink positions move to the left together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)
This instruction shifts right the entire display by 1 character position. The cursor
and blink positions move to the right together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)
S/C = “0”, R/L = “1”
S/C = “1”, R/L = “0”
S/C = “1”, R/L = “1”
In the 2-line mode, the cursor or blink moves from the first line to the second line when the cursor at digit 40
(27; hex) of the first line is shifted right.
When the entire display is shifted, the character pattern, cursor or blink will not move between the lines (from
line 1 to line 2 or vice versa).
Note:
The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
6) Function Setting
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
1
DL
N
ABE
SSR
CSR
×: Don’t Care
(1) When the “DL” bit (DB4) of this instruction is “1”, the data transfer to and from the CPU is performed
once by the use of 8 bits DB7 to DB0.
When the “DL” bit (DB4) of this instruction is “0”, the data transfer to and from the CPU is performed
twice by the use of 4 bits DB7 to DB4.
(2) The 2-line display mode is selected when the “N” bit (DB3) of this instruction is “1”. The 1-line display
mode is selected when the “N” bit is “0”.
The arbitrator is displayed when the “ABE” bit (DB2) of this instruction is “1”.
The arbitrator is not displayed when the “ABE” bit (DB2) of this instruction is “0”.
(3) The transfer direction of the segment signal output data is controlled.
When the “SSR” bit (DB1) of this instruction is “1”, the data is transferred from SEG100 to SEG1.
When the “SSR” bit (DB1) of this instruction is “0”, the data is transferred from SEG1 to SEG100.
The transfer direction of the common signal output data is controlled.
At 1/n duty,
When the “CSR” bit (DB0) of this instruction is “1”, the data is transferred from COMn to COM1.
When the “CSR” bit (DB0) of this instruction is “0”, the data is transferred from COM1 to COMn.
After the ML9042 is powered on, this function setting should be carried out before execution of any
instruction except the Busy Flag Read. After this function setting, no instructions other than the DL Set
instruction can be executed. In the Serial I/F Mode, DL setting is ignored.
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N
ABE
Number of
display lines
Font size
Duty
Number of
biases
Number of
common signals
0
0
1
5×8
1/8
4
8
0
1
1
5×8
1/9
4
9
1
0
2
5×8
1/16
5
16
1
1
2
5×8
1/17
5
17
Note:
The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270
kHz.
7) CGRAM Address Setting
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
1
C5
C4
C3
C2
C1
C0
This instruction sets the CGRAM address to the data represented by the bits C5 to C0 (binary).
The CGRAM addresses are valid until DDRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the CGRAM address bits C5 to
C0 set in the instruction code at that time.
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
8) DDRAM Address Setting
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
D6
D5
D4
D3
D2
D1
D0
Instruction code:
This instruction sets the DDRAM address to the data represented by the bits D6 to D0 (binary).
The DDRAM addresses are valid until CGRAM or ABRAM addresses are set.
The CPU writes or reads character codes starting from the one represented by the DDRAM address bits D6 to
D0 set in the instruction code at that time.
In the 1-line mode (the “N” bit is “0”), the DDRAM address represented by bits D6 to D0 (binary) should be in
the range “00” to “4F” in hexadecimal.
In the 2-line mode (the “N” bit is “1”), the DDRAM address represented by bits D6 to D0 (binary) should be in
the range “00” to “27” or “40” to “67” in hexadecimal.
If an address other than above is input, the ML9042 cannot properly write a character code in or read it from the
DDRAM.
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
9) DDRAM/ABRAM/CGRAM Data Write
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
0
E7
E6
E5
E4
E3
E2
E1
E0
A character code (E7 to E0) is written to the DDRAM, Display-ON data (E7 to E0) to the ABRAM or a character
pattern (E7 to E0) to the CGRAM.
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is written, the address counter (ADC) is incremented or decremented as set by the Entry Mode
Setting instruction (see 3).
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
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10) Busy Flag/Address Counter Read (Execution time: 0 µs)
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
BF
O6
O5
O4
O3
O2
O1
O0
The “BF” bit (DB7) of this instruction tells whether the ML9042 is busy in internal operation (BF = “1”) or not
(BF = “0”).
When the “BF” bit is “1”, the ML9042 cannot accept any other instructions. Before inputting a new instruction,
check that the “BF” bit is “0”.
When the “BF” bit is “0”, the ML9042 outputs the correct value of the address counter. The value of the
address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the DDRAM, ABRAM and
CGRAM addresses is set in the counter is determined by the preceding address setting.
When the “BF” bit is “1”, the value of the address counter is not always correct because it may have been
incremented or decremented by 1 during internal operation.
11) DDRAM/ABRAM/CGRAM Data Read
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
1
P7
P6
P5
P4
P3
P2
P1
P0
A character code (P7 to P0) is read from the DDRAM, Display-ON data (P7 to P0) from the ABRAM or a
character pattern (P7 to P0) from the CGRAM.
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is read, the address counter (ADC) is incremented or decremented as set by the Entry Mode Setting
instruction (see 3).
Note: Conditions for reading correct data
(1) The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read instruction is input.
(2) When reading a character code from the DDRAM, the Cursor/Display Shift instruction (see 5) is input
before this Data Read instruction is input.
(3) When two or more consecutive RAM Data Read instructions are executed, the following read data is
correct.
Correct data is not output under conditions other than the cases (1), (2) and (3) above.
Note:
The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
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Expansion Instruction Codes
The busy status of the ML9042 is rather longer than the cycle time of the CPU, since the internal processing of the
ML9042 starts at a timing which does not affect the display on the LCD. In the busy status (Busy Flag is “1”), the
ML9042 executes the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is
“0” before sending an expansion instruction code to the ML9042.
1) Arbitrator Display Line Set
Expansion instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
1
AS
This expansion instruction code sets the Arbitrator display line. The relationship between the status of this bit
and the common outputs is as follows:
For display examples, refer to LCD Drive Waveforms section.
ABE bit
CSR bit
duty
AS bit
Shift direction
Arbitrator’s common pin
L
L
1/8
L
COM1→COM8
None
L
L
1/8
H
COM1→COM8
None
L
L
1/16
L
COM1→COM16
None
L
L
1/16
H
COM1→COM16
None
L
H
1/8
L
COM8→COM1
None
L
H
1/8
H
COM8→COM1
None
L
H
1/16
L
COM16→COM1
None
L
H
1/16
H
COM16→COM1
None
H
L
1/9
L
COM1→COM9
COM9
H
L
1/9
H
COM1→COM9
COM1
H
L
1/17
L
COM1→COM17
COM17
H
L
1/17
H
COM1→COM17
COM1
H
H
1/9
L
COM9→COM1
COM1
H
H
1/9
H
COM9→COM1
COM9
H
H
1/17
L
COM17→COM1
COM1
H
H
1/17
H
COM17→COM1
COM17
Note:
The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of
270 kHz.
2) ABRAM Address Setting
Expansion instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
1
H4
H3
H2
H1
H0
This instruction sets the ABRAM address to the data represented by the bits H4 to H0 (binary).
The ABRAM addresses are valid until CGRAM or DDRAM addresses are set.
The CPU writes or reads the Display-ON data starting from the one represented by the ABRAM address bits H4
to H0 set in the instruction code at that time.
When the ABRAM address represented by bits H4 to H0 (binary) is in the range “00” to “13” in hexadecimal,
data is output to the LCD as the arbitrator.
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
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Examples of Combinations of ML9042 and LCD Panel
(1) Driving the LCD of one 20-character line under the conditions of the 1-line display mode and no arbitrator
display
(1/8 duty, ABE = “0”, AS = “0” or “1”, CSR = “0”, SSR = “1”)
COM1
Character
COM8
SEG100
SEG1
ML9042
• COM9 to COM17 output Display-OFF common signals.
(1/8 duty, ABE = “0”, AS = “0” or “1”, CSR = “1”, SSR = “0”)
ML9042
SEG1
SEG100
COM8
Character
COM1
• COM9 to COM17 output Display-OFF common signals.
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(2) Driving the LCD of one 20-character line under the conditions of the 1-line display mode and the arbitrator
display
(1/9 duty, ABE = “1”, AS = “0”, CSR = “0”, SSH = “1”)
COM1
Character
COM8
COM9
Arbitrator
SEG100
SEG1
ML9042
• COM10 to COM17 output Display-OFF common signals.
(1/9 duty, ABE = “1”, AS = “1”, CSR = “0”, SSR = “1”)
COM1
COM2
Arbitrator
Character
COM9
SEG100
SEG1
ML9042
• COM10 to COM17 output Display-OFF common signals.
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(1/9 duty, ABE = “1”, AS = “0”, CSR = “1”, SSR = “0”)
ML9042
SEG1
SEG100
COM9
Character
COM2
COM1
Arbitrator
• COM10 to COM17 output Display-OFF common signals.
(1/9 duty, ABE = “1”, AS = “1”, CSR = “1”, SSR = “0”)
ML9042
SEG1
Arbitrator
SEG100
COM9
COM8
Character
COM1
• COM10 to COM17 output Display-OFF common signals.
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(3) Driving the LCD of two 20-character lines under the conditions of the 2-line display mode and no arbitrator
display
(1/16 duty, ABE = “0”, AS = “0” or “1”, CSR = “0”, SSR = “1”)
COM1
Character
COM8
COM9
Character
COM16
SEG100
SEG1
ML9042
• COM17 outputs Display-OFF common signal.
(1/16 duty, ABE = “0”, AS = “0” or “1”, CSR = “1”, SSR = “0”)
ML9042
SEG1
SEG100
COM16
Character
COM9
COM8
Character
COM1
• COM17 outputs Display-OFF common signal.
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(4) Driving the LCD of two 20-character lines under the conditions of the 2-line display mode and the arbitrator
display
(1/17 duty, ABE = “1”, AS = “0”, CSR = “0”, SSR = “1”)
COM1
Character
COM8
COM9
Character
COM16
COM17
Arbitrator
SEG100
SEG1
ML9042
(1/17 duty, ABE = “1”, AS = “1”, CSR = “0”, SSR = “1”)
COM1
COM2
Arbitrator
Character
COM9
COM10
Character
COM17
SEG100
SEG1
ML9042
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(1/17 duty, ABE = “1”, AS = “0”, CSR = “1”, SSR = “0”)
ML9042
SEG1
SEG100
COM17
Character
COM10
COM9
Character
COM2
Arbitrator
COM1
(1/17 duty, ABE = “1”, AS = “1”, CSR = “1”, SSR = “0”)
ML9042
SEG1
Arbitrator
SEG100
COM17
COM16
Character
COM9
COM8
Character
COM1
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EXAMPLES OF VLCD GENERATION CIRCUITS
• With 1/4 bias, a voltage multiplier
VDD
ML9042
BE
VIN
VC
VCC
VOUT
V0
V1
V2
V3A
V3B
V4
GND
Reference potential
for voltage multiplier
+
+
• With 1/4 bias, no voltage multiplier
1) Apply VDD to VOUT and V0.
2) Apply VDD to VOUT, and apply the V0 level to V0 externally.
VDD
ML9042
BE
VIN
VC
VCC
VOUT
V0
V1
V2
V3A
V3B
V4
GND
V0 level
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• With 1/5 bias, a voltage multiplier
VDD
ML9042
BE
VIN
VC
VCC
VOUT
V0
V1
V2
V3A
V3B
V4
GND
Reference potential
for voltage multiplier
+
+
• With 1/5 bias, no voltage multiplier
1) Apply VDD to VOUT and V0.
2) Apply VDD to VOUT, and apply the V0 level to V0 externally.
VDD
ML9042
BE
VIN
VC
VCC
VOUT
V0
V1
V2
V3A
V3B
V4
GND
V0 level
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LCD Drive Waveforms
The COM and SEG waveforms (AC signal waveforms for display) vary according to the duty (1/9 and 1/17 duties).
See 1) and 2) below.
The relationship between the duty ratio and the frame frequency is as follows:
Duty ratio
Frame Frequency
1/8
84.4 Hz
1/9
75.0 Hz
1/16
84.4 Hz
1/17
79.4 Hz
Note: At an oscillation frequency (OSC) of 270 kHz
1) COM and SEG Waveforms on 1/9 Duty (ABE = “1”)
COM1 (CSR = “L”, AS = “L”)
COM2 (CSR = “L”, AS = “H”)
COM9 (CSR = “H”, AS = “L”)
COM8 (CSR = “H”, AS = “H”)
(first character line)
CSR=“H”
2 1 9 8 7 6 ··· 3 2 1 9 8 7 6 ··· 3 2 1 9 8
CSR=“L”
V0
V1
V2, V3B
V4
V5
8 9 1 2 3 4 ··· 7 8 9 1 2 3 4 ··· 7 8 9 1 2
1 frame
COM2 (CSR = “L”, AS = “L”)
COM3 (CSR = “L”, AS = “H”)
COM8 (CSR = “H”, AS = “L”)
COM7 (CSR = “H”, AS = “H”)
(second character line)
V0
V1
V2, V3B
V4
V5
COM8 (CSR = “L”, AS = “L”)
COM9 (CSR = “L”, AS = “H”)
COM2 (CSR = “H”, AS = “L”)
COM1 (CSR = “H”, AS = “H”)
(eighth character line)
V0
V1
V2, V3B
V4
V5
COM9 (CSR = “L”, AS = “L”)
COM1 (CSR = “L”, AS = “H”)
COM1 (CSR = “H”, AS = “L”)
COM9 (CSR = “H”, AS = “H”)
(arbitrator line)
V0
V1
V2, V3B
V4
V5
COM10 to
COM17
V0
V1
V2, V3B
V4
V5
Display
turning-off
waveform
SEG
V0
V1
V2, V3B
V4
V5
Display
turning-on
waveform
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FEDL9042-01
OKI Semiconductor
ML9042-xx
2) COM and SEG Waveforms on 1/17 Duty (ABE = “1”)
CSR=“H”
COM1 (CSR = “L”, AS = “L”)
COM2 (CSR = “L”, AS = “H”)
COM17 (CSR = “H”, AS = “L”)
COM16 (CSR = “H”, AS = “H”)
(first character line)
COM2 (CSR = “L”, AS = “L”)
COM3 (CSR = “L”, AS = “H”)
COM16 (CSR = “H”, AS = “L”)
COM15 (CSR = “H”, AS = “H”)
(second character line)
COM16 (CSR = “L”, AS = “L”)
COM17 (CSR = “L”, AS = “H”)
COM2 (CSR = “H”, AS = “L”)
COM1 (CSR = “H”, AS = “H”)
(sixteenth character line)
COM17 (CSR = “L”, AS = “L”)
COM1 (CSR = “L”, AS = “H”)
COM1 (CSR = “H”, AS = “L”)
COM17 (CSR = “H”, AS = “H”)
(arbitrator line)
2 1 17 16 15 14 13 12 11 10 9 8 7 6 5 ··· 2 1 17 16 15 14
CSR=“L” 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 ··· 16 17 1 2 3 4
V0
V1
V2
V3A (V3B)
V4
V5
1 frame
V0
V1
V2
V3A (V3B)
V4
V5
V0
V1
V2
V3A (V3B)
V4
V5
V0
V1
V2
V3A (V3B)
V4
V5
Display
turning-off
waveform
SEG
V0
V1
V2
V3A (V3B)
V4
V5
Display
turning-on
waveform
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FEDL9042-01
OKI Semiconductor
ML9042-xx
Initial Setting of Instructions
(a)
Data transfer from and to the CPU using 8 bits of DB0 to DB7
1) Turn on the power.
2) Wait for 15 ms or more after VDD has reached 2.7 V or higher.
3) Set “8 bits” with the Function Setting instruction.
4) Wait for 4.1 ms or more.
5) Set “8 bits” with the Function Setting instruction.
6) Wait for 100 µs or more.
7) Set “8 bits” with the Function Setting instruction.
8) Check the Busy Flag for No Busy (or wait for 100 µs or more).
9) Set “8 bits”, “Number of LCD lines” and “Font size” with the Function Setting instruction.
(After this, the number of LCD lines and the font size cannot be changed.)
10) Check the Busy Flag for No Busy.
11) Execute the Display ON/OFF control Instruction, Display Clear Instruction, Entry Mode Setting
instruction and Arbitrator Display Line Setting Instruction.
12) Check the Busy Flag for No Busy.
13) Initialization is completed.
An example of instruction code for 3), 5) and 7)
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
1
1
×
×
×
×
×: Don’t Care
(b) Data transfer from and to the CPU using 4 bits of DB4 to DB7
1) Turn on the power.
2) Wait for 15 ms or more after VDD has reached 2.7 V or higher.
3) Set “8 bits” with the Function Setting instruction.
4) Wait for 4.1 ms or more.
5) Set “8 bits” with the Function Setting instruction.
6) Wait for 100 µs or more.
7) Set “8 bits” with the Function Setting instruction.
8) Check the Busy Flag for No Busy (or wait for 100 µs or longer).
9) Set “4 bits” with the Function Setting instruction.
10) Wait for 100 µs or longer.
11) Set “4 bits”, “Number of LCD lines” and “Font size” with the Function Setting instruction. (After this,
the number of LCD lines and the font size cannot be changed.)
12) Check the Busy Flag for No Busy.
13) Execute the Display ON/OFF control Instruction, Display Clear Instruction, Entry Mode Setting
instruction and Arbitrator Display Line Setting Instruction.
14) Check the Busy Flag for No Busy.
15) Initialization is completed.
An example of instruction code for 3), 5) and 7)
RS1
RS0
R/W
DB7
DB6
DB5
DB4
1
0
0
0
0
1
1
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FEDL9042-01
OKI Semiconductor
ML9042-xx
An example of instruction code for 9)
RS1
RS0
R/W
DB7
DB6
DB5
DB4
1
0
0
0
0
1
0
*: From 11), input data twice by the use of 4-bit data.
*: In 13), check the Busy Flag for No Busy before executing each instruction.
(c)
Data transfer from and to the CPU using the serial I/F
1) Turn on the power.
2) Wait for 15 ms or more after VDD has reached 2.7 V or higher.
3) Check the busy flag for No Busy.
4) Set “Number of LCD lines” and “Font size” with the Function Setting Instruction. (After this, the
number of LCD lines and the font size cannot be changed.)
5) Check the busy flag for No Busy.
6) Execute the Display ON/OFF control Instruction, the Display Clear Instruction, the Entry Mode
Instruction and the Arbitrator Display Line Setting Instruction.
7) Check the busy flag for No Busy.
8) Initialization is completed.
*: In 6), check the Busy Flag for No Busy before executing each instruction.
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FEDL9042-01
OKI Semiconductor
ML9042-xx
ML9042-xx CVWA/DVWA PAD CONFIGURATION
Pad Layout
7.8 × 1.8 mm
625±20 µm
100 × 44 µm
Chip Size:
Chip Thickness:
Bump Size:
Y
115
220
114
221
X
233
101
100
1
Pad Coordinates
Pad
Symbol
X (µm)
Y (µm)
Pad
Symbol
X (µm)
Y (µm)
1
DUMMY
-3750
–750
21
DUMMY
-2250
–750
2
OSC2
-3675
–750
22
E/SHTB
-2175
–750
3
OSCR5
-3600
–750
23
E/SHTB
-2100
–750
4
OSCR3
-3525
–750
24
DUMMY
-2025
–750
5
OSC1
-3450
–750
25
DUMMY
-1950
–750
6
DUMMYGND
-3375
–750
26
DB0/SO
-1875
–750
7
T1
-3300
–750
27
DB0/SO
-1800
–750
8
T2
-3225
–750
28
DUMMY
-1725
–750
9
T3
-3150
–750
29
DUMMY
-1650
–750
10
ROM1S
-3075
–750
30
DB1
-1575
–750
11
DUMMYVDD
-3000
–750
31
DB1
-1500
–750
12
RS1
-2925
–750
32
DUMMY
-1425
–750
13
RS1
-2850
–750
33
DUMMY
-1350
–750
14
RSO/CSB
-2775
–750
34
DB2
-1275
–750
15
RSO/CSB
-2700
–750
35
DB2
-1200
–750
16
DUMMY
-2625
–750
36
DUMMY
-1125
–750
17
DUMMY
-2550
–750
37
DUMMY
-1050
–750
18
RW/SI
-2475
–750
38
DB3
-975
–750
19
RW/SI
-2400
–750
39
DB3
-900
–750
20
DUMMY
-2325
–750
40
DUMMY
-825
–750
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FEDL9042-01
OKI Semiconductor
ML9042-xx
Pad
Symbol
X (µm)
Y (µm)
Pad
Symbol
X (µm)
Y (µm)
41
DUMMY
-750
–750
81
V0
2250
-750
42
DB4
-675
–750
82
V0
2325
-750
43
DB4
-600
–750
83
V0
2400
-750
44
DUMMY
-525
–750
84
V0
2475
-750
45
DUMMY
-450
–750
85
V1
2550
-750
46
DB5
-375
–750
86
V2
2625
-750
47
DB5
-300
–750
87
V2
2700
-750
48
DUMMY
-225
–750
88
V3A
2775
-750
49
DUMMY
-150
–750
89
V3A
2850
-750
50
DB6
-75
–750
90
V3B
2925
-750
51
DB6
0
–750
91
V3B
3000
-750
52
DUMMY
75
–750
92
V4
3075
-750
53
DUMMY
150
–750
93
VC
3150
-750
54
DB7
225
–750
94
VC
3225
-750
55
DB7
300
–750
95
VC
3300
-750
56
DUMMYVDD
375
–750
96
VC
3375
-750
57
SP
450
–750
97
VCC
3450
-750
58
GND
525
–750
98
VCC
3525
-750
59
GND
600
–750
99
VCC
3600
-750
60
GND
675
–750
100
DUMMY
3675
-750
61
GND
750
–750
101
DUMMY
3750
-462
62
GND
825
–750
102
COM17
3750
-392
63
GND
900
–750
103
COM16
3750
-322
64
BE
975
–750
104
COM15
3750
-252
65
VDD
1050
–750
105
COM14
3750
-182
66
VDD
1125
–750
106
COM13
3750
-112
67
VDD
1200
–750
107
COM12
3750
-42
68
VDD
1275
–750
108
COM11
3750
28
69
VDD
1350
–750
109
COM10
3750
98
70
VDD
1425
–750
110
COM9
3750
168
71
TESTIN
1500
–750
111
DUMMY
3750
238
72
TESTIN
1575
–750
112
DUMMY
3750
308
73
TESTOUT
1650
–750
113
DUMMY
3750
378
74
TESTOUT
1725
–750
114
DUMMY
3750
448
75
VIN
1800
–750
115
DUMMY
3675
750
76
VIN
1875
–750
116
DUMMY
3605
750
77
VOUT
1950
–750
117
DUMMY
3535
750
78
VOUT
2025
–750
118
SEG100
3465
750
79
V0
2100
–750
119
SEG99
3395
750
80
V0
2175
–750
120
SEG98
3325
750
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FEDL9042-01
OKI Semiconductor
ML9042-xx
Pad
Symbol
X (µm)
Y (µm)
Pad
Symbol
X (µm)
Y (µm)
121
SEG97
3255
750
161
SEG57
455
750
122
SEG96
3185
750
162
SEG56
385
750
123
SEG95
3115
750
163
SEG55
315
750
124
SEG94
3045
750
164
SEG54
245
750
125
SEG93
2975
750
165
SEG53
175
750
126
SEG92
2905
750
166
SEG52
105
750
127
SEG91
2835
750
167
SEG51
35
750
128
SEG90
2765
750
168
SEG50
-35
750
129
SEG89
2695
750
169
SEG49
-105
750
130
SEG88
2625
750
170
SEG48
-175
750
131
SEG87
2555
750
171
SEG47
-245
750
132
SEG86
2485
750
172
SEG46
-315
750
133
SEG85
2415
750
173
SEG45
-385
750
134
SEG84
2345
750
174
SEG44
-455
750
135
SEG83
2275
750
175
SEG43
-525
750
136
SEG82
2205
750
176
SEG42
-595
750
137
SEG81
2135
750
177
SEG41
-665
750
138
SEG80
2065
750
178
SEG40
-735
750
139
SEG79
1995
750
179
SEG39
-805
750
140
SEG78
1925
750
180
SEG38
-875
750
141
SEG77
1855
750
181
SEG37
-945
750
142
SEG76
1785
750
182
SEG36
-1015
750
143
SEG75
1715
750
183
SEG35
-1085
750
144
SEG74
1645
750
184
SEG34
-1155
750
145
SEG73
1575
750
185
SEG33
-1225
750
146
SEG72
1505
750
186
SEG32
-1295
750
147
SEG71
1435
750
187
SEG31
-1365
750
148
SEG70
1365
750
188
SEG30
-1435
750
149
SEG69
1295
750
189
SEG29
-1505
750
150
SEG68
1225
750
190
SEG28
-1575
750
151
SEG67
1155
750
191
SEG27
-1645
750
152
SEG66
1085
750
192
SEG26
-1715
750
153
SEG65
1015
750
193
SEG25
-1785
750
154
SEG64
945
750
194
SEG24
-1855
750
155
SEG63
875
750
195
SEG23
-1925
750
156
SEG62
805
750
196
SEG22
-1995
750
157
SEG61
735
750
197
SEG21
-2065
750
158
SEG60
665
750
198
SEG20
-2135
750
159
SEG59
595
750
199
SEG19
-2205
750
160
SEG58
525
750
200
SEG18
-2275
750
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FEDL9042-01
OKI Semiconductor
ML9042-xx
Pad
Symbol
X (µm)
Y (µm)
201
SEG17
-2345
750
202
SEG16
-2415
750
203
SEG15
-2485
750
204
SEG14
-2555
750
205
SEG13
-2625
750
206
SEG12
-2695
750
207
SEG11
-2765
750
208
SEG10
-2835
750
209
SEG9
-2905
750
210
SEG8
-2975
750
211
SEG7
-3045
750
212
SEG6
-3115
750
213
SEG5
-3185
750
214
SEG4
-3255
750
215
SEG3
-3325
750
216
SEG2
-3395
750
217
SEG1
-3465
750
218
DUMMY
-3535
750
219
DUMMY
-3605
750
220
DUMMY
-3675
750
221
DUMMY
-3750
448
222
DUMMY
-3750
378
223
DUMMY
-3750
308
224
DUMMY
-3750
238
225
COM1
-3750
168
226
COM2
-3750
98
227
COM3
-3750
28
228
COM4
-3750
-42
229
COM5
-3750
-112
230
COM6
-3750
-182
231
COM7
-3750
-252
232
COM8
-3750
-322
233
DUMMY
-3750
-392
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FEDL9042-01
OKI Semiconductor
ML9042-xx
ML9042-xx CVWA/DVWA ALIGNMENT MARK SPECIFICATION
Alignment Mark Coordinates
Y
A
B
....................................................................................................
:
:
:
:
(0, 0)
X
....................................................................................................
C
Alignment Mark
X (µm)
Y (µm)
A
–3770
770
B
3770
770
C
3770
–770
The coordinates (X, Y) indicate the distances to the center of an alignment mark (the center of the maximum
outline of the L shape).
Alignment Mark Layer
Gold bump
Alignment Mark Gold Bump Specification
Symbol
Parameter
Mark
Size (µm)
a
b
Alignment Mark Width
A, B, C
30
Alignment Mark Size
A, B, C
80
b
a
b
+
a
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FEDL9042-01
OKI Semiconductor
ML9042-xx
ML9042-xx CVWA GOLD BUMP SPECIFICATION (HIGH HARDNESS)
Gold Bump Specification
Symbol
Parameter
A
Bump Pitch (I/O Section: Pitch Direction)
MIN
TYP
70
—
(Unit: µm)
MAX
—
B
Bump Size (I/O Section: Pitch Direction)
40
44
48
C
Bump Size (I/O Section: Depth Direction)
96
100
104
D
Bump-to-Bump Distance (I/O Section: Pitch Direction)
22
26
30
E
Bump Size (L-mark Section: Length)
76
80
84
F
Bump Size (L-mark Section: Width)
26
30
34
G
Sliding of Total Bump Pitches
—
—
2
Bump Height
10
15
20
Bump Height Dispersion Inside Chip (Range)
—
—
4
H
I
Bump Edge Height
—
—
5
J
Shear Strength (g)
27
—
—
K
Bump Hardness (Hv: 25 g load)
50
90
130
Wafer Thickness; 625 ±20 µm
Chip Size; 7.80 mm × 1.80 mm
Top View and Cross Section View
A
F
H
E
C
I
B
D
[I/O Section]
[L-Alignment Mark]
[Cross Section View]
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FEDL9042-01
OKI Semiconductor
ML9042-xx
ML9042-xx CVWA GOLD BUMP SPECIFICATION (LOW HARDNESS)
Gold Bump Specification
Symbol
Parameter
A
Bump Pitch (I/O Section: Pitch Direction)
MIN
TYP
70
—
(Unit: µm)
MAX
—
B
Bump Size (I/O Section: Pitch Direction)
40
44
48
C
Bump Size (I/O Section: Depth Direction)
96
100
104
D
Bump-to-Bump Distance (I/O Section: Pitch Direction)
22
26
30
E
Bump Size (L-mark Section: Length)
76
80
84
F
Bump Size (L-mark Section: Width)
26
30
34
G
Sliding of Total Bump Pitches
—
—
2
Bump Height
10
15
20
Bump Height Dispersion Inside Chip (Range)
—
—
4
H
I
Bump Edge Height
—
—
5
J
Shear Strength (g)
27
—
—
K
Bump Hardness (Hv: 25 g load)
30
—
80
Wafer Thickness; 625 ±20 µm
Chip Size; 7.80 mm × 1.80 mm
Top View and Cross Section View
A
F
H
E
C
I
B
D
[I/O Section]
[L-Alignment Mark]
[Cross Section View]
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FEDL9042-01
OKI Semiconductor
ML9042-xx
REVISION HISTORY
Document
No.
PEDL9042-01
FEDL9042-01
Date
Jun. 16, 2003
Page
Previous Current
Edition
Edition
–
5
–
5
8
8
25
25
44
44
45
45
Nov. 19, 2003
Description
Preliminary first edition
Changed descriptions of Symbols VC and VCC
Changed DC Characteristics
Condition
VDD = 4.5 to 5.5V→VDD = 4.0 to 5.5V
Ta = 25°C→Ta =- 20 to 75°C
Spec
Min. 175 Typ. 270 Max. 365
→Min. 200 Typ. 270 Max. 351
Min. 175 Typ. 270 Max. 365
→Min. 200 Typ. 280 Max. 364
Added of table
Partially changed figure of generation circuits
(VC+)→(VCC+) and V2,V3A,V3B
Partially changed figure of generation circuits
(VC+)→(VCC+)
57/58
FEDL9042-01
OKI Semiconductor
ML9042-xx
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any
system or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2003 Oki Electric Industry Co., Ltd.
58/58