E2B0021-27-Y2 ¡ Semiconductor MSM5299C ¡ Semiconductor This version: MSM5299C Nov. 1997 Previous version: Mar. 1996 80-DOT LCD SEGMENT DRIVER GENERAL DESCRIPTION The MSM5299C is a dot matrix LCD segment driver LSI which is fabricated using CMOS low power metal gate technology. This LSI consists of an 80-bit bidirectional shift register, 80-bit latch, 80-bit level shifter, and 80-bit 4-level driver. It receives the 4-bit parallel display data transferred from a microcomputer or an LCD controller LSI such as MSM6255, then outputs the LCD driving waveform to the LCD. This LSI is improved with respect to timing between load and clock in the switching characteristics of MSM5299A. (tLC = 200ns Æ 63ns) However, note that the timing regulations for the load signal leading edge are added. FEATURES • • • • • Logic supply voltage : 4.5 to 5.5V LCD driving voltage : 8 to 28V Applicable LCD duty : 1/64 to 1/256 LCD Output : 80 4-bit parallel data processing has improved the transfer speed to 1/4 that of the conventional serial transfer, thereby achieving low power consumption • Can be interfaced with the LCD controller LSI MSM6255 • Applicable common driver : MSM5298A (68 outputs) • Package options : 100-pin plastic QFP (QFP100-P-1420-0.65-K) (Product name : MSM5299CGS-K) 100-pin plastic QFP (QFP100-P-1420-0.65-BK) (Product name : MSM5299CGS-BK) 1/11 ¡ Semiconductor MSM5299C BLOCK DIAGRAM O1 O2 O79 O80 V1 V3 80-Bit 4-Level Driver VDD V4 VEE VEE DF DISP OFF 80-Bit Level Shifter VDD 80-Bit Latch (Edge Trigger D-F/F) LOAD D0 D1 D2 D3 4 x 20-Bit Bidirectional Shift Register SHL VDD SHIFT CP CP EL VSS CONTROL CIRCUIT VSS ER 2/11 ¡ Semiconductor MSM5299C 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 O50 O49 O48 O47 O46 O45 O44 O43 O42 O41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 PIN CONFIGURATION (TOP VIEW) O51 O52 O53 O54 O55 O56 O57 O58 O59 O60 O61 O62 O63 O64 O65 O66 O67 O68 O69 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 O30 O29 O28 O27 O26 O25 O24 O23 O22 O21 O20 O19 O18 O17 O16 O15 O14 O13 O12 O11 O10 O9 O8 O7 O6 O5 O4 O3 O2 O1 ER NC VEE V4 V3 V1 NC DF DISP OFF VDD SHL VSS D3 D2 D1 D0 CP NC LOAD EL 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 O70 O71 O72 O73 O74 O75 O76 O77 O78 O79 O80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC : No connection 100-Pin Plastic QFP Note : The abbreviated part number "M5299C" is imprinted on the package surface. 3/11 ¡ Semiconductor MSM5299C ABSOLUTE MAXIMUM RATINGS (VSS = 0V) Symbol Condition Rating Unit Supply Voltage (1) VDD Ta = 25°C –0.3 to +6 V Supply Voltage (2) VLCD Ta = 25°C, VDD–VEE 0 to 30 V Input Voltage VI Ta = 25°C –0.3 to VDD+0.3 V Storage Temperature TSTG — –55 to +150 °C Parameter *1 *1 VDD≥V1>V3>V4>VEE RECOMMENDED OPERATING CONDITIONS (VSS = 0V) Symbol Condition Range Unit Supply Voltage (1) VDD — 4.5 to 5.5 V Supply Voltage (2) VLCD VDD–VEE 8 to 28 V Operating Temperature Top — –20 to +85 °C Parameter *1 *1 VDD≥V1>V3>V4>VEE 4/11 ¡ Semiconductor MSM5299C ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 5V ± 10%, Ta = –20 to +85°C) Parameter Symbol "H" Input Voltage VIH "L" Input Voltage VIL "H" Input Current IIH L" Input Current IIL "H" Output Voltage VOH "L" Output Voltage VOL ON Resistance RON Condition Min. Typ. Max. Unit — 0.8VDD — VDD V — VSS — 0.2VDD V VIH = VDD, VDD = 5.5V — — 1 mA VIL = 0V, VDD = 5.5V — — –1 mA IO = –0.2mA, VDD = 4.5V VDD – 0.4 — — V IO = 0.2mA, VDD = 4.5V — — 0.4 V — — 4 kW *5 — — 200 mA *6 — — 3 mA *7 — — ±100 mA — 5 — pF *1 *1 *1 *1 *2 *2 *3 *4 VDD – VEE = 23V Stand-by Current IDDSBY Supply Current (1) IDD1 Supply Current (2) IV Input Capacitance CI VN – VO = 0.25V, VDD = 4.5V fCP = 1MHz, VDD = 5.5V VDD – VEE = 26V, no load fCP = 1MHz, VDD = 5.5V VDD – VEE = 26V, no load fCP = 1MHz, VDD = 5.5V VDD – VEE = 26V, no load f = 1MHz *1 Applicable to LOAD, CP, D0 to D3, EL, ER, SHL, DF, DISP OFF pins *2 Applicable to EL, ER pins. *3 VN = VDD to VEE, V4 = 2 13 (VDD – VEE), V3 = (VDD – VEE), VDD = V1 15 15 *4 Applicable to O1 to O80 pins. *5 Display data 1010, fDF = 40 Hz, current that flows from VDD to VSS when the display data is not clocked in. *6 Display data 1010, fDF = 40 Hz, current that flows from VDD to VSS when the display data is clocked in. *7 Display data 1010, fDF = 40 Hz, current that flows to each of the V1, V3 and V4 pins. 5/11 ¡ Semiconductor MSM5299C Switching Characteristics (VDD = 5V ± 10%, Ta = –20 to +75°C, CL = 15pF) Parameter Clock Frequency Symbol Condition Min. Typ. Max. Unit fCP DUTY=50% — — 3.4 MHz tW — 100 — — ns tr, tf — — — 50 ns Data Setup Time tDSU — 50 — — ns Data Hold Time tDHD — 80 — — ns Clock, Load Pulse Width Clock Pulse Rise/Fall Time Clock Æ Load Time tCL — 63 — — ns Load Setup Time tLSU1 — 90 — — ns Load Setup Time tLSU2 — 90 — — ns Load Æ Clock Time tLC — 63 — — ns Propagation Delay Time tPHL — — — 224 ns ER, EL Setup Time tESU — 70 — — ns tf tW CP 0.8VDD 0.8VDD tDSU tW tr tW 0.8VDD 0.2VDD 0.2VDD tDHD 0.8VDD 0.8VDD 0.8VDD 0.2VDD 0.2VDD D0 - D3 tLSU1 tLSU2 tCL LOAD 0.8VDD 0.2VDD 1 tLC 0.2VDD tW tr CP 0.8VDD tf 2 19 0.2VDD 0.8VDD 20 LOAD tPHL ER, EL (Output) EL, ER (Input) 0.2VDD tESU 0.2VDD 6/11 ¡ Semiconductor MSM5299C FUNCTIONAL DESCRIPTION Pin Functional Description • ER, EL Pin Input/Output ER Input EL Output EL Input ER Output Description SHL Input pin to ENABLE F/F of MSM5299C. L Output pin of ENABLE F/F. EL is connected to next MSM5299C's ER when MSM5299Cs are connected in series (cascade connection). Input pin to ENABLE F/F of MSM5299C. H Output pin of ENABLE F/F. ER is connected to next MSM5299C's EL when MSM5299Cs are connected in series (cascade connection). When a single MSM5299C device is used, ER (EL) should be set at "L" level. When a cascade connection is required, set the first MSM5299C's ER (EL) pin at "L" level and connect the next MSM5299C's EL (ER) pin to the further next MSM5299C's ER (EL) pin. • CP Clock pulse input pin for the 4-bit parallel shift register. The data is shifted to the 4-bit parallel shift register at the falling edge of the clock pulse. • SHL ER and EL can be used as either an input pin or an output pin based on the H/L condition of SHL. The shift direction of each data (D0 to D3), the Input/Output condition of ER and EL and the H/L condition of SHL are described in the table below. SHL L H ER Input Output EL Shift direction Output D0 D1 D2 D3 O1 O2 O3 O4 O5 O6 O7 O8 O77 O78 O79 O80 Input D0 D1 D2 D3 O80 O79 O78 O77 O76 O75 O74 O73 O4 O3 O2 O1 end data start data 7/11 ¡ Semiconductor MSM5299C • D0, D1, D2, D3 Display data input pins for 4¥20-bit shift register. The display data is clocked into these pins. The combinations of D0 to D3, DF signal level, display data output level and the display on the LCD panel are described in the table below. D0 - D3 DF Liquid crystal drive output Liquid crystal dispaly L L Non-select level (V3) OFF H L Select level (V1) ON L H Non-select level (V4) OFF H H Select level (VEE) ON • LOAD The signal for latching the shift register contents is input to this pin. The display data stored in the shift register is latched at the falling edge of the LOAD pulse. • DF Alternate signal input pin for LCD driving. Frame inversion signal is input to this pin. • VDD, VSS Supply voltage pins. VDD should be 4.5 to 5.5V. VSS is a ground pin (VSS = 0V). • V1, V3, V4, VEE Bias supply voltage pin to drive the LCD. Bias voltage to drive the LCD is supplied from an external source. 8/11 ¡ Semiconductor MSM5299C • O1 to O80 Display data output pins which correspond to the respective latch contents. One of V1, V3, V4 and VEE is selected as a display driving voltage source based on the combination of the latched data level and DF signal. (Refer to the Truth Table). The outputs O1 to O80 are connected to the segment side of the LCD panel. • DISP OFF Input pin for controlling the outputs of O1 to O80. V1 level is output from O1 to O80 pins during "L" level input. Refer to the Truth Table. Truth Table DF Latched data DISP OFF Driver output level (O1-O80) L L H V3 L H H V1 H L H V4 H H H VEE X L V1 X NOTES ON USE Note the following when turning power on and off : The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied to the LCD drivers with the logic power supply floating, excess current flows. This may damage the IC. Be sure to carry out the follwing power-on and power-off sequences : When turning power on : First VDD ON, next VEE, V4, V3, V1 ON. Or both ON at the same time. When turning power off : First VEE, V4, V3, V1 OFF, next VDD OFF. Or both OFF at the same time. 9/11 ¡ Semiconductor MSM5299C PACKAGE DIMENSIONS (Unit : mm) QFP100-P-1420-0.65-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 10/11 ¡ Semiconductor MSM5299C (Unit : mm) QFP100-P-1420-0.65-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 11/11