E2B0020-27-Y2 ¡ Semiconductor MSM5299A ¡ Semiconductor This version: MSM5299A Nov. 1997 Previous version: Mar. 1996 80-DOT LCD SEGMENT DRIVER GENERAL DESCRIPTION The MSM5299A is a dot matrix LCD segment driver LSI which is fabricated using CMOS low power metal gate technology. This LSI consists of an 80-bit bidirectional shift register, 80-bit latch, 80-bit level shifter and 80-bit 4-level driver. It receives the display data, which is transferred in 4-bit parallel from a microcomputer or LCD controller LSI such as MSM6255, then outputs the LCD driving waveform to the LCD. FEATURES • • • • • Supply voltage : 4.5 to 5.5V LCD driving voltage : 8 to 28V Applicable LCD duty : 1/64 to 1/256 LCD Output : 80 The 4-bit parallel data processing has improved the transfer speed to 1/4 that of the conventional serial transfer, thereby achieving low power consumption • Can be interfaced with the LCD controller LSI MSM6255 • Applicable common diriver : MSM5298A (68 outputs) • Package options: 100-pin plastic QFP (QFP100-P-1420-0.65-K) (Product name : MSM5299AGS-K) 100-pin plastic QFP (QFP100-P-1420-0.65-BK) (Product name : MSM5299AGS-BK) 1/11 ¡ Semiconductor MSM5299A BLOCK DIAGRAM O1 O2 O79 O80 V1 V3 80-Bit 4-Level Driver VDD V4 VEE VEE DF DISP OFF 80-Bit Level Shifter VDD 80-Bit Latch (Edge trigger D-F/F) LOAD D0 D1 D2 D3 4 x 20-Bit Bidirectional Shift Register SHL VDD SHIFT CP CP EL VSS Control Circuit VSS ER 2/11 ¡ Semiconductor MSM5299A O34 O33 O32 O31 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 O50 O49 O48 O47 O46 O45 O44 O43 O42 O41 O40 O39 O38 O37 O36 O35 PIN CONFIGURATION (TOP VIEW) O51 O52 1 80 2 79 O53 3 78 O54 O55 4 77 O28 O27 5 76 O26 O56 6 75 O57 7 74 O58 8 73 O25 O24 O23 O59 O60 9 72 O22 10 71 O61 O62 11 70 O21 O20 12 69 O63 O64 13 68 14 67 O65 15 66 O66 O67 16 65 17 64 O68 O69 18 63 19 62 O70 20 61 O71 O72 21 60 22 59 O73 O74 23 58 O9 O8 24 57 O7 O75 25 56 O76 O77 26 55 O6 O5 27 54 O78 28 53 O79 29 52 O80 30 51 O30 O29 O19 O18 O17 O16 O15 O14 O13 O12 O11 O10 O4 O3 EL D3 D2 D1 D0 CP NC LOAD ER NC VEE V4 V3 V1 NC DF DISPOFF VDD SHL VSS 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 O2 O1 NC : No connection 100-Pin Plastic QFP Note: The abbreviated part number "M5299A" is imprinted on the package surface. 3/11 ¡ Semiconductor MSM5299A ABSOLUTE MAXIMUM RATINGS (VSS=0V) Symbol Condition Rating Unit Supply Voltage (1) VDD Ta = 25°C –0.3 to +6 V Supply Voltage (2) VLCD Ta = 25°C, VDD – VEE 0 to 30 V Input Voltage VI Ta = 25°C –0.3 to VDD+0.3 V Storage Temperature TSTG — –55 to +150 °C Parameter *1 *1 VDD≥V1>V3>V4>VEE RECOMMENDED OPERATING CONDITIONS (VSS=0V) Symbol Condition Range Unit Supply Voltage (1) VDD — 4.5 to 5.5 V Supply Voltage (2) VLCD VDD – VEE 8 to 28 V Operating Temperature Top — –20 to +85 °C Parameter *1 *1 VDD≥V1>V3>V4>VEE 4/11 ¡ Semiconductor MSM5299A ELECTRICAL CHARACTERISTICS DC Characteristics Parameter (VDD = 5V ± 10%, Ta = –20 to +85°C) Symbol Condition Min. Typ. Max. Unit "H" Input Voltage VIH *1 — 0.8VDD — VDD V "L" Input Voltage VIL *1 — VSS — 0.2VDD V "H" Input Current VIH *1 VIH = VDD, VDD = 5.5V — — 1 mA "H" Input Current VIL *1 VIL = 0V, VDD = 5.5V — — –1 mA "H" Output Voltage VOH *2 IO = –0.2mA, VDD = 4.5V VDD – 0.4 — — V "L" Output Voltage VOL *2 IO = 0.2mA, VDD = 4.5V — — 0.4 V ON Resistance RON *4 — 2 4 kW — — 200 mA — — 3 mA — — ±100 mA — 5 — pF Stand-by Current IDDSBY Supply Current (1) IDD1 Supply Current (2) IV Input Capacitance CI VDD – VEE = 23V *3 VN – VO = 0.25V, VDD = 4.5V fCP = 1MHz, VDD = 5.5V VDD – VEE = 26V, No load *5 fCP =1MHz, VDD = 5.5V VDD – VEE = 26V, No load *6 fCP = 1MHz, VDD = 5.5V VDD – VEE = 26V, No load f = 1MHz *7 *1 Applicable to LOAD, CP, D0 - D3, EL, ER, SHL, DF, DISP OFF *2 Applicable to EL, ER. *3 VN = VDD to VEE, V4 = 2 13 (VDD – VEE), V3 = (VDD – VEE), V1 = VDD 15 15 *4 Applicable to O1 to O80. *5 Display data 1010 ......fDF = 40 Hz, Current from VDD to VSS when the display data is not processing. *6 Display data 1010 ......fDF = 40 Hz, Current from VDD to VSS when the display data is processing. *7 Display data 1010 ......fDF = 40 Hz, Current on V1, V3 and V4. 5/11 ¡ Semiconductor MSM5299A Switching Characteristics (VDD = 5V ± 10%, Ta = –20 to +75°C, CL = 15pF) Parameter Symbol Condition DUTY=50% Min. Typ. Max. Unit — — 3.4 MHz Clock Frequency fCP Clock, Load Pulse Width tW — 100 — — ns Clock Pulse Rise/Fall Time tr, tf — — — 50 ns Data Set-up Time tDSU — 50 — — ns Data Hold Time tDHD — 80 — — ns Load Set-up Time tLSU — 90 — — ns Load Æ Clock Time tLC — 200 — — ns Propagation Delay Time tPHL — — — 224 ns ER, EL Set-up Time tESU — 70 — — ns tf tW CP 0.8VDD 0.8VDD tDSU tW tr tW 0.8VDD 0.2VDD 0.2VDD tDHD 0.8VDD 0.8VDD 0.8VDD 0.2VDD 0.2VDD D0 - D3 tLSU LOAD 0.8VDD 0.2VDD 1 tLC 0.2VDD tW tr CP 0.8VDD tf 2 19 0.2VDD 0.8VDD 20 LOAD tPHL ER, EL (Output) EL, ER (Input) 0.2VDD tESU 0.2VDD 6/11 ¡ Semiconductor MSM5299A FUNCTIONAL DESCRIPTION Pin Functional Description • ER, EL Pin Input/Output ER Input EL Output EL Input ER Output Description SHL Input pin to ENABLE F/F of MSM5299A. L Output pin of ENABLE F/F. EL is connected to next MSM5299A's ER when MSM5299As are connected in series (cascade connection). Input pin to ENABLE F/F of MSM5299A. H Output pin of ENABLE F/F. ER is connected to next MSM5299A's EL when MSM5299As are connected in series (cascade connection). When single MSM5299A is used, ER (EL) should be set at "L" level. When a cascade connection is required, set the ER (EL) pin of the first MSM5299A at "L" level and connect the EL (ER) pin of the first MSM5299A to the ER (EL) pin of the second MSM5299A, then connect the EL (ER) pin of the second MSM5299A to the ER (EL) pin of the third MSM5299A. • CP Clock pulse input pin for the 4-bit parallel shift register. The data is shifted to 4 ¥ 20-bit shift register at the falling edge of the clock pulse. The clock pulse is activated when the ENABLE F/F is set and is deactivated when the ENABLE F/F is not set. • SHL Input pin to switch the input or output of pins ER and EL, and the shift direction of the 4-bit parallel bidirectional shift register. The shift direction of the 4-bit parallel data, the correspondence of the data D0 to D3 to the driver outputs O1 to O80, and the input and output state of pins ER and EL are shown in the table below. SHL L H ER Input Output EL Shift direction Output D0 D1 D2 D3 O1 O2 O3 O4 O5 O6 O7 O8 O77 O78 O79 O80 Input D0 D1 D2 D3 O80 O79 O78 O77 O76 O75 O74 O73 O4 O3 O2 O1 end data start data 7/11 ¡ Semiconductor MSM5299A • D0, D1, D2, D3 Display data input pins for 4 ¥ 20-bit shift register. The display data is clocked into the shift register at the falling edge of the clock pulse. The combinations of D0 to D3 level, DF signal level, display data output level and the display on the LCD panel are described on the table below. D0 to D3 DF Display data output level Display on the LCD L L Nonselect level (V3) OFF H L Select level (V1) ON L H Nonselect level (V4) OFF H H Select level (VEE) ON • LOAD The signal for latching the shift register contents is input to this pin. The display data stored in the shift register is latched at the falling edge of the load pulse. • DF Synchronous signal input pin for alternate signal for LCD driving. • VDD, VSS Supply voltage pins, VDD should be 4.5 to 5.5V. VSS is a ground pin (VSS = 0V) • V1, V3, V4, VEE Bias supply voltage pin to drive the LCD. Use an external bias voltage supply for driving the LCD. 8/11 ¡ Semiconductor MSM5299A • O1 - O80 Display data output pins, which correspond to the respective latch contents. One of V1, V3, V4 and VEE is selected as a display driving voltage source according to the combination of the latched data level and DF signal. Refer to the Truth Table. The outputs O1 to O80 are connected to the segment side of the LCD panel. • DISP OFF Input pin to control outputs of O1 to O80. V1 level is output from O1 to O80 pins during "L" level input. Refer to the Truth Table. Truth Table DF Latched data DISP OFF L LCD driver output (O1 - O80) L H V3 L H H V1 H L H V4 H H H VEE X X L V1 X : Don't care NOTES ON USE Note the following when turning power on and off: The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied to the LCD drivers with the logic power supply floating, excess current flows. This may damage the IC. Be sure to carry out the following power-on and power-off sequences: When turning power on: First VDD ON, next VEE, V4, V3, V1 ON. Or both ON at the same time. When turning power off: First VEE, V4, V3, V1 OFF, next VDD OFF. Or both OFF at the same time. 9/11 ¡ Semiconductor MSM5299A PACKAGE DIMENSIONS (Unit : mm) QFP100-P-1420-0.65-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 10/11 ¡ Semiconductor MSM5299A (Unit : mm) QFP100-P-1420-0.65-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 11/11