E2B0028-27-Y2 ¡ Semiconductor MSM5298A ¡ Semiconductor This version: MSM5298A Nov. 1997 Previous version: Mar. 1996 68-DOT COMMON DRIVER GENERAL DESCRIPTION The MSM5298A is a dot matrix LCD common driver LSI which is fabricated using low power CMOS metal gate technology. This LSI consists of 68-bit bidirectional shift register, 68-bit level shifter and 68-bit 4-level driver. This LSI has 68 output pins to be connected to the LCD. By connecting two or more MSM5298As in series, this LSI is applicable to a wide LCD panel. FEATURES • Supply voltage : 4.5 to 5.5V • LCD driving voltage : 8 to 28V • Applicable LCD duty : 1/64 to 1/256 • Applicable segment driver : MSM5299A (80 outputs), MSM5299C (80 outputs) • Package options: 80-pin plastic QFP (QFP80-P-1420-0.80-K) (Product name : MSM5298AGS-K) 80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM5298AGS-BK) 1/9 ¡ Semiconductor MSM5298A BLOCK DIAGRAM O 1 O2 O67 O68 V1 V2 68-Bit 4-Level Driver VDD V5 VEE VEE DF DISP OFF SHL IO1 CP 68-Bit Level Shifter VDD VSS 68-Bit Bidirectional Shift Register IO68 VDD VSS 2/9 ¡ Semiconductor MSM5298A O35 O34 O33 O32 O31 O30 O29 O28 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 O43 O42 O41 O40 O39 O38 O37 O36 PIN CONFIGURATION (TOP VIEW) O27 O26 O44 O45 1 64 2 63 O46 3 62 O47 O48 4 61 O25 O24 5 60 O23 O49 6 59 O50 7 58 O22 O21 O51 8 57 O20 O52 9 O53 10 O54 11 56 O19 55 O18 O17 O55 12 O56 13 53 O57 14 51 O58 15 O59 16 50 O60 17 O61 18 48 O62 19 46 O63 20 O64 21 45 O65 22 O66 23 43 42 O6 O5 O67 24 41 O4 54 52 49 47 O14 O13 O12 O11 O10 O9 O8 O7 O3 IO1 O1 O2 O68 IO68 VEE V5 V2 V1 DISPOFF VDD SHL VSS DF CP 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 44 O16 O15 80-Pin Plastic QFP Note: The abbreviated part number "M5298A" is imprinted on the package surface. 3/9 ¡ Semiconductor MSM5298A ABSOLUTE MAXIMUM RATINGS (VSS = 0 V) Parameter Symbol Condition Supply Voltage (1) VDD Ta = 25°C Supply Voltage (2) VLCD Ta = 25°C, VDD–VEE *1 VI Ta = 25°C TSTG — Input Voltage Storage Temperature Rating Unit –0.3 to +6 V 0 to +30 V –0.3 to VDD +0.3 V –55 to +150 °C *1 VDD≥V1>V2>V5>VEE RECOMMENDED OPERATING CONDITIONS (VSS = 0 V) Parameter Symbol Condition Range Unit Supply Voltage (1) VDD — 4.5 to 5.5 V Supply Voltage (2) VLCD VDD–VEE 8 to 28 V Operating Temperature Top — –20 to +85 °C *1 *1 VDD≥V1>V2>V5>VEE ELECTRICAL CHARACTERISTICS DC Characteristics Parameter (VDD = 5V±10%, Ta = –20 to +85°C) Symbol Condition Min. Typ. Max. Unit — 0.8VDD — VSS — VDD V — 0.2VDD V — — 1 mA "H" Input Voltage VIH *1 "L" Input Voltage VIL *1 IIH *1 VI = VDD, VDD = 5.5V IIL *1 VI= 0V, VDD = 5.5V — — –1 mA VOH *2 IO= –0.4mA, VDD = 4.5V VDD – 0.4 — — V VOL *2 IO= 0.4mA, VDD = 4.5V — — 0.4 V — 1.5 3 kW — — 100 mA — 5 — pF "H" Input Current "L" Input Current "H" Output Voltage "L" Output Voltage ON Resistance RON Supply Current IDD Input Capacitance CI *1 *2 *3 *4 *4 VDD – VEE = 23V, VDD = 4.5V |VN – VO| = 0.25V fCP = 14kHz, VDD = 5.5V VDD – VEE = 23V, No load f = 1MHz *3 Applicable to CP, IO1, IO68, SHL, DF, DISP OFF. Applicable to IO1, IO68. 14 1 VN = VDD to VEE, V2 = (VDD – VEE), V5 = (VDD – VEE), VDD = V1 15 15 Applicable to O1 to O68. 4/9 ¡ Semiconductor MSM5298A Switching Characteristics (VDD = 5V±10%, Ta = –20 to +85°C, CL = 15pF) Parameter Symbol Condition Min. Typ. Max. Unit — — — 250 ns fCP — — — 1 MHz tW(CP) — 125 — — ns tSETUP — 100 — — ns tHOLD — 100 — — ns tr(CP) — — — 50 ns "H" , "L" Propagation tPLH Delay Time tPHL Clock Frequency Clock Pulse Width Data Setup Time IO1(IO68)ÆCP Data Hold Time CPÆIO1(IO68) Clock Pulse Rise/Fall Time tf(CP) tf(CP) tr(CP) tW(CP) CP 0.8VDD 0.8VDD 0.8VDD tSETUP 0.2VDD 0.2VDD tHOLD IO1 (IO68) 0.8VDD 0.8VDD 0.2VDD 0.2VDD tPLH tPHL IO68 (IO1) 0.8VDD 0.2VDD 5/9 ¡ Semiconductor MSM5298A FUNCTIONAL DESCRIPTION Pin Functional Description • IO1, IO68, SHL IO1 and IO68 are 68-bit bidirectional shift register input/output pins. The shifting direction is selected by the SHL pin. Refer to the table below. SHL L H Shifting direction IO1/IO68 Input/ output IO1 Input The scanning data from the LCD controller LSI is input into IO1 synchronized with the clock pulse.* 1 IO68 Output Shift register contents output pin. The data which is input into IO1 is output from IO68 with 68 bit's delay, synchronized with the clock pulse. IO68 Input The scanning data from the LCD controller LSI is input into IO68 synchronized with the clock pulse.* 1 IO1 Output Shift register contents output pin. The data which is input into IO68 is output from IO1 with 68 bit's delay, synchronized with the clock pulse. Description O1 Æ O68 O68 Æ O1 *1 The combination of the scanning data, IO1 or IO68, and the LCD driving output, O1 to O68, is shown in the table below. IO1, IO68 LCD driving output (V1, VEE) "H" Select level "L" Non-select level (V2, V5) • CP Clock pulse input pin for 68-bit bidirectional shift register. The data is shifted to 68-bit bidirectional shift register at the falling edge of the clock pulse. • DF Alternate signal input pin for LCD driving. • VDD, VSS Supply voltage pins. VDD should be 4.5 to 5.5V. VSS is a ground pin. (VSS = 0V). • DISP OFF Control input pin for display data output level (O1 to O68). V1 level is output from O1 to O68 pin during "L" level input. Refer to Truth Table. 6/9 ¡ Semiconductor MSM5298A • V1, V2, V5, VEE Bias supply voltage pins to drive the LCD. The V1 pin can be separated from the VDD pin. • O1 - O68 Display data output pins which correspond to each bit of the 68-bit bidirectional shift register. One of the four levels, V1, V2, V5 and VEE, is selected based on the combination of the latched data level and DF signal. (Refer to Truth Table.) Connect these outputs to the common side of the LCD panel. Truth Table DF Shift register data DISP OFF Driver output level (O1 to O68) L L H V2 L H H VEE H L H V5 H H H V1 X X L V1 X : Don't care NOTES ON USE (when turning the power ON or OFF) The LCD drivers of this IC require a high voltage. For this reason, if a high voltage is applied to the LCD drivers with the logic power supply floating, excess current flows. This may damage the IC. Be sure to follow the sequence below when turning the power ON or OFF. Power ON : Logic circuits ON Æ LCD drivers ON, or both ON at a time Power OFF : LCD drivers OFF Æ logic circuits OFF, or both OFF at a time 7/9 ¡ Semiconductor MSM5298A PACKAGE DIMENSIONS (Unit : mm) QFP80-P-1420-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.27 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 8/9 ¡ Semiconductor MSM5298A (Unit : mm) QFP80-P-1420-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Epoxy resin 42 alloy Solder plating 5 mm or more Package weight (g) 1.27 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 9/9