LMR12010
LMR12010 SIMPLE SWITCHER ® 20Vin, 1A Step-Down Voltage Regulator in
SOT-23
Literature Number: SNVS731A
LMR12010
SIMPLE SWITCHER® 20Vin, 1A Step-Down Voltage
Regulator in SOT-23
Applications
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Point-of-Load Conversions from 3.3V, 5V, and 12V Rails
Space Constrained Applications
Battery Powered Equipment
Industrial Distributed Power Applications
Power Meters
Portable Hand-Held Instruments
System Performance
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Efficiency vs Load Current - "X" VOUT = 5V
Features
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Input voltage range of 3V to 20V
Output voltage range of 0.8V to 17V
Output current up to 1A
1.6MHz (LMR12010X) and 3 MHz (LMR12010Y)
switching frequencies
Low shutdown Iq, 30 nA typical
Internal soft-start
Internally compensated
Current-Mode PWM operation
Thermal shutdown
Thin SOT23-6 package (2.97 x 1.65 x 1mm)
Fully enabled for WEBENCH® Power Designer
Performance Benefits
■ Extremely easy to use
■ Tiny overall solution reduces system cost
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Efficiency vs Load Current - "Y" VOUT = 5V
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WEBENCH® is a registered trademark of National Semiconductor Corp.
© 2011 National Semiconductor Corporation
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LMR12010 SIMPLE SWITCHER 20Vin, 1A Step-Down Voltage Regulator in SOT-23
September 29, 2011
LMR12010
Connection Diagrams
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Pin 1 Indentification
6-Lead TSOT
NS Package Number MK06A
Ordering Information
Order Number
Package Type
NSC Package
Drawing
LMR12010XMKE
Package Marking
SF7B
LMR12010XMK
LMR12010XMKX
LMR12010YMKE
Supplied As
250 Units on Tape and Reel
1000 Units on Tape and Reel
TSOT-6
3000 Units on Tape and Reel
MK06A
SF8B
250 Units on Tape and Reel
LMR12010YMK
1000 Units on Tape and Reel
LMR12010YMKX
3000 Units on Tape and Reel
Pin Descriptions
Pin
Name
Function
1
BOOST
Boost voltage that drives the internal NMOS control switch. A
bootstrap capacitor is connected between the BOOST and SW pins.
2
GND
3
FB
Feedback pin. Connect FB to the external resistor divider to set output
voltage.
4
EN
Enable control input. Logic high enables operation. Do not allow this
pin to float or be greater than VIN + 0.3V.
5
VIN
Input supply voltage. Connect a bypass capacitor to this pin.
6
SW
Output switch. Connects to the inductor, catch diode, and bootstrap
capacitor.
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Signal and Power ground pin. Place the bottom resistor of the
feedback network as close as possible to this pin for accurate
regulation.
2
Operating Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Note 1)
VIN
SW Voltage
Boost Voltage
Boost to SW Voltage
Junction Temperature Range
VIN
-0.5V to 24V
SW Voltage
-0.5V to 24V
Boost Voltage
-0.5V to 30V
Boost to SW Voltage
-0.5V to 6.0V
FB Voltage
-0.5V to 3.0V
EN Voltage
-0.5V to (VIN + 0.3V)
Junction Temperature
150°C
ESD Susceptibility (Note 2)
2kV
Storage Temp. Range
-65°C to 150°C
For soldering specifications: see product folder at
www.national.com and www.national.com/ms/MS/MSSOLDERING.pdf
3V to 20V
-0.5V to 20V
-0.5V to 25V
1.6V to 5.5V
−40°C to +125°C
Thermal Resistance θJA (Note 3)
118°C/W
Electrical Characteristics
Specifications with standard typeface are for TJ = 25°C, and those in boldface type apply over the full Operating Temperature
Range (TJ = -40°C to 125°C). VIN = 5V, VBOOST - VSW = 5V unless otherwise specified. Datasheet min/max specification limits are
guaranteed by design, test, or statistical analysis.
Symbol
VFB
Parameter
Conditions
Feedback Voltage
Min
(Note 4)
Typ
(Note 5)
Max
(Note 4)
Units
0.784
0.800
0.816
V
ΔVFB/ΔVIN Feedback Voltage Line Regulation VIN = 3V to 20V
IFB
UVLO
Feedback Input Bias Current
Sink/Source
Undervoltage Lockout
VIN Rising
Undervoltage Lockout
VIN Falling
0.01
Switching Frequency
DMAX
Maximum Duty Cycle
DMIN
Minimum Duty Cycle
RDS(ON)
10
250
2.74
2.90
V
2.0
2.3
0.44
0.62
LMR12010X
1.2
1.6
1.9
LMR12010Y
2.2
3.0
3.6
LMR12010X
85
92
LMR12010Y
78
85
LMR12010X
2
LMR12010Y
8
%
VBOOST - VSW = 3V
ICL
Switch Current Limit
VBOOST - VSW = 3V
IQ
Quiescent Current
Switching
Quiescent Current (shutdown)
VEN = 0V
30
LMR12010X (50% Duty Cycle)
2.5
3.5
LMR12010Y (50% Duty Cycle)
4.25
6.0
Boost Pin Current
Shutdown Threshold Voltage
VEN Falling
Enable Threshold Voltage
VEN Rising
IEN
Enable Pin Current
Sink/Source
ISW
Switch Leakage
VEN_TH
1.2
MHz
%
Switch ON Resistance
IBOOST
nA
0.30
UVLO Hysteresis
FSW
%/V
300
600
1.7
2.5
A
1.5
2.5
mA
nA
0.4
1.8
mΩ
mA
V
10
nA
40
nA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see Electrical Characteristics.
Note 2: Human body model, 1.5kΩ in series with 100pF.
Note 3: Thermal shutdown will occur if the junction temperature exceeds 165°C. The maximum power dissipation is a function of TJ(MAX) , θJA and TA . The
maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/θJA . All numbers apply for packages soldered directly onto a 3” x 3” PC
board with 2oz. copper on 4 layers in still air. For a 2 layer board using 1 oz. copper in still air, θJA = 204°C/W.
Note 4: Guaranteed to National’s Average Outgoing Quality Level (AOQL).
Note 5: Typicals represent the most likely parametric norm.
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LMR12010
Absolute Maximum Ratings (Note 1)
LMR12010
Typical Performance Characteristics
All curves taken at VIN = 5V, VBOOST - VSW = 5V, L1 = 4.7 µH ("X"),
L1 = 2.2 µH ("Y") and TA = 25°C, unless specified otherwise.
Efficiency vs Load Current - "X" VOUT = 5V
Efficiency vs Load Current - "Y" VOUT = 5V
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Efficiency vs Load Current - "X" VOUT = 3.3V
Efficiency vs Load Current - "Y" VOUT = 3.3V
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Efficiency vs Load Current - "X" VOUT = 1.5V
Efficiency vs Load Current - "Y" VOUT = 1.5V
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4
Oscillator Frequency vs Temperature - "Y"
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Current Limit vs Temperature
VIN = 5V
Current Limit vs Temperature
VIN = 20V
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VFB vs Temperature
RDSON vs Temperature
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LMR12010
Oscillator Frequency vs Temperature - "X"
LMR12010
IQ Switching vs Temperature
Line Regulation - "X"
VOUT = 1.5V, IOUT = 500mA
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Line Regulation - "Y"
VOUT = 1.5V, IOUT = 500mA
Line Regulation - "X"
VOUT = 3.3V, IOUT = 500mA
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Line Regulation - "Y"
VOUT = 3.3V, IOUT = 500mA
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LMR12010
Block Diagram
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FIGURE 1.
switching frequency of either 3 MHz (LMR12010Y) or 1.6MHz
(LMR12010X). These high frequencies allow the LMR12010
to operate with small surface mount capacitors and inductors,
resulting in DC/DC converters that require a minimum amount
of board space. The LMR12010 is internally compensated, so
it is simple to use, and requires few external components. The
LMR12010 uses current-mode control to regulate the output
voltage.
The following operating description of the LMR12010 will refer
to the Simplified Block Diagram (Figure 1) and to the waveforms in Figure 2. The LMR12010 supplies a regulated output
voltage by switching the internal NMOS control switch at constant frequency and variable duty cycle. A switching cycle
begins at the falling edge of the reset pulse generated by the
internal oscillator. When this pulse goes low, the output control logic turns on the internal NMOS control switch. During
this on-time, the SW pin voltage (VSW) swings up to approximately VIN, and the inductor current (IL) increases with a linear
slope. IL is measured by the current-sense amplifier, which
generates an output proportional to the switch current. The
sense signal is summed with the regulator’s corrective ramp
and compared to the error amplifier’s output, which is proportional to the difference between the feedback voltage and
VREF. When the PWM comparator output goes high, the output switch turns off until the next switching cycle begins.
During the switch off-time, inductor current discharges
through Schottky diode D1, which forces the SW pin to swing
below ground by the forward voltage (VD) of the catch diode.
The regulator loop adjusts the duty cycle (D) to maintain a
constant output voltage.
General Description
The LMR12010 regulator is a monolithic, high frequency,
PWM step-down DC/DC converter in a 6-pin Thin SOT23
package. It provides all the active functions to provide local
DC/DC conversion with fast transient response and accurate
regulation in the smallest possible PCB area.
With a minimum of external components and online design
support through WEBENCH®™, the LMR12010 is easy to
use. The ability to drive 1A loads with an internal 300mΩ
NMOS switch using state-of-the-art 0.5µm BiCMOS technology results in the best power density available. The world
class control circuitry allows for on-times as low as 13ns, thus
supporting exceptionally high frequency conversion over the
entire 3V to 20V input operating range down to the minimum
output voltage of 0.8V. Switching frequency is internally set
to 1.6 MHz (LMR12010X) or 3 MHz (LMR12010Y), allowing
the use of extremely small surface mount inductors and chip
capacitors. Even though the operating frequencies are very
high, efficiencies up to 90% are easy to achieve. External
shutdown is included, featuring an ultra-low stand-by current
of 30nA. The LMR12010 utilizes current-mode control and internal compensation to provide high-performance regulation
over a wide range of operating conditions. Additional features
include internal soft-start circuitry to reduce inrush current,
pulse-by-pulse current limit, thermal shutdown, and output
over-voltage protection.
Application Information
THEORY OF OPERATION
The LMR12010 is a constant frequency PWM buck regulator
IC that delivers a 1A load current. The regulator has a preset
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LMR12010
VIN minus the forward voltage of D2 (VFD2), during which the
current in the inductor (L) forward biases the Schottky diode
D1 (VFD1). Therefore the voltage stored across CBOOST is
VBOOST - VSW = VIN - VFD2 + VFD1
When the NMOS switch turns on (TON), the switch pin rises
to
VSW = VIN – (RDSON x IL),
forcing VBOOST to rise thus reverse biasing D2. The voltage at
VBOOST is then
VBOOST = 2VIN – (RDSON x IL) – VFD2 + VFD1
which is approximately
2VIN - 0.4V
for many applications. Thus the gate-drive voltage of the
NMOS switch is approximately
VIN - 0.2V
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An alternate method for charging CBOOST is to connect D2 to
the output as shown in Figure 3. The output voltage should
be between 2.5V and 5.5V, so that proper gate voltage will be
applied to the internal switch. In this circuit, CBOOST provides
a gate drive voltage that is slightly less than VOUT.
In applications where both VIN and VOUT are greater than
5.5V, or less than 3V, CBOOST cannot be charged directly from
these voltages. If VIN and VOUT are greater than 5.5V,
CBOOST can be charged from VIN or VOUT minus a zener voltage by placing a zener diode D3 in series with D2, as shown
in Figure 4. When using a series zener diode from the input,
ensure that the regulation of the input supply doesn’t create
a voltage that falls outside the recommended VBOOST voltage.
(VINMAX – VD3) < 5.5V
(VINMIN – VD3) > 1.6V
FIGURE 2. LMR12010 Waveforms of SW Pin Voltage and
Inductor Current
BOOST FUNCTION
Capacitor CBOOST and diode D2 in Figure 3 are used to generate a voltage VBOOST. VBOOST - VSW is the gate drive voltage
to the internal NMOS control switch. To properly drive the internal NMOS switch during its on-time, VBOOST needs to be at
least 1.6V greater than VSW. Although the LMR12010 will operate with this minimum voltage, it may not have sufficient
gate drive to supply large values of output current. Therefore,
it is recommended that VBOOST be greater than 2.5V above
VSW for best efficiency. VBOOST – VSW should not exceed the
maximum operating limit of 5.5V.
5.5V > VBOOST – VSW > 2.5V for best performance.
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FIGURE 4. Zener Reduces Boost Voltage from VIN
FIGURE 3. VOUT Charges CBOOST
An alternative method is to place the zener diode D3 in a
shunt configuration as shown in Figure 5. A small 350mW to
500mW 5.1V zener in a SOT-23 or SOD package can be used
for this purpose. A small ceramic capacitor such as a 6.3V,
0.1µF capacitor (C4) should be placed in parallel with the
zener diode. When the internal NMOS switch turns on, a pulse
of current is drawn to charge the internal NMOS gate capacitance. The 0.1 µF parallel shunt capacitor ensures that the
VBOOST voltage is maintained during this time.
Resistor R3 should be chosen to provide enough RMS current
to the zener diode (D3) and to the BOOST pin. A recommended choice for the zener current (IZENER) is 1 mA. The
current I BOOST into the BOOST pin supplies the gate current
of the NMOS control switch and varies typically according to
the following formula for the X version:
When the LMR12010 starts up, internal circuitry from the
BOOST pin supplies a maximum of 20mA to CBOOST. This
current charges CBOOST to a voltage sufficient to turn the
switch on. The BOOST pin will continue to source current to
CBOOST until the voltage at the feedback pin is greater than
0.76V.
There are various methods to derive VBOOST:
1. From the input voltage (VIN)
2. From the output voltage (VOUT)
3. From an external distributed voltage rail (VEXT)
4. From a shunt or series zener diode
In the Simplifed Block Diagram of Figure 1, capacitor
CBOOST and diode D2 supply the gate-drive current for the
NMOS switch. Capacitor CBOOST is charged via diode D2 by
VIN. During a normal switching cycle, when the internal NMOS
control switch is off (TOFF) (refer to Figure 2), VBOOST equals
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IBOOST = 0.56 x (D + 0.54) x (VZENER – VD2) mA
IBOOST can be calculated for the Y version using the following:
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LMR12010
IBOOST = (D + 0.5) x (VZENER - VD2) mA
where D is the duty cycle, VZENER and VD2 are in volts, and
IBOOST is in milliamps. VZENER is the voltage applied to the
anode of the boost diode (D2), and VD2 is the average forward
voltage across D2. Note that this formula for IBOOST gives typical current. For the worst case IBOOST, increase the current
by 40%. In that case, the worst case boost current will be
IBOOST-MAX = 1.4 x IBOOST
R3 will then be given by
R3 = (VIN - VZENER) / (1.4 x IBOOST + IZENER)
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For example, using the X-version let VIN = 10V, VZENER = 5V,
VD2 = 0.7V, IZENER = 1mA, and duty cycle D = 50%. Then
FIGURE 7. VBOOST Derived from Series Zener Diode
(VOUT)
IBOOST = 0.56 x (0.5 + 0.54) x (5 - 0.7) mA = 2.5mA
R3 = (10V - 5V) / (1.4 x 2.5mA + 1mA) = 1.11kΩ
ENABLE PIN / SHUTDOWN MODE
The LMR12010 has a shutdown mode that is controlled by
the enable pin (EN). When a logic low voltage is applied to
EN, the part is in shutdown mode and its quiescent current
drops to typically 30nA. Switch leakage adds another 40nA
from the input supply. The voltage at this pin should never
exceed VIN + 0.3V.
SOFT-START
This function forces VOUT to increase at a controlled rate during start up. During soft-start, the error amplifier’s reference
voltage ramps from 0V to its nominal value of 0.8V in approximately 200µs. This forces the regulator output to ramp up in
a more linear and controlled fashion, which helps reduce inrush current. Under some circumstances at start-up, an output voltage overshoot may still be observed. This may be due
to a large output load applied during start up. Large amounts
of output external capacitance can also increase output voltage overshoot. A simple solution is to add a feed forward
capacitor with a value between 470pf and 1000pf across the
top feedback resistor (R1).
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FIGURE 5. Boost Voltage Supplied from the Shunt Zener
on VIN
OUTPUT OVERVOLTAGE PROTECTION
The overvoltage comparator compares the FB pin voltage to
a voltage that is 10% higher than the internal reference Vref.
Once the FB pin voltage goes 10% above the internal reference, the internal NMOS control switch is turned off, which
allows the output voltage to decrease toward regulation.
UNDERVOLTAGE LOCKOUT
Undervoltage lockout (UVLO) prevents the LMR12010 from
operating until the input voltage exceeds 2.74V(typ).
The UVLO threshold has approximately 440mV of hysteresis,
so the part will operate until VIN drops below 2.3V(typ). Hysteresis prevents the part from turning off during power up if
VIN is non-monotonic.
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FIGURE 6. VBOOST Derived from VIN
CURRENT LIMIT
The LMR12010 uses cycle-by-cycle current limiting to protect
the output switch. During each switching cycle, a current limit
comparator detects if the output switch current exceeds 1.7A
(typ), and turns off the switch until the next switching cycle
begins.
THERMAL SHUTDOWN
Thermal shutdown limits total power dissipation by turning off
the output switch when the IC junction temperature exceeds
165°C. After thermal shutdown occurs, the output switch
doesn’t turn on until the junction temperature drops to approximately 150°C.
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LMR12010
Now that the ripple current or ripple ratio is determined, the
inductance is calculated by:
Design Guide
INDUCTOR SELECTION
The Duty Cycle (D) can be approximated quickly using the
ratio of output voltage (VO) to input voltage (VIN):
where fs is the switching frequency and IO is the output current. When selecting an inductor, make sure that it is capable
of supporting the peak output current without saturating. Inductor saturation will result in a sudden reduction in inductance and prevent the regulator from operating correctly.
Because of the speed of the internal current limit, the peak
current of the inductor need only be specified for the required
maximum output current. For example, if the designed maximum output current is 0.5A and the peak current is 0.7A, then
the inductor should be specified with a saturation current limit
of >0.7A. There is no need to specify the saturation or peak
current of the inductor at the 1.7A typical switch current limit.
The difference in inductor size is a factor of 5. Because of the
operating frequency of the LMR12010, ferrite based inductors
are preferred to minimize core losses. This presents little restriction since the variety of ferrite based inductors is huge.
Lastly, inductors with lower series resistance (DCR) will provide better operating efficiency. For recommended inductors
see Example Circuits.
The catch diode (D1) forward voltage drop and the voltage
drop across the internal NMOS must be included to calculate
a more accurate duty cycle. Calculate D by using the following
formula:
VSW can be approximated by:
VSW = IO x RDS(ON)
The diode forward drop (VD) can range from 0.3V to 0.7V depending on the quality of the diode. The lower VD is, the higher
the operating efficiency of the converter.
The inductor value determines the output ripple current. Lower inductor values decrease the size of the inductor, but
increase the output ripple current. An increase in the inductor
value will decrease the output ripple current. The ratio of ripple
current (ΔiL) to output current (IO) is optimized when it is set
between 0.3 and 0.4 at 1A. The ratio r is defined as:
INPUT CAPACITOR
An input capacitor is necessary to ensure that VIN does not
drop excessively during switching transients. The primary
specifications of the input capacitor are capacitance, voltage,
RMS current rating, and ESL (Equivalent Series Inductance).
The recommended input capacitance is 10µF, although 4.7µF
works well for input voltages below 6V. The input voltage rating is specifically stated by the capacitor manufacturer. Make
sure to check any recommended deratings and also verify if
there is any significant change in capacitance at the operating
input voltage and the operating temperature. The input capacitor maximum RMS input current rating (IRMS-IN) must be
greater than:
One must also ensure that the minimum current limit (1.2A)
is not exceeded, so the peak current in the inductor must be
calculated. The peak current (ILPK) in the inductor is calculated
by:
ILPK = IO + ΔIL/2
If r = 0.5 at an output of 1A, the peak current in the inductor
will be 1.25A. The minimum guaranteed current limit over all
operating conditions is 1.2A. One can either reduce r to 0.4
resulting in a 1.2A peak current, or make the engineering
judgement that 50mA over will be safe enough with a 1.7A
typical current limit and 6 sigma limits. When the designed
maximum output current is reduced, the ratio r can be increased. At a current of 0.1A, r can be made as high as 0.9.
The ripple ratio can be increased at lighter loads because the
net ripple is actually quite low, and if r remains constant the
inductor value can be made quite large. An equation empirically developed for the maximum ripple ratio at any current
below 2A is:
It can be shown from the above equation that maximum RMS
capacitor current occurs when D = 0.5. Always calculate the
RMS at the point where the duty cycle, D, is closest to 0.5.
The ESL of an input capacitor is usually determined by the
effective cross sectional area of the current path. A large
leaded capacitor will have high ESL and a 0805 ceramic chip
capacitor will have very low ESL. At the operating frequencies
of the LMR12010, certain capacitors may have an ESL so
large that the resulting impedance (2πfL) will be higher than
that required to provide stable operation. As a result, surface
mount capacitors are strongly recommended. Sanyo
POSCAP, Tantalum or Niobium, Panasonic SP or Cornell
Dubilier ESR, and multilayer ceramic capacitors (MLCC) are
all good choices for both input and output capacitors and have
very low ESL. For MLCCs it is recommended to use X7R or
X5R dielectrics. Consult capacitor manufacturer datasheet to
see how rated capacitance varies over operating conditions.
r = 0.387 x IOUT-0.3667
Note that this is just a guideline.
The LMR12010 operates at frequencies allowing the use of
ceramic output capacitors without compromising transient response. Ceramic capacitors allow higher inductor ripple without significantly increasing output ripple. See the output
capacitor section for more details on calculating output voltage ripple.
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OUTPUT CAPACITOR
The output capacitor is selected based upon the desired output ripple and transient response. The initial current of a load
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PCB Layout Considerations
When planning layout there are a few things to consider when
trying to achieve a clean, regulated output. The most important consideration when completing the layout is the close
coupling of the GND connections of the CIN capacitor and the
catch diode D1. These ground ends should be close to one
another and be connected to the GND plane with at least two
through-holes. Place these components as close to the IC as
possible. Next in importance is the location of the GND connection of the COUT capacitor, which should be near the GND
connections of CIN and D1.
There should be a continuous ground plane on the bottom
layer of a two-layer board except under the switching node
island.
The FB pin is a high impedance node and care should be
taken to make the FB trace short to avoid noise pickup and
inaccurate regulation. The feedback resistors should be
placed as close as possible to the IC, with the GND of R2
placed as close as possible to the GND of the IC. The VOUT
trace to R1 should be routed away from the inductor and any
other traces that are switching.
High AC currents flow through the VIN, SW and VOUT traces,
so they should be as short and wide as possible. However,
making the traces wide increases radiated noise, so the designer must make this trade-off. Radiated noise can be decreased by choosing a shielded inductor.
The remaining components should also be placed as close
as possible to the IC. Refer to the LMR12010 demo board as
an example of a good layout.
When using MLCCs, the ESR is typically so low that the capacitive ripple may dominate. When this occurs, the output
ripple will be approximately sinusoidal and 90° phase shifted
from the switching action. Given the availability and quality of
MLCCs and the expected output voltage of designs using the
LMR12010, there is really no need to review any other capacitor technologies. Another benefit of ceramic capacitors is
their ability to bypass high frequency noise. A certain amount
of switching edge noise will couple through parasitic capacitances in the inductor to the output. A ceramic capacitor will
bypass this noise while a tantalum will not. Since the output
capacitor is one of the two external components that control
the stability of the regulator control loop, most applications will
require a minimum at 10 µF of output capacitance. Capacitance can be increased significantly with little detriment to the
regulator stability. Like the input capacitor, recommended
multilayer ceramic capacitors are X7R or X5R. Again, verify
actual capacitance at the desired operating voltage and temperature.
Check the RMS current rating of the capacitor. The RMS current rating of the capacitor chosen must also meet the following condition:
Calculating Efficiency, and Junction
Temperature
CATCH DIODE
The catch diode (D1) conducts during the switch off-time. A
Schottky diode is recommended for its fast switching times
and low forward voltage drop. The catch diode should be
chosen so that its current rating is greater than:
The complete LMR12010 DC/DC converter efficiency can be
calculated in the following manner.
ID1 = IO x (1-D)
The reverse breakdown rating of the diode must be at least
the maximum input voltage plus appropriate margin. To improve efficiency choose a Schottky diode with a low forward
voltage drop.
Or
BOOST DIODE
A standard diode such as the 1N4148 type is recommended.
For VBOOST circuits derived from voltages less than 3.3V, a
small-signal Schottky diode is recommended for greater efficiency. A good choice is the BAT54 small signal diode.
Calculations for determining the most significant power losses are shown below. Other losses totaling less than 2% are
not discussed.
Power loss (PLOSS) is the sum of two basic types of losses in
the converter, switching and conduction. Conduction losses
usually dominate at higher output loads, where as switching
losses remain relatively fixed and dominate at lower output
loads. The first step in determining the losses is to calculate
the duty cycle (D).
BOOST CAPACITOR
A ceramic 0.01µF capacitor with a voltage rating of at least
6.3V is sufficient. The X7R and X5R MLCCs provide the best
performance.
OUTPUT VOLTAGE
The output voltage is set using the following equation where
R2 is connected between the FB pin and GND, and R1 is
connected between VO and the FB pin. A good value for R2
is 10kΩ.
VSW is the voltage drop across the internal NFET when it is
on, and is equal to:
VSW = IOUT x RDSON
11
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LMR12010
transient is provided mainly by the output capacitor. The output ripple of the converter is:
LMR12010
VD is the forward voltage drop across the Schottky diode. It
can be obtained from the Electrical Characteristics section. If
the voltage drop across the inductor (VDCR) is accounted for,
the equation becomes:
The simplest means to determine this loss is to empirically
measuring the rise and fall times (10% to 90%) of the switch
at the switch node:
PSWF = 1/2(VIN x IOUT x freq x TFALL)
PSWR = 1/2(VIN x IOUT x freq x TRISE)
PSW = PSWF + PSWR
Typical Rise and Fall Times vs Input Voltage
This usually gives only a minor duty cycle change, and has
been omitted in the examples for simplicity.
The conduction losses in the free-wheeling Schottky diode
are calculated as follows:
PDIODE = VD x IOUT(1-D)
TFALL
5V
8ns
4ns
10V
9ns
6ns
15V
10ns
7ns
PQ = IQ x VIN
IQ is the quiescent operating current, and is typically around
1.5mA. The other operating power that needs to be calculated
is that required to drive the internal NFET:
PIND = IOUT2 x RDCR
PBOOST = IBOOST x VBOOST
The LMR12010 conduction loss is mainly associated with the
internal NFET:
PCOND =
TRISE
Another loss is the power required for operation of the internal
circuitry:
Often this is the single most significant power loss in the circuit. Care should be taken to choose a Schottky diode that
has a low forward voltage drop.
Another significant external power loss is the conduction loss
in the output inductor. The equation can be simplified to:
IOUT2
VIN
VBOOST is normally between 3VDC and 5VDC. The IBOOST rms
current is approximately 4.25mA. Total power losses are:
x RDSON x D
Switching losses are also associated with the internal NFET.
They occur during the switch on and off transition periods,
where voltages and currents overlap resulting in power loss.
Design Example 1:
Operating Conditions
VIN
5.0V
POUT
2.5W
VOUT
2.5V
PDIODE
151mW
IOUT
1.0A
PIND
75mW
VD
0.35V
PSWF
53mW
Freq
3MHz
PSWR
53mW
IQ
1.5mA
PCOND
187mW
TRISE
8ns
PQ
7.5mW
TFALL
8ns
PBOOST
21mW
RDSON
330mΩ
PLOSS
548mW
INDDCR
75mΩ
D
0.568
η = 82%
Calculating the LMR12010 Junction Temperature
RθJC = Thermal resistance from chip junction to device case
RθJA = Thermal resistance from chip junction to ambient air
Thermal Definitions:
TJ = Chip junction temperature
TA = Ambient temperature
www.national.com
12
LMR12010
30166573
FIGURE 8. Cross-Sectional View of Integrated Circuit Mounted on a Printed Circuit Board.
ature, which can be empirically measured on the bench we
have:
Heat in the LMR12010 due to internal power dissipation is
removed through conduction and/or convection.
Conduction: Heat transfer occurs through cross sectional areas of material. Depending on the material, the transfer of
heat can be considered to have poor to good thermal conductivity properties (insulator vs conductor).
Heat Transfer goes as:
silicon→package→lead frame→PCB.
Convection: Heat transfer is by means of airflow. This could
be from a fan or natural convection. Natural convection occurs
when air currents rise from the hot device to cooler air.
Thermal impedance is defined as:
Therefore:
TJ = (RθJC x PLOSS) + TC
Design Example 2:
Operating Conditions
Thermal impedance from the silicon junction to the ambient
air is defined as:
This impedance can vary depending on the thermal properties of the PCB. This includes PCB size, weight of copper
used to route traces and ground plane, and number of layers
within the PCB. The type and number of thermal vias can also
make a large difference in the thermal impedance. Thermal
vias are necessary in most applications. They conduct heat
from the surface of the PCB to the ground plane. Place two
to four thermal vias close to the ground pin of the device.
The datasheet specifies two different RθJA numbers for the
Thin SOT23–6 package. The two numbers show the difference in thermal impedance for a four-layer board with 2oz.
copper traces, vs. a four-layer board with 1oz. copper. RθJA
equals 120°C/W for 2oz. copper traces and GND plane, and
235°C/W for 1oz. copper traces and GND plane.
Method 1:
To accurately measure the silicon temperature for a given
application, two methods can be used. The first method requires the user to know the thermal impedance of the silicon
junction to case. (RθJC) is approximately 80°C/W for the Thin
SOT23-6 package. Knowing the internal dissipation from the
efficiency calculation given previously, and the case temper-
VIN
5.0V
POUT
2.5W
VOUT
2.5V
PDIODE
151mW
IOUT
1.0A
PIND
75mW
VD
0.35V
PSWF
53mW
Freq
3MHz
PSWR
53mW
IQ
1.5mA
PCOND
187mW
TRISE
8ns
PQ
7.5mW
TFALL
8ns
PBOOST
21mW
RDSON
330mΩ
PLOSS
548mW
INDDCR
75mΩ
D
0.568
The second method can give a very accurate silicon junction
temperature. The first step is to determine RθJA of the application. The LMR12010 has over-temperature protection circuitry. When the silicon temperature reaches 165°C, the
device stops switching. The protection circuitry has a hysteresis of 15°C. Once the silicon temperature has decreased
to approximately 150°C, the device will start to switch again.
Knowing this, the RθJA for any PCB can be characterized during the early stages of the design by raising the ambient
temperature in the given application until the circuit enters
thermal shutdown. If the SW-pin is monitored, it will be obvi13
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LMR12010
ous when the internal NFET stops switching indicating a
junction temperature of 165°C. Knowing the internal power
dissipation from the above methods, the junction temperature
and the ambient temperature, RθJA can be determined.
TFALL
8ns
RDSON
400mΩ
INDDCR
75mΩ
D
30.3%
Once this is determined, the maximum ambient temperature
allowed for a desired junction temperature can be found.
Using a standard National Semiconductor Thin SOT23-6
demonstration board to determine the RθJA of the board. The
four layer PCB is constructed using FR4 with 1/2oz copper
traces. The copper ground plane is on the bottom layer. The
ground plane is accessed by two vias. The board measures
2.5cm x 3cm. It was placed in an oven with no forced airflow.
The ambient temperature was raised to 94°C, and at that
temperature, the device went into thermal shutdown.
Design Example 3:
Operating Conditions
Package
SOT23-6
VIN
12.0V
POUT
2.475W
VOUT
3.30V
PDIODE
523mW
IOUT
750mA
PIND
56.25mW
VD
0.35V
PSWF
108mW
Freq
3MHz
PSWR
108mW
IQ
1.5mA
PCOND
68.2mW
IBOOST
4mA
PQ
18mW
VBOOST
5V
PBOOST
20mW
TRISE
8ns
PLOSS
902mW
www.national.com
If the junction temperature was to be kept below 125°C, then
the ambient temperature cannot go above 54.2°C.
TJ - (RθJA x PLOSS) = TA
14
LMR12010
Physical Dimensions inches (millimeters) unless otherwise noted
6-Lead TSOT Package
NS Package Number MK06A
15
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LMR12010 SIMPLE SWITCHER 20Vin, 1A Step-Down Voltage Regulator in SOT-23
Notes
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